CN112909072B - Transient voltage suppression diode structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a transient voltage suppression diode structure and a manufacturing method thereof. The transient voltage suppression diode structure comprises a substrate, an N-type epitaxial layer, a first metal layer, a first N+ type injection layer, a deep N+ type injection layer and a plurality of polycrystalline columns. The N-type epitaxial layer is arranged on the substrate, the first metal layer is arranged on the N-type epitaxial layer and assembled to form a working voltage end, the first N+ type injection layer is embedded in the N-type epitaxial layer in a space corresponding to the working voltage end and assembled to be connected to the working voltage end, the deep N+ type injection layer is embedded in the N-type epitaxial layer in a space corresponding to the working voltage end, and a spacing distance is reserved between the deep N+ type injection layer and the first N+ type injection layer. The polycrystalline columns are embedded in the N-type epitaxial layer and penetrate through the first N+ type injection layer, and the polycrystalline columns are connected between the working voltage end of the first metal layer and the deep N+ type injection layer.

Description

Transient voltage suppression diode structure and manufacturing method thereof

Technical Field

The invention relates to a diode structure, and in particular to a transient voltage suppression diode structure and a manufacturing method thereof.

Background Art

Transient voltage suppression diodes, also known as TVS diodes, are protective electronic components that can protect electrical equipment from voltage spikes introduced by wires. In recent years, as electronic systems have become more sophisticated, the demand for TVS components has become more urgent.

Traditional TVS components use Zener diodes to guide current after component breakdown, so that it does not flow into the protected circuit. Zener diodes have characteristics such as large leakage current and large junction capacitance. Among them, Zener diodes used in TVS components tend to be developed for low voltage applications.

FIG1 discloses a cross-sectional view of a known transient voltage suppression diode structure. It uses a Zener diode as a protection mechanism for the transient voltage suppression diode component. As shown in the figure, the structure of the TVS component 1 is stacked in sequence with a bottom metal layer 11 connected to the ground terminal GND, a P+ type base layer 12, an N-type epitaxial layer 13, an N+ type buried layer 14, an N-type epitaxial layer 15, a dielectric layer (interlayer dielectric, ILD) 16, a top metal layer 17 and a passivation layer 18. The top metal layer 17 is assembled to form an input/output terminal I/O and a working voltage terminal Vcc. Under the input/output terminal I/O, an N+ type injection layer 20 and a P+ type injection layer 21 are correspondingly arranged, embedded in the N-type epitaxial layer 15, and connected to the input/output terminal I/O. Under the working voltage terminal Vcc, an N+ type injection layer 22 and a deep N+ type injection layer 23 are correspondingly arranged, embedded in the N-type epitaxial layer 15, and isolated by an oxidized insulating portion 19. It is worth noting that in the structure of the conventional TVS device 1, the voltage of the working voltage terminal Vcc is related to the Zener diode constructed by the P+ type base layer 12 and the N type epitaxial layer 13. However, when the thickness of the N-type epitaxial layer 15 is very thick, it is not easy to increase the concentration of the N+ type injection layer 22 and the deep N+ type injection layer 23 in the N-type epitaxial layer 15 through the general doping and drive-in process to obtain a Zener diode structure with a low breakdown voltage.

In view of this, it is necessary to provide a transient voltage suppression diode structure and a manufacturing method thereof to solve the above-mentioned problems and obtain a Zener diode structure with a low breakdown voltage.

Summary of the invention

The object of the present invention is to provide a transient voltage suppressor diode structure and a manufacturing method thereof. By introducing multiple polycrystalline column structures, the problem of difficult control and increase of concentration in the general doping and driving process of the transient voltage suppressor diode structure is solved. The polycrystalline column structure can further reduce the distance of deep injection, avoid the problem of concentration reduction after driving, and effectively reduce the difficulty of the process. In addition, the polycrystalline column structure can further reduce the parasitic resistance of, for example, an N-type epitaxial layer, further improving the performance of the transient voltage suppressor diode structure.

To achieve the above-mentioned purpose, the present invention provides a transient voltage suppression diode structure. It includes a substrate, at least one N-type epitaxial layer, a first metal layer, a first N+ type injection layer, a deep N+ type injection layer and a plurality of polycrystalline columns. At least one N-type epitaxial layer is disposed on the substrate. The first metal layer is disposed on at least one N-type epitaxial layer and is assembled to form an operating voltage terminal. The first N+ type injection layer corresponds to the operating voltage terminal in space, is embedded in at least one N-type epitaxial layer, and is assembled and connected to the operating voltage terminal of the first metal layer. The deep N+ type injection layer corresponds to the operating voltage terminal in space, is embedded in at least one N-type epitaxial layer, and has a spacing distance between it and the first N+ type injection layer. A plurality of polycrystalline columns spatially correspond to the working voltage end, are embedded in at least one N-type epitaxial layer, and penetrate the first N+ type injection layer, wherein each polycrystalline column has a first end and a second end opposite to each other, the first end is in contact with the working voltage end of the first metal layer, and the second end at least partially penetrates the deep N+ type injection layer and is in contact with the deep N+ type injection layer.

In one embodiment, the substrate includes a P+ type base layer, and an N type epitaxial layer disposed on the P+ type base layer and connected to at least one N- type epitaxial layer.

In one embodiment, the substrate further includes a second metal layer connected to the P+ type base layer, opposite to the first metal layer, and assembled to form a ground terminal.

In one embodiment, the transient voltage suppression diode structure further includes a dielectric layer disposed between the at least one N-type epitaxial layer and the first metal layer.

In one embodiment, the first metal layer is also assembled to form an input and output terminal, and the transient voltage suppression diode structure also includes a second N+ type injection layer and a P+ type injection layer, which are respectively embedded in at least one N-type epitaxial layer, wherein the input and output terminals of the first metal layer are respectively connected to the second N+ type injection layer and the P+ type injection layer through the dielectric layer.

In one embodiment, the TVS diode structure further includes an N+ buried layer disposed between the N epitaxial layer and at least one N- epitaxial layer, and the N+ buried layer spatially corresponds to the P+ implanted layer and the plurality of polycrystalline pillars.

In one embodiment, the transient voltage suppression diode structure further includes a protection layer disposed on the first metal layer and partially exposing the first metal layer to respectively define the working voltage terminal and the input and output terminals.

In one embodiment, at least one oxide insulating portion is disposed between the second N+ type injection layer and the P+ type injection layer, and the at least one oxide insulating portion penetrates at least one N- type epitaxial layer, the N type epitaxial layer and a portion of the P+ type base layer.

To achieve the above-mentioned object, the present invention further provides a method for manufacturing a transient voltage suppressor diode structure, which comprises the following steps: (a) providing a substrate; (b) forming at least one N-type epitaxial layer disposed on the substrate; (c) forming a first N+ type injection layer embedded in the at least one N-type epitaxial layer; (d) partially etching the at least one N-type epitaxial layer and the first N+ type injection layer to form a plurality of columnar grooves penetrating the first N+ type injection layer and a portion of the at least one N-type epitaxial layer; (e) forming a deep N+ type injection layer embedded in the at least one N-type epitaxial layer and having a spacing distance between the deep N+ type injection layer and the first N+ type injection layer; f) filling a plurality of columnar grooves with a polysilicon material to form a plurality of polycrystalline pillars, which are embedded in at least one N-type epitaxial layer and penetrate the first N+ type injection layer; and (g) forming a first metal layer, which is disposed on at least one N-type epitaxial layer, wherein the first metal layer is assembled to form an operating voltage end at a location spatially corresponding to the first N+ type injection layer, the plurality of polycrystalline pillars and the deep N+ type injection layer, wherein each polycrystalline pillar has a first end and a second end opposite to each other, the first end is in contact with the operating voltage end of the first metal layer, and the second end at least partially penetrates the deep N+ type injection layer and is in contact with the deep N+ type injection layer.

In one embodiment, step (b) further includes step (b0) of forming an N+ type buried layer, wherein the N+ type buried layer is disposed between the substrate and at least one N- type epitaxial layer.

In one embodiment, step (c) also includes step (c0) of forming a second N+ type injection layer and a P+ type injection layer, which are embedded in at least one N-type epitaxial layer, wherein the first metal layer is assembled to form an input-output end at a location corresponding to the second N+ type injection layer and the P+ type injection layer in space, wherein the input-output end of the first metal layer is respectively connected to the second N+ type injection layer and the P+ type injection layer through a dielectric layer.

In one embodiment, the method for manufacturing a transient voltage suppressor diode structure further includes step (h) forming a protection layer disposed on the first metal layer and partially exposing the first metal layer to respectively define the operating voltage terminal and the input and output terminals.

In one embodiment, the substrate includes a P+ type base layer and an N type epitaxial layer, wherein the N type epitaxial layer is disposed on the P+ type base layer, and at least one N- type epitaxial layer is formed on the N type epitaxial layer.

In one embodiment, step (d) also includes step (d0) of partially etching at least one N-type epitaxial layer and the substrate, and filling an oxide to form at least one oxidized insulating portion, wherein the at least one oxidized insulating portion penetrates at least one N-type epitaxial layer, the N-type epitaxial layer and a portion of the P+ type base layer.

In one embodiment, step (d) further includes step (d1) of forming a dielectric layer disposed on at least one N-type epitaxial layer.

In one embodiment, the manufacturing method further includes step (i) forming a second metal layer connected to the P+ type base layer, opposite to the first metal layer, and assembled to form a ground terminal.

The beneficial effect of the present invention is that the present invention provides a transient voltage suppression diode structure and a manufacturing method thereof. By introducing multiple polycrystalline column structures, the problem of difficult control and increase of concentration in the transient voltage suppression diode structure in general doping and driving procedures is solved. The polycrystalline column structure can further reduce the distance of deep injection, avoid the problem of concentration reduction after driving, and effectively reduce the difficulty of the process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 discloses a cross-sectional view of a known transient voltage suppressor diode structure.

FIG. 2 discloses a transient voltage suppression diode structure according to a preferred embodiment of the present invention.

3A to 3I disclose a schematic diagram of the manufacturing process of a transient voltage suppression diode structure according to a preferred embodiment of the present invention.

FIG. 4 discloses a flow chart of a method for manufacturing a transient voltage suppression diode structure according to a preferred embodiment of the present invention.

The reference numerals are as follows:

1: TVS components

11: Bottom metal layer

12: P+ type base

13: N-type epitaxial layer

14: N+ type buried layer

15: N-type epitaxial layer

16: Dielectric layer

17: Top metal layer

18: Protective layer

19: Oxidation insulation

20: N+ type injection layer

21: P+ type injection layer

22: N+ type injection layer

23: Deep N+ type injection layer

3: Transient Voltage Suppression Diode Structure

30: Substrate

31: Second metal layer

32: P+ type base

33: N-type epitaxial layer

34: N+ type buried layer

35: N-type epitaxial layer

36: Dielectric layer

37: First Metal

38: Protective layer

39: Oxidation insulation

40: Second N+ type injection layer

41: P+ type injection layer

42: First N+ type injection layer

43: Deep N+ type injection layer

44: Polycrystalline column

44a: First end

44b: Second end

44c: Columnar groove

D: Interval

GND: Ground terminal

I/O: Input and output

Vcc: working voltage terminal

S1～S10: Steps

DETAILED DESCRIPTION

Some typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can be varied in various ways without departing from the scope of the present invention, and the description and drawings are essentially for illustrative purposes rather than for limiting the present invention.

FIG2 discloses a transient voltage suppressor diode structure of a preferred embodiment of the present invention. In this embodiment, the transient voltage suppressor diode structure 3 includes a substrate 30, at least one N-type epitaxial layer 35, a first metal 37, a first N+ type injection layer 42, a deep N+ type injection layer 43 and a plurality of polycrystalline pillars 44. At least one N-type epitaxial layer 35 is disposed on the substrate 30. In this embodiment, the substrate 30 includes, for example, a P+ type base layer 32 and an N-type epitaxial layer 33. The N-type epitaxial layer 33 is disposed on the P+ type base layer 32 and is connected to the at least one N-type epitaxial layer 35. In addition, the transient voltage suppressor diode structure 3 also includes an N+ type buried layer 34 disposed between the N-type epitaxial layer 33 and the at least one N-type epitaxial layer 35. The first metal layer 37 is disposed on the at least one N-type epitaxial layer 35 and is assembled to form a working voltage terminal Vcc and an input/output terminal I/O. In this embodiment, a dielectric layer 36 is further disposed between the first metal layer 37 and the at least one N-type epitaxial layer 35 , but the invention is not limited thereto.

In the present embodiment, the transient voltage suppression diode structure 3 further includes a protection layer 38, which is disposed on the first metal layer 37 and partially exposes the first metal layer 37 to respectively define the working voltage terminal Vcc and the input/output terminal I/O. Of course, the present invention is not limited thereto. In the present embodiment, the structures of the first N+ type injection layer 42, the deep N+ type injection layer 43 and the plurality of polycrystalline pillars 44 all correspond to the working voltage terminal Vcc of the first metal layer 37. In the present embodiment, the first N+ type injection layer 42 corresponds to the working voltage terminal Vcc in space, is embedded in at least one N-type epitaxial layer 35, and is assembled and connected to the working voltage terminal Vcc of the first metal layer 37. The deep N+ type injection layer 43 corresponds to the working voltage terminal Vcc of the first metal layer 37 in space, is embedded in at least one N-type epitaxial layer 35, and is connected to the N+ type buried layer 34, and has a spacing distance D between it and the first N+ type injection layer 42. In other words, compared with the first N+ type implantation layer 42 , the deep N+ type implantation layer 43 is further embedded in at least one N− type epitaxial layer 35 at a spacing distance D and connected to the N+ type buried layer 34 .

It is worth noting that a plurality of polycrystalline pillars 44 are spatially corresponding to the working voltage terminal Vcc of the first metal layer 37, are embedded in at least one N-type epitaxial layer 35, and penetrate the dielectric layer 36 and the first N+ type injection layer 42. Each polycrystalline pillar 44 has a first end 44a and a second end 44b opposite to each other, the first end 44a is in contact with and connected to the working voltage terminal Vcc of the first metal layer 37, and the second end 44b at least partially penetrates the deep N+ type injection layer 43 and is in contact with and connected to the deep N+ type injection layer 43. The structure of the polycrystalline pillar 44 penetrates the first N+ type injection layer 42, and through the general doping and drive-in process, it is helpful to control and increase the concentration of the deep N+ type injection layer 43 in at least one N-type epitaxial layer 35, so as to obtain a low voltage Zener diode structure. In addition, the deep N+ type injection layer 43 can be electrically connected through the structure of multiple polycrystalline pillars 44, which helps to reduce the parasitic resistance of at least one N-type epitaxial layer 35. In other words, by introducing multiple polycrystalline pillars 44 structures, the problem of the concentration of the deep N+ type injection layer 43 being difficult to control and increase in the general doping and driving process of the transient voltage suppression diode structure 3 is solved, and at the same time, the deep injection distance of the deep N+ type injection layer 43 is reduced to avoid the problem of concentration reduction after driving, effectively reducing the difficulty of the process. In addition, the structure of the polycrystalline pillars 44 further reduces the parasitic resistance of the N-type epitaxial layer 35, further improving the performance of the transient voltage suppression diode structure 3.

In this embodiment, the substrate 30 further includes a second metal layer 31, connected to the P+ type base layer 32, opposite to the first metal layer 37, and assembled to form a ground terminal GND. On the other hand, it should be noted that, corresponding to the input and output terminals I/O of the first metal layer 37, the transient voltage suppression diode structure 3 further includes a second N+ type injection layer 40 and a P+ type injection layer 41, which are respectively embedded in the at least one N-type epitaxial layer 35. The input and output terminals I/O of the first metal layer 37 are respectively connected to the second N+ type injection layer 40 and the P+ type injection layer 41 through the dielectric layer 36. In addition, the N+ type buried layer 34 corresponds to the P+ type injection layer 41 and the plurality of polycrystalline pillars 44 in space. In the present embodiment, at least one oxide insulating portion 39 is further provided between the second N+ type injection layer 40 and the P+ type injection layer 41, and the at least one oxide insulating portion 39 groove penetrates at least one N-type epitaxial layer 35, the N-type epitaxial layer 33 and a portion of the P+ type base layer 32. In addition, at least one oxide insulating portion 39 can also be used as a boundary defining the transient voltage suppression diode structure 3, but it is not a necessary technical feature to limit the present invention and is not described in detail here. It should be noted that the number and relative positions of the P+ type injection layer 41, the second N+ type injection layer 40, the plurality of polycrystalline pillars 44 and the oxide insulating portion 39 can be modulated according to actual application requirements, and the present invention is not limited thereto.

Corresponding to the above-mentioned transient voltage suppression diode structure 3, the present invention also discloses a manufacturing method of a transient voltage suppression diode structure 3. FIG. 3A to FIG. 3I disclose a schematic diagram of the manufacturing process of the transient voltage suppression diode structure of a preferred embodiment of the present invention. FIG. 4 discloses a flow chart of the manufacturing method of the transient voltage suppression diode structure of a preferred embodiment of the present invention. Refer to FIG. 2, FIG. 3A to FIG. 3I and FIG. 4. First, in step S1, a substrate 30 is provided. As shown in FIG. 3A, the substrate 30 includes a P+ type base layer 32 and an N type epitaxial layer 33, wherein the N type epitaxial layer 33 is disposed on the P+ type base layer 32. Next, in step S2, an N+ type buried layer 34 is formed on the N type epitaxial layer 33 by using a process such as implant and drive-in, as shown in FIG. 3B. In step S3, at least one N-type epitaxial layer 35 is formed and disposed on the N-type epitaxial layer 33 of the substrate 30, and the N+ type buried layer 34 is disposed between the N-type epitaxial layer 33 of the substrate 30 and the at least one N-type epitaxial layer 35, and the N-type epitaxial layer 33 is connected to the at least one N-type epitaxial layer 35, as shown in FIG. 3C.

Then, in step S4, a first N+ type implantation layer 42, a second N+ type implantation layer 40 and a P+ type implantation layer 41 are respectively formed on at least one N-type epitaxial layer 35 by a process such as implantation, and are embedded in at least one N-type epitaxial layer 35, as shown in FIG3D. The position of the first N+ type implantation layer 42 corresponds to an operating voltage terminal Vcc; and the positions of the second N+ type implantation layer 40 and the P+ type implantation layer 41 correspond to an input/output terminal I/O (see FIG2). In step S5, an etching process is used to partially etch at least one N-type epitaxial layer 35 and the substrate 30, and fill an oxide to form at least one oxide insulating portion 39, as shown in FIG3E. At least one oxide insulating portion 39 penetrates at least one N-type epitaxial layer 35, the N+ type buried layer 34, the N-type epitaxial layer 33 and a portion of the P+ type base layer 32. In this embodiment, a dielectric layer 36 is further formed on at least one N-type epitaxial layer 35. The dielectric layer 36 is used to define the connection region of the first N+ type implantation layer 42, the second N+ type implantation layer 40 and the P+ type implantation layer 41, but the present invention is not limited thereto.

Then, in step S6, an etching process is used to partially etch at least one N-type epitaxial layer 35 and the first N+ type injection layer 42 to form a plurality of columnar grooves 44c, which penetrate the first N+ type injection layer 42 and a portion of at least one N-type epitaxial layer 35, as shown in FIG3F. In step S7, an injection process is performed through each columnar groove 44c to form a deep N+ type injection layer 43 at the bottom of the columnar groove 44c. The deep N+ type injection layer 43 is embedded in at least one N-type epitaxial layer 35 and maintains a spacing distance D with the first N+ type injection layer 42, as shown in FIG3G. It should be noted that the injection process performed through a plurality of columnar grooves 44c can reduce the distance of the deep N+ type injection layer 43 deep injection, solve the problem of difficult control and increase of injection concentration, and at the same time, avoid the problem of concentration reduction after driving, effectively reducing the difficulty of the process. Thereafter, in step S8, a plurality of columnar grooves 44c are filled with a polysilicon material, and then, for example, the excess polysilicon material is removed by an etch-back process to form a plurality of polycrystalline pillars 44, which are embedded in at least one N-type epitaxial layer 35 and penetrate the first N+ type implantation layer 42, as shown in FIG3H. In this embodiment, the drive-in process of the deep N+ type implantation layer 43, the first N+ type implantation layer 42, the second N+ type implantation layer 40, and the P+ type implantation layer 41 can be performed after the polycrystalline pillars 44 are formed, but the present invention is not limited thereto. It is worth noting that since the polycrystalline pillars 44 are connected between the deep N+ type implantation layer 43 and the first N+ type implantation layer 42, it helps to reduce the parasitic resistance of the N-type epitaxial layer 35, and further improve the performance of the transient voltage suppressor diode structure 3.

Finally, in step S9, a first metal layer 37 is formed and disposed on at least one N-type epitaxial layer 35 and the dielectric layer 36. The first metal layer 37 is assembled to form an operating voltage terminal Vcc at a location corresponding to the first N+ type injection layer 42, a plurality of polycrystalline pillars 44, and the deep N+ type injection layer 43 in space. Each polycrystalline pillar 44 has a first end 44a and a second end 44b opposite to each other, the first end 44a is in contact with and connected to the operating voltage terminal Vcc of the first metal layer 37, and the second end 44b at least partially penetrates the deep N+ type injection layer 43 and is in contact with and connected to the deep N+ type injection layer 43. In other embodiments, the dielectric layer 36 can be loaded before the first metal layer 37 is formed to define the region where the first metal layer 37 is connected to the first N+ type injection layer 42, the second N+ type injection layer 40, and the P+ type injection layer 41, and the present invention is not limited thereto.

In this embodiment, the manufacturing method of the transient voltage suppression diode structure 3 further includes step S10, i.e. forming a protective layer 38, which is disposed on the first metal layer 37, and partially exposing the first metal layer 37, so as to define the working voltage terminal Vcc and the input and output terminal I/O respectively, as shown in FIG3I. In addition, in addition to the first metal layer 37, a second metal layer 31 is formed on the other side opposite to the first metal layer 37, connected to the P+ type base layer 32 of the substrate 30, and assembled to form a ground terminal GND, as shown in FIG2. Of course, the formation of the dielectric 36, the first metal layer 37, the protective layer 38 and the second metal layer 31 can be modulated according to the actual application requirements, and the present invention is not limited thereto and will not be repeated.

In summary, the present invention provides a transient voltage suppressor diode structure and a manufacturing method thereof. By introducing multiple polycrystalline column structures, the problem of difficult control and increase of concentration in the general doping and driving process of the transient voltage suppressor diode structure is solved. The polycrystalline column structure can further reduce the distance of deep injection, avoid the problem of concentration reduction after driving, and effectively reduce the difficulty of the process. In addition, the polycrystalline column structure can further reduce the parasitic resistance (parasitic resistance) of, for example, an N-type epitaxial layer, further improving the performance of the transient voltage suppressor diode structure.

The present invention may be modified in various ways by those skilled in the art, but all of these modifications are within the protection scope of the appended claims.

Claims (16)

1. A transient voltage suppression diode structure, comprising: a substrate; At least one N-type epitaxial layer is disposed on the substrate; A first metal layer is disposed on the at least one N-type epitaxial layer and is assembled to form a working voltage terminal; A first N+ type implantation layer, spatially corresponding to the working voltage end, embedded in the at least one N- type epitaxial layer, and assembled and connected to the working voltage end of the first metal layer; a deep N+ type implantation layer, spatially corresponding to the working voltage end, embedded in the at least one N-type epitaxial layer, and having a spacing distance from the first N+ type implantation layer; and A plurality of polycrystalline columns are spatially corresponding to the operating voltage end, embedded in the at least one N-type epitaxial layer, and penetrate the first N+ type injection layer, wherein each of the polycrystalline columns has a first end and a second end opposite to each other, the first end is in contact with and connected to the operating voltage end of the first metal layer, and the second end at least partially penetrates the deep N+ type injection layer and is in contact with and connected to the deep N+ type injection layer. 2. The transient voltage suppression diode structure of claim 1, wherein the substrate comprises: A P+ type substrate, and An N-type epitaxial layer is disposed on the P+ type base layer and connected to the at least one N-type epitaxial layer. 3. The transient voltage suppression diode structure as claimed in claim 2, wherein the substrate further comprises a second metal layer connected to the P+ type base layer, opposite to the first metal layer, and assembled to form a ground terminal. 4 . The transient voltage suppression diode structure as claimed in claim 2 , further comprising a dielectric layer disposed between the at least one N-type epitaxial layer and the first metal layer. 5. The transient voltage suppression diode structure as described in claim 4, wherein the first metal layer is also assembled to form an input and output terminal, and the transient voltage suppression diode structure also includes a second N+ type injection layer and a P+ type injection layer, which are respectively embedded in the at least one N-type epitaxial layer, wherein the input and output terminals of the first metal layer are respectively connected to the second N+ type injection layer and the P+ type injection layer through the dielectric layer. 6. The transient voltage suppression diode structure as claimed in claim 5, further comprising an N+ type buried layer disposed between the N type epitaxial layer and the at least one N- type epitaxial layer, and the N+ type buried layer spatially corresponds to the P+ type implanted layer and the plurality of polycrystalline pillars. 7 . The transient voltage suppression diode structure as claimed in claim 5 , further comprising a protection layer disposed on the first metal layer and partially exposing the first metal layer to respectively define the working voltage terminal and the input and output terminals. 8. The transient voltage suppressor diode structure as claimed in claim 5, wherein at least one oxide insulating portion is further disposed between the second N+ type injection layer and the P+ type injection layer, and the at least one oxide insulating portion penetrates the at least one N-type epitaxial layer, the N-type epitaxial layer and a portion of the P+ type base layer. 9. A method for manufacturing a transient voltage suppression diode structure, comprising the steps of: (a) providing a substrate; (b) forming at least one N-type epitaxial layer disposed on the substrate; (c) forming a first N+ type implantation layer embedded in the at least one N- type epitaxial layer; (d) partially etching the at least one N-type epitaxial layer and the first N+ type implantation layer to form a plurality of columnar grooves penetrating the first N+ type implantation layer and a portion of the at least one N-type epitaxial layer; (e) forming a deep N+ type implantation layer embedded in the at least one N-type epitaxial layer and having a spacing distance between the deep N+ type implantation layer and the at least one N-type epitaxial layer; (f) filling the plurality of columnar trenches with a polysilicon material to form a plurality of polycrystalline columns embedded in the at least one N-type epitaxial layer and penetrating the first N+ type implantation layer; and (g) forming a first metal layer disposed on the at least one N-type epitaxial layer, wherein the first metal layer is spatially arranged to correspond to the first N+ type injection layer, the plurality of polycrystalline pillars and the deep N+ type injection layer to form an operating voltage end, wherein each of the polycrystalline pillars has a first end and a second end opposite to each other, the first end is in contact with and connected to the operating voltage end of the first metal layer, and the second end at least partially penetrates the deep N+ type injection layer and is in contact with and connected to the deep N+ type injection layer. 10. The method for manufacturing a transient voltage suppressor diode structure as claimed in claim 9, wherein the step (b) further comprises the steps of: (b0) forming an N+ type buried layer, wherein the N+ type buried layer is disposed between the substrate and the at least one N- type epitaxial layer. 11. The method for manufacturing a transient voltage suppressor diode structure as claimed in claim 9, wherein the step (c) further comprises the steps of: (c0) forming a second N+ type injection layer and a P+ type injection layer respectively, embedded in the at least one N-type epitaxial layer, wherein the first metal layer is assembled to form an input-output terminal at a location corresponding to the second N+ type injection layer and the P+ type injection layer in space, wherein the input-output terminal of the first metal layer is connected to the second N+ type injection layer and the P+ type injection layer respectively through a dielectric layer. 12. The method for manufacturing a transient voltage suppression diode structure according to claim 11, further comprising the steps of: (h) forming a protection layer disposed on the first metal layer and partially exposing the first metal layer to respectively define the working voltage terminal and the input/output terminal. 13. The method for manufacturing a transient voltage suppressor diode structure as claimed in claim 9, wherein the substrate comprises a P+ type base layer and an N type epitaxial layer, and the N type epitaxial layer is disposed on the P+ type base layer, and the at least one N- type epitaxial layer is formed on the N type epitaxial layer. 14. The method for manufacturing a transient voltage suppressor diode structure as claimed in claim 13, wherein the step (d) further comprises the steps of: (d0) Partially etching the at least one N-type epitaxial layer and the substrate, and filling with an oxide to form at least one oxidized insulating portion, wherein the at least one oxidized insulating portion penetrates the at least one N-type epitaxial layer, the N-type epitaxial layer and a portion of the P+ type base layer. 15. The method for manufacturing a transient voltage suppressor diode structure as claimed in claim 14, wherein the step (d) further comprises the steps of: (d1) forming a dielectric layer disposed on at least one N-type epitaxial layer. 16. The method for manufacturing a transient voltage suppressor diode structure according to claim 13, further comprising the steps of: (i) forming a second metal layer connected to the P+ type base layer, opposite to the first metal layer, and assembled to form a ground terminal.