CN113140611B - Transient voltage suppression diode structure and manufacturing method thereof - Google Patents
Transient voltage suppression diode structure and manufacturing method thereof Download PDFInfo
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- CN113140611B CN113140611B CN202010051940.9A CN202010051940A CN113140611B CN 113140611 B CN113140611 B CN 113140611B CN 202010051940 A CN202010051940 A CN 202010051940A CN 113140611 B CN113140611 B CN 113140611B
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- 230000001629 suppression Effects 0.000 title claims abstract description 17
- 230000001052 transient effect Effects 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 272
- 239000007943 implant Substances 0.000 claims description 47
- 238000002513 implantation Methods 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 42
- 238000002955 isolation Methods 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 34
- 229920005591 polysilicon Polymers 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 19
- 238000001312 dry etching Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 230000000149 penetrating effect Effects 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 description 12
- 238000001039 wet etching Methods 0.000 description 9
- 238000002161 passivation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/422—PN diodes having the PN junctions in mesas
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
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- H10D8/045—Manufacture or treatment of PN junction diodes
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Abstract
本公开提供一种瞬态电压抑制二极管结构及其制造方法。其结构包括P型基层板、N型外延层、P+型植入层、N+型植入层、深层沟渠部、介电质层以及第一金属层。N型外延层设置于P型基层板。P+型植入层与N+型植入层，嵌设于N型外延层上，且彼此分离设置。深层沟渠部贯穿N型外延层，且具有彼此相对的第一端与第二端。第一端插置于P型基层板。介电质层设置于N型外延层上。第一金属层设置于介电质层上，且通过介电质层而连接至P+型植入层、N+型植入层以及深层沟渠部的第二端。其中深层沟渠部连接第一金属层，且组配架构一硅控整流器。
The present disclosure provides a transient voltage suppression diode structure and a manufacturing method thereof. The structure includes a P-type base plate, an N-type epitaxial layer, a P+ type implanted layer, an N+ type implanted layer, a deep trench portion, a dielectric layer and a first metal layer. The N-type epitaxial layer is arranged on the P-type base plate. The P+ type implanted layer and the N+ type implanted layer are embedded in the N-type epitaxial layer and are arranged separately from each other. The deep trench portion penetrates the N-type epitaxial layer and has a first end and a second end opposite to each other. The first end is inserted into the P-type base plate. The dielectric layer is arranged on the N-type epitaxial layer. The first metal layer is arranged on the dielectric layer and is connected to the P+ type implanted layer, the N+ type implanted layer and the second end of the deep trench portion through the dielectric layer. The deep trench portion is connected to the first metal layer, and the assembly structure is a silicon-controlled rectifier.
Description
Technical Field
The present disclosure relates to diode structures, and more particularly to a transient voltage suppression diode structure and a method of manufacturing the same.
Background
The transient voltage suppression diode (TVS) is also called a transient-voltage-suppression (TVS) diode (TVS diode), and is an electronic component for protection, and can protect electrical equipment from being damaged by voltage spikes introduced by a lead. In recent years, with the trend of more sophisticated electronic systems, the demand for TVS devices is more stringent.
Conventional TVS devices may incorporate a silicon controlled rectifier (Silicon Controlled Rectifier, SCR). Fig. 1 is a cross-sectional view of a prior art transient voltage suppression diode structure in combination with a scr. As shown, the TVS device 1 is structured by stacking a bottom metal layer 18, a P-type base layer 10, an N-type buried layer 21, an N-type epitaxial layer 11, a p+ -type implanted layer 13, an n+ -type implanted layer 14, a dielectric layer (INTERLAYER DIELECTRIC, ILD) 15, a top metal layer 16, and a protective layer (passivation layer) 17 in order. The p+ type implanted layer 13 and the n+ type implanted layer 14 are embedded in the N type epitaxial layer 11, and the top metal layer 16 is connected to the p+ type implanted layer 13 and the n+ type implanted layer 14 through the dielectric layer 15. The TVS device 1 includes a plurality of isolation trenches 12 configured to isolate p+ type implants 13 and n+ type implants 14. The N-type buried layer 21 is disposed between the P-type base layer 10 and the N-type epitaxial layer 11 and spatially corresponds to the p+ type implanted layer 13. In addition, the TVS device 1 further includes a scr 20. It should be noted that, in the structure of the conventional TVS device 1, the silicon controlled rectifier 20 is formed by forming a recess 19 through a wet etching process after the p+ type implantation layer 13, the n+ type implantation layer 14 and the dielectric layer 15 are formed. After the subsequent processing of the top metal layer 16 and the passivation layer (passivationlayer) 17 is completed, the structure of the scr 20 is obtained at the recess 19. Since the process of the scr 20 is performed by wet etching, the etching rate is not easy to control, and the metal filling force is weak, so that the process stability of the TVS device 1 is poor.
In view of the foregoing, it is desirable to provide a tvs structure and a method for fabricating the same to solve the foregoing problems.
Disclosure of Invention
An object of the present disclosure is to provide a transient voltage suppression diode structure and a method of manufacturing the same. By introducing a plurality of deep trench structures formed by dry etching, the problems of unstable process, difficult control of etching rate, poor metal filling property and the like caused by wet etching can be avoided, and the performance of the transient voltage suppression diode structure is further improved. Furthermore, the silicon controlled rectifier constructed by the deep trench structures is easy to control the size and provide preferable electrical connection characteristics. And the deep trench structure formed by doped polysilicon material can reduce parasitic resistance (PARASITIC RESISTANCE) of N-type epitaxial layer, and further improve the performance of the transient voltage suppression diode structure.
Another object of the present disclosure is to provide a tvs structure and a method of manufacturing the same. The silicon controlled rectifier is constructed by a plurality of deep trench portions formed by, for example, dry etching, so as to avoid process instability caused by wet etching and reduce the complexity of the process. In addition, the silicon controlled rectifier constructed by the deep trench structures is easy to control the size and can provide preferable electrical connection characteristics. And the deep trench structures formed by doped polysilicon material can eliminate the problem of poor metal filling property, reduce parasitic resistance (PARASITICRESISTANCE) of the N-type epitaxial layer, and further improve the performance of the transient voltage suppression diode structure.
To achieve the foregoing objects, the present disclosure provides a tvs structure. The semiconductor device comprises a P-type substrate, an N-type epitaxial layer, at least one P+ type implantation layer, at least one N+ type implantation layer, a plurality of deep trench portions, a dielectric layer and a first metal layer. The P-type base layer board is provided with a first surface and a second surface, wherein the first surface and the second surface are opposite to each other. The N-type epitaxial layer is arranged on the first surface of the P-type base plate. At least one P+ type implantation layer embedded on the N type epitaxial layer. At least one N+ type implantation layer is embedded on the N type epitaxial layer and is separated from the at least one P+ type implantation layer. A plurality of deep trench portions penetrate through the N-type epitaxial layer, wherein each deep trench portion is provided with a first end and a second end which are opposite to each other, and the first end is connected to the P-type substrate. The dielectric layer is arranged on the N-type epitaxial layer and exposes at least one P+ type implantation layer, at least one N+ type implantation layer and the second ends of each of the plurality of deep trench portions. The first metal layer is arranged on the dielectric layer and connected to the second ends of the at least one P+ type implantation layer, the at least one N+ type implantation layer and the plurality of deep trench parts, wherein the plurality of deep trench parts are connected with the first metal layer and are assembled to form the silicon controlled rectifier.
In one embodiment, the plurality of deep trenches includes a doped polysilicon layer.
In one embodiment, the deep trenches are formed using a dry etching process.
In one embodiment, the tvs structure further includes an N-type buried layer spatially opposite to the at least one p+ type implanted layer and disposed between the P-type substrate and the N-type epitaxial layer.
In an embodiment, the tvs structure further includes a protective layer disposed on the first metal layer and partially exposing the first metal layer.
In an embodiment, the tvs structure further includes a second metal layer disposed on the second surface of the P-type substrate.
In an embodiment, the tvs further includes a plurality of isolation trenches penetrating the N-epi layer and partially interposed between the P-type substrate, wherein the plurality of isolation trenches are configured to isolate at least one p+ type implant, at least one n+ type implant, and a plurality of deep trenches between the at least one p+ type implant, the at least one n+ type implant, and the plurality of deep trenches.
In one embodiment, each isolation trench includes an oxide layer, which encapsulates the outer periphery and bottom of the polysilicon layer.
In order to achieve the above object, the present disclosure further provides a method for manufacturing a tvs structure, which includes the steps of: (a) Providing a P-type base plate, wherein the P-type base plate is provided with a first surface and a second surface, and the first surface and the second surface are opposite to each other; (b) Forming an N-type epitaxial layer which is arranged on the first surface of the P-type base plate; (c) Partially etching the N-type epitaxial layer to form a plurality of deep trenches penetrating through the N-type epitaxial layer; (d) Filling a plurality of deep trenches with a polysilicon material to form a plurality of deep trench portions, wherein each deep trench portion has a first end and a second end opposite to each other, wherein the first end is connected to the P-type substrate; (e) Forming at least one P+ type implantation layer and at least one N+ type implantation layer respectively, wherein the at least one P+ type implantation layer, the at least one N+ type implantation layer and the plurality of deep trench parts are arranged in an isolated manner; (f) Forming a dielectric layer on the N-type epitaxial layer and exposing at least one P+ type implantation layer, at least one N+ type implantation layer and the second ends of each of the plurality of deep trench portions; and (g) forming a first metal layer disposed on the dielectric layer and connected to the at least one P+ implant layer, the at least one N+ implant layer, and the second ends of the plurality of deep trench portions, wherein the plurality of deep trench portions are connected to the first metal layer and are assembled to form a silicon controlled rectifier.
In one embodiment, wherein the polysilicon material is a doped polysilicon material, the deep trench portion includes a doped polysilicon layer.
In one embodiment, in step (c), the plurality of deep trenches are formed using a dry etching process.
In one embodiment, the step (b) further includes forming an N-type buried layer in the step (b 0), wherein the N-type buried layer is disposed between the P-type substrate and the N-type epitaxial layer and spatially corresponds to the at least one p+ type implanted layer.
In an embodiment, the method further includes the step (h 1) of forming a protection layer disposed on the first metal layer and partially exposing the first metal layer.
In an embodiment, the method for manufacturing a tvs structure further includes a step (h 2) of forming a second metal layer disposed on the second surface of the P-type substrate.
In one embodiment, step (c) further comprises the steps of: (c0) And forming a plurality of isolation trench parts penetrating the N-type epitaxial layer and partially inserted into the P-type substrate, wherein the isolation trench parts are positioned among the at least one P+ type implantation layer, the at least one N+ type implantation layer and the deep trench parts, and are assembled to isolate the at least one P+ type implantation layer, the at least one N+ type implantation layer and the deep trench parts.
In one embodiment, step (c 0) further comprises the steps of: (c01) Partially etching the N-type epitaxial layer and the P-type substrate to form a plurality of isolation trenches penetrating through the N-type epitaxial layer; (c02) Forming an oxide layer on the sidewalls and bottom of the isolation trenches; and (c 03) filling a plurality of isolation trenches with a polysilicon material to form a plurality of isolation trench portions, wherein the plurality of isolation trench portions penetrate through the N-type epitaxial layer and are partially inserted into the P-type substrate, and the plurality of isolation trench portions are positioned between the at least one P+ type implantation layer, the at least one N+ type implantation layer and the plurality of deep trench portions, and are assembled to isolate the at least one P+ type implantation layer, the at least one N+ type implantation layer and the plurality of deep trench portions.
Drawings
Fig. 1 is a cross-sectional view disclosing a prior art tvs structure.
Fig. 2 is a schematic diagram of a transient voltage suppression diode structure in accordance with a preferred embodiment of the present disclosure.
Fig. 3A-3K are schematic flow diagrams of the fabrication of a tvs structure in accordance with a preferred embodiment of the present disclosure.
Fig. 4 is a flow chart disclosing a method of manufacturing a tvs structure of a preferred embodiment of the present disclosure.
Reference numerals illustrate:
1: TVS element
10: P-type base layer board
11: N-type epitaxial layer
12: Isolation trench portion
13: P+ type implantation layer
14: N+ type implantation layer
15: Dielectric layer
16: Top metal layer
17: Protective layer
18: Bottom metal layer
19: Groove
20: Silicon controlled rectifier
21: N-type buried layer
3: Transient voltage suppression diode structure
30: P-type base layer board
30A: first surface
30B: a second surface
31: N-type epitaxial layer
32: Isolation trench portion
32A: oxide layer
32B: polysilicon layer
32C: isolation trench
33: + Implant layer
34: N+ type implantation layer
35: Dielectric layer
36: A first metal layer
37: Protective layer
38: Second metal layer
40: Silicon controlled rectifier
41: N-type buried layer
42: Deep trench portion
42A: first end
42B: second end
42C: deep trench
S01-S11: step (a)
Detailed Description
Some exemplary embodiments embodying features and advantages of the present disclosure will be described in detail in the following description. It will be understood that the present disclosure is capable of various modifications in the various embodiments, all without departing from the scope of the present disclosure, and that the description and drawings are intended to be illustrative in nature and not to be limiting of the present disclosure.
Fig. 2 is a schematic diagram illustrating a transient voltage suppression diode structure in accordance with a preferred embodiment of the present disclosure. In this embodiment, the tvs 3 includes a P-type substrate 30, an N-type epitaxial layer 31, a plurality of isolation trenches 32, at least one p+ -type implant layer 33, at least one n+ -type implant layer 34, a plurality of deep trenches 42, a dielectric layer 35, a first metal layer 36, a passivation layer 37, and a second metal layer 38. The P-type substrate 30 has a first surface 30a and a second surface 30b, wherein the first surface 30a and the second surface 30b are opposite to each other. The N-type epitaxial layer 31 is disposed on the first surface 30a of the P-type base layer 30. At least one p+ implant 33 is embedded on the N-epi layer 31. At least one n+ type implantation layer 34 is embedded on the N type epitaxial layer 31, and the at least one n+ type implantation layer 34 and the at least one p+ type implantation layer 33 are further separated from each other by the isolation trench portion 32. In addition, in the present embodiment, a plurality of deep trench portions 42 penetrate through the N-type epitaxial layer 31, wherein each deep trench portion 42 has a first end 42a and a second end 42b opposite to each other, and the first end 42a is connected to and inserted into the P-type substrate 30. In addition, the dielectric layer 35 is disposed on the N-type epitaxial layer 31 and exposes the at least one p+ -type implant layer 33, the at least one n+ -type implant layer 34, and the second ends 42b of each of the plurality of deep trench portions 42. The first metal layer 36 is disposed on the dielectric layer 35 and connected to the at least one p+ type implant layer 33, the at least one n+ type implant layer 34, and the second ends 42b of the plurality of deep trench portions 42, wherein the plurality of deep trench portions 42 are connected to the first metal layer 36 and are assembled to form a scr 40.
In this embodiment, the tvs 3 further includes a protection layer 37 disposed on the first metal layer 36 and partially exposing the first metal layer 36 to define the external connection terminal. In addition, the tvs 3 further includes a second metal layer 38 disposed on the second surface 30b of the P-type substrate 30. In this embodiment, the tvs 3 further includes an N-type buried layer 41 spatially opposite to the at least one p+ type implanted layer 33 and disposed between the P-type substrate 30 and the N-type epitaxial layer 31. Of course, the disclosure is not limited thereto.
It should be noted that the deep trench portions 42 are more preferably formed by a dry etching process, and the deep trench portions 42 are more preferably a doped polysilicon layer. Since the plurality of deep trench portions 42 can be manufactured, for example, using only a dry etching process, it is advantageous to eliminate process instability caused by a wet etching process and to reduce the complexity of the process. Furthermore, the silicon controlled rectifier 40 constructed by the deep trench portions 42 is easy to control the size and provide preferable electrical connection characteristics. The deep trenches 42, for example, formed of doped polysilicon, can eliminate the problem of poor metal filling, and can reduce parasitic resistance (PARASITIC RESISTANCE) of the N-type epitaxial layer 31, for example, to further improve the performance of the tvs 3.
In this embodiment, the isolation trench portions 32 are further located between the at least one p+ implant layer 33, the at least one n+ implant layer 34 and the deep trench portions 42, so as to isolate the at least one p+ implant layer 33, the at least one n+ implant layer 34 and the deep trench portions 42. Each isolation trench 32 further includes an oxide layer 32a and a polysilicon layer 32b, wherein the oxide layer 32a covers the outer periphery and the bottom of the polysilicon layer 32 b. And are not intended to limit the essential features of the present disclosure, which are not described in detail herein.
Corresponding to the aforementioned tvs 3, the present disclosure also discloses a method for manufacturing the tvs 3. Fig. 3A to 3K are schematic views illustrating a manufacturing flow of a tvs structure according to a preferred embodiment of the present disclosure. Fig. 4 is a flow chart illustrating a method of fabricating a tvs structure of a preferred embodiment of the present disclosure. Reference is made to fig. 2, 3A to 3K and 4. First, in step S01, a P-type substrate 30 is provided. As shown in fig. 3A, the P-type substrate 30 includes a first surface 30a and a second surface 30b, wherein the first surface 30a and the second surface 30b are opposite surfaces of the P-type substrate 30. Next, in step S02, an N-type buried layer 41 is formed on the P-type substrate 30 by using the processes of implant and drive-in, as shown in fig. 3B. In step S03, at least one N-type epitaxial layer 31 is formed on the first surface 30a of the P-type substrate 30, and the N-type buried layer 41 is disposed between the first surface 30a of the P-type substrate 30 and the N-type epitaxial layer 31, as shown in fig. 3C.
Then, in step S04, a plurality of isolation trenches 32 are formed through the N-type epitaxial layer 31 and connected to the P-type base layer 30. In this embodiment, the plurality of isolation trenches 32 may be formed by, for example, partially etching the N-type epitaxial layer 30 and the P-type substrate 30 by a dry etching process to form a plurality of isolation trenches 32c penetrating the N-type epitaxial layer 31 and penetrating the first surface 30a of the P-type substrate 30 and the N-type buried layer 41, as shown in fig. 3D. Then, a gate oxidation process is performed, and unnecessary oxide is removed by an etching back process to form an oxide layer 32a disposed on the sidewalls and bottom of the isolation trenches 32 c. Then, the isolation trenches 32c are filled with a polysilicon material, and unnecessary polysilicon material is removed by an etching back process to form the isolation trenches 32, as shown in fig. 3E. Each isolation trench 32 includes an oxide layer 32a and a polysilicon layer 32b, wherein the oxide layer 32a covers the outer periphery and the bottom of the polysilicon layer 32 b. And are not intended to limit the essential features of the present disclosure, which are not described in detail herein.
In step S05, a dry etching process is performed to partially etch at least one N-type epitaxial layer 31 and P-type base layer 30 to form a plurality of deep trenches 42c penetrating the N-type epitaxial layer 31, as shown in fig. 3F. Next, in step S06, the deep trenches 42c are filled with a polysilicon material, and unnecessary polysilicon material is removed by an etching back process to form the deep trenches 42, as shown in fig. 3G. Each deep trench 42 has a first end 42a and a second end 42b opposite to each other, wherein the first end 42a is connected to and inserted in the P-type substrate 30. In this embodiment, the deep trenches 42 may be formed by a doped polysilicon material layer, for example. Since the formation of the plurality of deep trenches 42c is easily controlled by the dry etching process, process instability caused by the wet etching is avoided. In addition, the deep trench 42 structure formed by doped polysilicon material can eliminate the problem of poor metal filling, reduce parasitic resistance (PARASITICRESISTANCE) of the N-type epitaxial layer 31, and further improve the performance of the TVS diode structure 3
In step S07, at least one p+ type implant layer 33 and at least one n+ type implant layer 34 are respectively formed and embedded in the N type epitaxial layer 31, and the at least one p+ type implant layer 33 and the at least one n+ type implant layer 34 are isolated from the deep trench portions 42, as shown in fig. 3H. In other words, the isolation trench portions 32 are further located between the at least one p+ implant layer 33, the at least one n+ implant layer 34 and the deep trench portions 42, and are configured to isolate the at least one p+ implant layer 33, the at least one n+ implant layer 34 and the deep trench portions 42. The number and relative positions of the at least one p+ implant layer 33, the at least one n+ implant layer 34, and the plurality of deep trench portions 42 may be modulated according to the actual application requirements, and the disclosure is not limited thereto.
In step S08, a dielectric layer 35 is formed on the N-type epitaxial layer 31 by, for example, dielectric material deposition and etching processes, and exposes the at least one p+ -type implant layer 33, the at least one n+ -type implant layer 34, and the second ends 42b of each of the plurality of deep trench portions 42, as shown in fig. 3I. Thereafter, in step S09, a first metal layer 36 is formed on the dielectric layer 35 and connected to the at least one p+ type implant layer 33, the at least one n+ type implant layer 34 and the second ends 42b of the plurality of deep trenches 42 by, for example, metal sputtering and etching processes, wherein the plurality of deep trenches 42 are connected to the first metal layer 36 and a scr 40 is configured as shown in fig. 3J. In step S10, a passivation layer 37 is formed on the first metal layer 36 and partially exposes the first metal layer 36 to define the external connection terminal. In addition, in step S11, a second metal layer 38 is further formed and disposed on the second surface 30b of the P-type substrate 30. The second metal layer 38 is connected to the P-type substrate 30 and is assembled to form a ground, as shown in fig. 2. Of course, the formation of the protection layer 37 and the second metal layer 38 can be modulated according to practical requirements, and is not a limitation of the essential technical features of the present disclosure, and will not be repeated herein.
It should be noted that, the tvs 3 of the present disclosure replace the metal-filled recess 19 (refer to fig. 1) with a plurality of deep trenches 42, which can simplify the complexity of process control and control the size of the scr 40 in addition to replacing the wet etching process with the dry etching process. In addition, the deep trenches 42 formed by doping the polysilicon material can eliminate the problem of poor metal filling, provide preferable electrical connection characteristics, and reduce parasitic resistance (PARASITIC RESISTANCE) of the N-type epitaxial layer 31, for example, so as to further improve the performance of the tvs 3. Of course, the order of formation of the deep trenches 42 with respect to other structures such as the p+ implant 33 or the n+ implant 34 may also be modulated according to the practical requirements. That is, the dry etching and polysilicon filling and etching back processes used for the deep trenches 42 can be modulated according to the practical requirements, and the disclosure is not limited thereto and will not be repeated.
In summary, the present disclosure provides a tvs structure and a method for fabricating the same. The introduction of a plurality of deep trench structures formed by dry etching is utilized to avoid the problems of unstable process, difficult control of etching rate, poor metal filling property and the like caused by wet etching, thereby further improving the performance of the transient voltage suppression diode structure. Furthermore, the silicon controlled rectifier constructed by the deep trench structures is easy to control the size and provide preferable electrical connection characteristics. And the deep trench structure formed by doped polysilicon material can reduce parasitic resistance (PARASITIC RESISTANCE) of N-type epitaxial layer, and further improve the performance of the transient voltage suppression diode structure. In other words, the silicon controlled rectifier is constructed by forming a plurality of deep trenches by dry etching, so as to avoid the unstable process caused by wet etching and reduce the complexity of the process. In addition, the silicon controlled rectifier constructed by the deep trench structures is easy to control the size and can provide preferable electrical connection characteristics. The deep trench structure formed by doped polysilicon material can eliminate the problem of poor metal filling property, reduce parasitic resistance (PARASITIC RESISTANCE) of N-type epitaxial layer, and further improve the performance of the transient voltage suppression diode structure.
Various modifications and adaptations of this disclosure may occur to one skilled in the art without departing from the scope of the appended claims.
Claims (14)
1. A transient voltage suppression diode structure comprising
A P-type substrate having a first surface and a second surface, wherein the first surface and the second surface are opposite to each other;
An N-type epitaxial layer arranged on the first surface of the P-type base plate;
at least one P+ type implantation layer embedded on the N type epitaxial layer;
at least one N+ type implantation layer embedded on the N type epitaxial layer and separated from the at least one P+ type implantation layer;
A plurality of deep trench portions penetrating the N-type epitaxial layer, wherein each deep trench portion has a first end and a second end opposite to each other, and wherein the first end is connected to the P-type substrate;
A dielectric layer disposed on the N-type epitaxial layer and exposing the at least one P+ implant layer, the at least one N+ implant layer and the second ends of each of the plurality of deep trenches; and
The first metal layer is arranged on the dielectric layer and connected with the at least one P+ type implanted layer, the at least one N+ type implanted layer and the second ends of the deep trench parts, wherein the deep trench parts are connected with the first metal layer and are assembled to form a silicon controlled rectifier, and the deep trench parts comprise a doped polysilicon layer.
2. The tvs structure of claim 1, wherein the plurality of deep trenches are formed using a dry etching process.
3. The tvs structure of claim 1, further comprising an N-type buried layer spatially opposite to the at least one p+ type implanted layer and disposed between the P-type substrate and the N-type epitaxial layer.
4. The tvs structure of claim 1, further comprising a protective layer disposed on the first metal layer and partially exposing the first metal layer.
5. The tvs structure of claim 1, further comprising a second metal layer disposed on the second side of the P-type substrate.
6. The tvs structure of claim 1, further comprising a plurality of isolation trenches extending through the N-epi layer and partially interposed between the P-epi layer, wherein the isolation trenches are disposed between the at least one p+ implant, the at least one n+ implant, and the plurality of deep trenches, and are configured to isolate the at least one p+ implant, the at least one n+ implant, and the plurality of deep trenches.
7. The tvs structure of claim 6, wherein each of said isolation trenches comprises an oxide layer and a polysilicon layer, said oxide layer surrounding the periphery and bottom of said polysilicon layer.
8. A method of fabricating a tvs structure, comprising the steps of:
(a) Providing a P-type base plate, wherein the P-type base plate is provided with a first surface and a second surface, and the first surface and the second surface are opposite to each other;
(b) Forming an N-type epitaxial layer arranged on the first surface of the P-type base plate;
(c) Partially etching the N-type epitaxial layer to form a plurality of deep trenches penetrating the N-type epitaxial layer;
(d) Filling the deep trenches with a polysilicon material to form a plurality of deep trench portions, wherein each deep trench portion has a first end and a second end opposite to each other, wherein the first end is connected to the P-type substrate, wherein the polysilicon material is a doped polysilicon material, and the plurality of deep trench portions include a doped polysilicon layer;
(e) Forming at least one P+ type implantation layer and at least one N+ type implantation layer respectively, wherein the at least one P+ type implantation layer, the at least one N+ type implantation layer and the plurality of deep trench portions are arranged in an isolated manner;
(f) Forming a dielectric layer on the N-type epitaxial layer and exposing the at least one P+ type implant layer, the at least one N+ type implant layer and the second ends of each of the plurality of deep trenches; and
(G) Forming a first metal layer on the dielectric layer and connected to the at least one P+ implant layer, the at least one N+ implant layer and the second ends of the deep trench portions, wherein the deep trench portions are connected to the first metal layer and are assembled to form a SCR.
9. The method of claim 8, wherein in step (c), the deep trenches are formed by a dry etching process.
10. The method for fabricating a tvs structure of claim 8, wherein the step (b) further comprises the steps of:
(b0) An N-type embedded layer is formed, wherein the N-type embedded layer is arranged between the P-type base layer plate and the N-type epitaxial layer and corresponds to the at least one P+ type implanted layer in space.
11. The method of fabricating a tvs structure of claim 8, further comprising the steps of:
(h1) A protective layer is formed on the first metal layer and partially exposes the first metal layer.
12. The method of fabricating a tvs structure of claim 8, further comprising the steps of:
(h2) Forming a second metal layer on the second surface of the P-type base plate.
13. The method for fabricating a tvs structure of claim 8, wherein the step (c) further comprises the steps of:
(c0) Forming a plurality of isolation trench portions penetrating the N-type epitaxial layer and partially inserted into the P-type substrate, wherein the isolation trench portions are positioned among the at least one P+ type implanted layer, the at least one N+ type implanted layer and the plurality of deep trench portions, and are assembled to isolate the at least one P+ type implanted layer, the at least one N+ type implanted layer and the plurality of deep trench portions.
14. The method for fabricating a tvs structure of claim 13, wherein the step (c 0) further comprises the steps of:
(c01) Partially etching the N-type epitaxial layer and the P-type substrate to form a plurality of isolation trenches penetrating through the N-type epitaxial layer;
(c02) Forming an oxide layer on the side walls and the bottoms of the isolation trenches; and
(C03) And filling the isolation trenches with a polysilicon material to form a plurality of isolation trench portions, wherein the isolation trench portions penetrate through the N-type epitaxial layer and are partially inserted into the P-type substrate, and the isolation trench portions are positioned among the at least one P+ type implantation layer, the at least one N+ type implantation layer and the deep trench portions to form the isolation of the at least one P+ type implantation layer, the at least one N+ type implantation layer and the deep trench portions.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101847663A (en) * | 2010-04-30 | 2010-09-29 | 上海新进半导体制造有限公司 | Transient voltage suppressor (TVS) and method for forming same |
| CN108109998A (en) * | 2017-12-29 | 2018-06-01 | 杭州士兰集成电路有限公司 | One-way low-capacitance TVS device and its manufacturing method |
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| US8338854B2 (en) * | 2009-03-31 | 2012-12-25 | Alpha And Omega Semiconductor Incorporated | TVS with low capacitance and forward voltage drop with depleted SCR as steering diode |
| JP2014175324A (en) * | 2013-03-06 | 2014-09-22 | Panasonic Corp | Low capacity semiconductor device |
| CN103208530B (en) * | 2013-03-11 | 2016-04-27 | 江苏应能微电子有限公司 | Low electric capacity ultra-deep groove transient voltage suppressor structure |
| EP2996156A1 (en) * | 2014-09-10 | 2016-03-16 | Ipdia | Semiconductor device comprising a diode and electrostatic discharge protection device |
| CN106449633B (en) * | 2016-09-23 | 2019-08-09 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101847663A (en) * | 2010-04-30 | 2010-09-29 | 上海新进半导体制造有限公司 | Transient voltage suppressor (TVS) and method for forming same |
| CN108109998A (en) * | 2017-12-29 | 2018-06-01 | 杭州士兰集成电路有限公司 | One-way low-capacitance TVS device and its manufacturing method |
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