CN116632003B - Preparation method of ESD protection device and ESD protection device - Google Patents

Abstract

This application relates to semiconductor chip technology and discloses a method for preparing an ESD protection device, which includes: forming a P-epitaxial layer and an N-epitaxial layer on a P+ substrate; forming a first P+ isolation region that penetrates the N-epitaxial layer vertically and a second P+ isolation region; a P-well region is formed in the N-epitaxial layer between the first P+ isolation region and the second P+ isolation region; a P-well region is formed in the N-epitaxial layer between the first P+ isolation region and the P-well region forming a first N+ implanted region and a first P+ implanted region, and forming a second N+ implanted region across a boundary between the N-epitaxial layer and the P-well region, and forming a second P+ implanted region within the P-well region and The third N+ injection region; respectively forms isolation trenches that penetrate the N-epitaxial layer vertically. This application also discloses an ESD protection device. This application aims to reduce the manufacturing size of the ESD protection device without affecting the current flow capacity of the ESD protection device.

Description

Preparation method of ESD protection device and ESD protection device

Technical field

The present application relates to the field of semiconductor chip technology, and in particular to a preparation method of an ESD protection device and an ESD protection device.

Background technique

Integrated circuit products are extremely susceptible to ESD (Electro-Static discharge) during their production, manufacturing, assembly and working processes, causing internal damage and reduced reliability of the product. Therefore, research on high-performance, high-reliability ESD protection devices plays a vital role in improving the yield and reliability of integrated circuits. Among them, SCR (Silicon Controlled Rectifier) devices are often used to make ESD protection devices.

At present, the lateral structure of the existing low-capacitance SCR device often requires the production of a larger ESD protection device under the same line width. Because the anode and cathode of the lateral structure are both made on the upper surface of the device, the size of the anode and cathode is affected. The packaging impact cannot be reduced to less than 10um, so larger devices need to be made accordingly. If the device size is reduced by reducing the lateral structure, the area-related current flow capacity of the SCR device will be reduced. That is, it is difficult for the current low-capacitance SCR structure large flyback ESD protection device to be applied to smaller device packages.

The above content is only used to assist in understanding the technical solutions of the present application, and does not represent an admission that the above content is prior art.

Contents of the invention

The main purpose of this application is to provide a method for preparing an ESD protection device and an ESD protection device, aiming to reduce the manufacturing size of the ESD protection device without affecting the current flow capacity of the ESD protection device.

In order to achieve the above objectives, this application provides a method for preparing an ESD protection device, which includes the following steps:

Provide a P+ substrate, form a P- epitaxial layer on the P+ substrate, and form an N- epitaxial layer on the P- epitaxial layer;

Form two P+ isolation areas that penetrate the N- epitaxial layer longitudinally, namely the first P+ isolation area and the second P+ isolation area;

forming a P-well region in the N-epitaxial layer between the first P+ isolation region and the second P+ isolation region;

A first N+ implanted region and a first P+ implanted region are formed in the N-epitaxial layer between the first P+ isolation region and the P-well region, and a first N-epitaxial layer and a first P-well implanted region are formed across the boundary between the N-epitaxial layer and the P-well region. two N+ implant regions, and forming a second P+ implant region and a third N+ implant region in the P well region;

Isolation trenches longitudinally penetrating the N- epitaxial layer are respectively formed between the first N+ implanted region and the first P+ implanted region, and between the P well region and the second P+ isolation region.

Optionally, the preparation method of the ESD protection device also includes:

The annealing temperature during the formation of the P+ isolation zone is 1200°C~1250°C, and the annealing time is 1 hour~2 hours.

Optionally, the preparation method of the ESD protection device also includes:

The annealing temperature during the formation of the P-well region is 1000°C to 2000°C, and the annealing time is 2 to 3 hours.

Optionally, the preparation method of the ESD protection device also includes:

In the process of forming the first P+ implantation area and the second P+ injection area, the injected P+ dose is 1.0E15/cm²~1.0E16/cm²;

And, in the process of forming the first N+ implanted region, the second N+ implanted region and the third N+ implanted region, the injected N+ dose is 1.0E15/cm²~1.0E16/cm².

Optionally, the preparation method of the ESD protection device also includes:

In the process of forming the first N+ implanted region, the first P+ implanted region, the second N+ implanted region, the second P+ implanted region and the third N+ implanted region, a first annealing process and a second annealing process are performed, wherein, The annealing temperature of the first annealing process is 1100°C~1200°C, and the annealing time is 10 seconds~20 seconds; the annealing temperature of the second annealing process is 800°C~900°C, and the annealing time is 30 minutes~60 minutes.

Optionally, the step of forming isolation trenches longitudinally penetrating the N- epitaxial layer between the first N+ implanted region and the first P+ implanted region, and between the P well region and the second P+ isolation region includes: :

Deep trenches longitudinally penetrating the N- epitaxial layer are formed between the first N+ implanted region and the first P+ implanted region, and between the P well region and the second P+ isolation region;

Fill the two deep trenches with isolation dielectric until an isolation layer with a preset thickness is formed on the N-epitaxial layer, so that the deep trenches form isolation trenches, wherein the preset thickness is 2 μm ~ 3.5 μm;

Peel off the isolation layer.

Optionally, after the step of forming isolation trenches longitudinally penetrating the N- epitaxial layer between the first N+ implanted region and the first P+ implanted region, and between the P well region and the second P+ isolation region, respectively ,Also includes:

An oxide layer covering the N- epitaxial layer, the first P+ isolation region, the second N+ implantation region and the upper surface of the isolation trench is formed on the N- epitaxial layer.

Optionally, after the step of forming an oxide layer on the N-epitaxial layer covering the N-epitaxial layer, the first P+ isolation region, the second N+ implantation region and the upper surface of the isolation trench, the step further includes:

Form a first metal layer on the second P+ injection region, the third N+ injection region and the second P+ isolation region, so that the second P+ injection region, the third N+ injection region and the second P+ isolation region are electrically connected;

And, forming a second metal layer connecting the first N+ implanted region and the first P+ implanted region on the first N+ implanted region and the first P+ implanted region.

Optionally, the preparation method of the ESD protection device also includes:

A passivation layer is formed on the first metal layer and the second metal layer, wherein wiring points are reserved in the passivation layer above the second metal layer.

In order to achieve the above object, the present application also provides an ESD protection device, which is prepared using the method for preparing an ESD protection device as described above.

The ESD protection device preparation method and ESD protection device provided by this application can produce an ESD protection device that can use a P+ substrate as a cathode. There is no need to make a cathode from the upper surface layer of the ESD protection device, so that the device can be maintained while maintaining the conductivity of the device. In the case of current capacity, the manufacturing size of the device can be reduced to meet the packaging requirements of smaller devices, and a large flyback ESD protection device with a low capacitance vertical structure can be obtained. When packaging the ESD protection device, the device can be extracted from the P+ substrate. The cathode can avoid grounding wires during device packaging, thereby reducing packaging costs.

Description of drawings

Figure 1 is a schematic diagram of the steps of a method for preparing an ESD protection device in an embodiment of the present application;

Figure 2 is a schematic diagram of the preparation process of an ESD protection device in an embodiment of the present application;

Figure 3 is another schematic diagram of the preparation process of the ESD protection device in an embodiment of the present application;

Figure 4 is another schematic diagram of the preparation process of the ESD protection device in an embodiment of the present application;

Figure 5 is another schematic diagram of the preparation process of the ESD protection device in an embodiment of the present application;

Figure 6 is a schematic structural diagram of an ESD protection device in an embodiment of the present application;

Figure 7 is an equivalent circuit diagram of an ESD protection device in an embodiment of the present application;

FIG. 8 is another structural schematic diagram of an ESD protection device according to an embodiment of the present application.

The realization of the purpose, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings.

Detailed ways

The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are illustrative and are intended to be used to explain the present application and cannot be understood as limitations of the present application. Based on the embodiments in the present application, those of ordinary skill in the art will not make creative efforts without premise All other embodiments obtained below belong to the protection scope of this application.

In addition, if the descriptions of "first", "second", etc. are mentioned in this application, they are only used for descriptive purposes (such as to distinguish the same or similar elements), and shall not be understood as indicating or implying their relative importance or implication. Specify the quantity of technical characteristics indicated. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions in various embodiments can be combined with each other, but it must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions does not exist. , nor is it within the scope of protection required by this application.

Referring to Figure 1, in one embodiment, a method for preparing an ESD protection device includes:

Step S10: Provide a P+ substrate, form a P- epitaxial layer on the P+ substrate, and form an N- epitaxial layer on the P- epitaxial layer;

Step S20: Form two P+ isolation regions longitudinally penetrating the N-epitaxial layer and the P-epitaxial layer, which are the first P+ isolation region and the second P+ isolation region respectively;

Step S30, forming a P-well region in the N- epitaxial layer between the first P+ isolation region and the second P+ isolation region;

Step S40, forming a first N+ implantation region and a first P+ implantation region in the N-epitaxial layer between the first P+ isolation region and the P-well region, and across the boundary between the N-epitaxial layer and the P-well region forming a second N+ implanted region, and forming a second P+ implanted region and a third N+ implanted region in the P well region;

Step S50: Form isolation trenches longitudinally penetrating the N- epitaxial layer between the first N+ implanted region and the first P+ implanted region, and between the P well region and the second P+ isolation region.

In this embodiment, the resistivity of the P+ substrate may be 0.0005Ω·cm~0.0008Ω·cm.

As described in step S10, referring to Figure 2, the lightly doped P-epitaxial layer 101 process is completed on the pre-provided P+ substrate 100; that is, the P+ substrate 100 is grown by chemical vapor deposition to a thickness of 6 μm~14 μm and a resistance of 6 μm to 14 μm. P-epitaxial layer 101 with a rate of 2Ω·cm ~4Ω·cm.

Then, the lightly doped N-epitaxial layer 102 process is completed on the P-epitaxial layer 101; that is, the P-epitaxial layer 101 is grown by chemical vapor deposition to a thickness of 6 μm ~ 12 μm, and a resistivity of 45Ω·cm ~ 55Ω·cm (optional 50Ω·cm) N-epitaxial layer 102.

As described in step S20 , referring to FIG. 3 , two left and right window areas are formed on a partial area of the N-epitaxial layer 102 through photolithography and etching, and the two formed left and right window areas need to ensure longitudinal penetration of the N-epitaxial layer 102 . Layer 102 (i.e., the depth of the window region is greater than the thickness of N-epitaxial layer 102).

It should be noted that here you only need to ensure that both the left and right window areas need to penetrate the N-epitaxial layer 102 (this is to ensure that current can flow from the surface of the subsequently formed P+ isolation area to the P+ substrate 100). In addition, the left and right The two window areas may further penetrate the P-epitaxial layer 101 , or may not penetrate the P-epitaxial layer 101 . Among them, it is preferable to form a P+ isolation region longitudinally penetrating the N-epitaxial layer 102 and the P-epitaxial layer 101 (that is, the depth of the P+ isolation region may be greater than or equal to the sum of the thicknesses of the N-epitaxial layer 102 and the P-epitaxial layer 101).

Optionally, by injecting boron into the left and right window areas, two left and right P+ isolation areas can be formed; the two left and right P+ isolation areas are marked as the first P+ isolation area 103 and the second P+ isolation area 104 respectively.

Optionally, in the process of forming the P+ isolation area, when completing the annealing process on the P+ isolation area, the selected annealing temperature is 1200°C~1250°C and the annealing time is 1 hour~2 hours. This ensures that the P+ isolation region can expand through the N- epitaxial layer 102 and the P- epitaxial layer 101, and then be connected to the P+ substrate 100.

As described in step S30, referring to FIG. 3, a window region is formed by photolithography and etching in a local area of the upper part of the N-epitaxial layer 102 between the first P+ isolation region 103 and the second P+ isolation region 104, and Boron is implanted in the window area to form a P-well area 105 (P-well). Among them, the boron implant dose is determined by the trigger voltage of the pre-designed ESD protection device; for example, for the trigger voltage of the ESD protection device of 3.3V~7.0V, the boron implant dose required to form the P-well region 105 can be selected as 4.5 E15/cm²~2.0E14/cm².

Optionally, in the process of forming the P-well region 105, when completing the annealing process of the P-well region 105, the selected annealing temperature is 1000°C~2000°C and the annealing time is 2 hours-3 hours to ensure that the P-well region 105 The junction depth of the push junction is greater than the junction depth of the subsequently formed N+ implanted region/P+ implanted region contact.

As described in step S40 , referring to FIG. 4 , a LOCOS (Local Oxidation of Silicon) process is used to form multiple active area, and respectively inject N+/P+ into the selected window in each active area to form an N+ injection area/P+ injection area accordingly.

Optionally, a first N+ injection region 106 and a first P+ injection region 107 are formed in the N-epitaxial layer 102 between the first P+ isolation region 103 and the P well region 105, wherein the first N+ injection region 106 is disposed in between the first P+ isolation region 103 and the first P+ implantation region 107, and the first P+ implantation region 107 is correspondingly disposed between the first N+ implantation region 106 and the P-well region 105.

Optionally, a second N+ implanted region 108 is formed across the boundary between the N-epitaxial layer 102 and the P-well region 105 (that is, the second N+ implanted region 108 is disposed across the N-epitaxial layer 102 and the P-well region 105 at the boundary between them), and the second N+ implanted region 108 is disposed between the first P+ implanted region 107 and the subsequently formed second P+ implanted region 109 .

Optionally, a second P+ implanted region 109 and a third N+ implanted region 110 are formed in the P well region 105, wherein the second P+ implanted region 109 is disposed in the second N+ implanted region 108 and the third N+ implanted region 110. Three N+ implanted regions 110 are disposed between the second P+ implanted region 109 and the second P+ isolation region 104 .

In this way, the N+ implanted region, P+ implanted region, P well region 105 and N- epitaxial layer 102 can form the SCR structure in the ESD protection device.

Optionally, in the process of forming each P+ implanted region (including the first P+ implanted region 107 and the second P+ implanted region 109), the injected P+ dose is 1.0E15/cm²~1.0E16/cm²; when forming In the process of each N+ implantation area (including the first N+ injection area 106, the second N+ injection area 108, and the third N+ injection area 110), the N+ dose injected is 1.0E15/cm²~1.0E16/cm².

Optionally, in the process of forming the first N+ implanted region 106, the first P+ implanted region 107, the second N+ implanted region 108, the second P+ implanted region 109 and the third N+ implanted region 110, each N+ implanted region The /P+ injection area needs to complete two annealing processes, namely the first annealing process and the second annealing process.

Among them, the first annealing process is a high-temperature rapid annealing process, with an annealing temperature of 1100°C to 1200°C and an annealing time of 10 seconds to 20 seconds. The purpose of high-temperature rapid annealing is to activate all injected phosphorus impurities to ensure the formation of good ohmic contact while also reducing the leakage current of the SCR structure.

After completing the first annealing process, a second annealing process is performed. The second annealing process is a low-temperature furnace tube annealing process, with an annealing temperature of 800°C to 900°C and an annealing time of 30 to 60 minutes. The purpose of low-temperature furnace tube annealing is to control the junction depth and breakdown voltage of the N+ implanted area/P+ injected area.

As described in step S50, referring to FIG. 5, through photolithography and etching, a deep groove longitudinally penetrating the N- epitaxial layer 102 is formed between the first N+ implanted region 106 and the first P+ implanted region 107, and a deep groove is formed between the first N+ implanted region 106 and the first P+ implanted region 107. A deep trench longitudinally penetrating the N- epitaxial layer 102 is formed between the well region 105 and the second P+ isolation region 104, and two isolation trenches 111 are obtained by filling the two deep trenches with isolation dielectric. Among them, the depth of the deep trench needs to be greater than the thickness of the N-epitaxial layer 102 to ensure that the areas between the two isolation trenches 111 formed subsequently are not affected by each other and play an isolation role.

Optional, the depth of the deep groove can be selected from 10μm~20μm, and the width of the deep groove can be selected from 1.5μm~3μm.

Wherein, the isolation medium may be polycrystalline or silicon dioxide, preferably polycrystalline.

In this way, referring to Figure 6, the formed ESD protection device can directly use the P+ substrate 100 to make the cathode GND of the ESD protection device (for example, extract an electrode from the P+ substrate 100 as the cathode GND of the ESD protection device), and use the first N+ The injection region 106 and the first P+ injection region 107 make the anode I/O of the ESD protection device (for example, an electrode connecting the first N+ injection region 106 and the first P+ injection region 107 is drawn above the N- epitaxial layer 102 as an electrode of the ESD protection device. anode I/O), and connect the second P+ injection region 109, the third N+ injection region 110 and the second P+ isolation region 104 by making electrodes above the N- epitaxial layer 102 (the dotted lines in Figure 6 represent equivalent replacement of the corresponding electrodes wire, that is, corresponding wiring method), the equivalent circuit diagram of the obtained ESD protection device is shown in Figure 7: P-epitaxial layer 101 and N-epitaxial layer 102 play the role of diode D, and the second P+ isolation area 104 Playing the role of resistor R, the first N+ implanted region 106, the first P+ implanted region 107, the second N+ implanted region 108, the second P+ implanted region 109, the third N+ implanted region 110, the P well region 105 and the N- epitaxial The layers 102 may together function as an SCR structure (ie, equivalent to an SCR structure composed of the first transistor T1 and the second transistor T2 ).

In one embodiment, by making an ESD protection device that can use a P+ substrate as the cathode, there is no need to make a cathode from the upper surface layer of the ESD protection device, so that the device can be reduced in size while maintaining the current flow capacity of the device. The production size (the allowed size can be up to 220μm) can meet the needs of smaller device packaging, and a vertical structure large flyback ESD protection device with low capacitance (can be as low as 0.3pF) can be obtained. When packaging the ESD protection device, Leading the device cathode from the P+ substrate can avoid grounding wires during device packaging, thereby reducing packaging costs.

In one embodiment, based on the above embodiment, vertical through-hole N-layers are respectively formed between the first N+ implanted region and the first P+ implanted region, and between the P-well region and the second P+ isolation region. -The steps for isolating trenches for epitaxial layers include:

Deep trenches longitudinally penetrating the N- epitaxial layer are formed between the first N+ implanted region and the first P+ implanted region, and between the P well region and the second P+ isolation region;

Fill the two deep trenches with isolation dielectric until an isolation layer with a preset thickness is formed on the N-epitaxial layer, so that the deep trenches form isolation trenches, wherein the preset thickness is 2 μm ~ 3.5 μm;

Peel off the isolation layer.

In this embodiment, between the first N+ implanted region 106 and the first P+ implanted region 107, and between the P well region 105 and the second P+ isolation region 104, deep longitudinally penetrating N- epitaxial layers 102 are respectively formed. After the grooves are formed, the isolation medium is filled into the two deep grooves at the same time, and the isolation medium is overfilled until the isolation medium fills the two deep grooves and overflows, and the overflowed part forms a preset thickness above the N-epitaxial layer 102 isolation layer, thus ensuring that the isolation medium in the two isolation grooves 111 can be filled tightly.

Wherein, the preset thickness is 2 μm~3.5 μm.

Then, the isolation layer above the N-epitaxial layer 102 is removed (that is, the isolation layer above the N-epitaxial layer 102 is finally removed).

In one embodiment, based on the above embodiment, referring to FIG. 8 , between the first N+ implanted region and the first P+ implanted region, and between the P well region and the second P+ isolation region, respectively After the step of forming an isolation trench longitudinally penetrating the N-epitaxial layer, it also includes:

An oxide layer covering the N- epitaxial layer, the first P+ isolation region, the second N+ implantation region and the upper surface of the isolation trench is formed on the N- epitaxial layer.

Among them, the oxide layer 112 is first formed on the N- epitaxial layer 102 at one time, and then through photolithography and etching methods, the first N+ implantation region 106, the first P+ implantation region 107, the P well region 105, and the second Corresponding contact holes are made in the oxide layer 112 above the P+ injection region 109, the third N+ injection region 110 and the second P+ isolation region 104, so that the formed oxide layer 112 cannot completely cover the first N+ injection region 106 and the first P+ The upper surfaces of the implanted region 107, the P well region 105, the second P+ implanted region 109, the third N+ implanted region 110 and the second P+ isolation region 104, while the remaining portion of the oxide layer 112 completely covers the N- epitaxial layer 102, the third A P+ isolation region 103, a second N+ implant region 108 and the upper surface of the isolation trench 111.

In one embodiment, based on the above embodiment, referring to Figure 8, the upper surface covering the N-epitaxial layer, the first P+ isolation region, the second N+ injection region and the isolation trench is formed on the N-epitaxial layer. After the oxide layer step, it also includes:

Form a first metal layer on the second P+ injection region, the third N+ injection region and the second P+ isolation region, so that the second P+ injection region, the third N+ injection region and the second P+ isolation region are electrically connected;

And, forming a second metal layer connecting the first N+ implanted region and the first P+ implanted region on the first N+ implanted region and the first P+ implanted region.

In this embodiment, in order to facilitate the production of electrodes and wires on the ESD protection device, a metal layer can be formed on the oxide layer 112 by evaporation or sputtering, and then the metal layer can be divided into The first metal layer 113 and the second metal layer 114, wherein the first metal layer 113 is formed to connect the second P+ implanted region 109, the third N+ implanted region 110 and the second P+ isolation region 104, so that the second P+ The injection region 109, the third N+ injection region 110 and the second P+ isolation region 104 are electrically connected (that is, the first metal layer 113 is used instead to connect the second P+ injection region 109, the third N+ injection region 110 and the second P+ isolation region). The electrode of region 104); the formed second metal layer 114 connects the first N+ injection region 106 and the first P+ injection region 107, and serves as the anode I/O of the ESD protection device (that is, using the second metal layer 114 instead corresponding electrode).

Optionally, the thickness of the metal layer may be greater than the thickness of the oxide layer 112 .

Optionally, the metal layer can be made of aluminum, copper or other metals with good electrical conductivity, preferably aluminum.

Optionally, in order to protect the metal layer, a passivation layer (not shown in the figure) is formed on the first metal layer 113 and the second metal layer 114 .

Among them, in order to facilitate the anode I/O wiring of the ESD protection device, through-holes can be made in the passivation layer above the second metal layer 114 through photolithography and etching methods, and pressure points can be formed as reserved Wiring point (that is, the contact point corresponding to the anode I/O).

Optionally, the thickness of the passivation layer can be 0.5 μm ~ 2 μm, preferably 1 μm; the material for making the passivation layer can be Si ₃ N ₄ .

In addition, based on the molded ESD protection device, the back metal can also be thinned to a certain extent (as long as the degree of reduction does not affect the normal operation of the ESD protection device) to further reduce the size of the device.

This application further proposes an ESD protection device, which is prepared using the preparation method of the ESD protection device described in the above embodiments; since this ESD protection device adopts all the technical solutions of all the above embodiments, it at least has All technical effects brought by the technical solutions of the above embodiments will not be described again here.

In summary, for the ESD protection device preparation method and ESD protection device provided in the embodiments of the present application, by manufacturing an ESD protection device that can use a P+ substrate as a cathode, there is no need to manufacture it from the upper surface layer of the ESD protection device. cathode, so that the manufacturing size of the device can be reduced while maintaining the current flow capacity of the device, meeting the requirements for smaller device packaging, obtaining a low-capacitance vertical structure large flyback ESD protection device, and packaging the ESD protection device By drawing out the cathode of the device from the P+ substrate, grounding wires can be avoided during device packaging, thereby reducing packaging costs.

It should be noted that, in this document, the terms "include", "comprises" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, device, article or method that includes a series of elements not only includes those elements, It also includes other elements not expressly listed or inherent in the process, apparatus, article or method. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, apparatus, article or method that includes that element.

The above are only preferred embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly used in other related The technical fields are all equally included in the scope of patent protection of this application.

Claims (10)

1. A method of manufacturing an ESD protection device comprising:

providing a P+ substrate, forming a P-epitaxial layer on the P+ substrate, and forming an N-epitaxial layer on the P-epitaxial layer;

forming two P+ isolation regions which longitudinally penetrate through the N-epitaxial layer, wherein the two P+ isolation regions are a first P+ isolation region and a second P+ isolation region respectively;

forming a P well region in the N-epitaxial layer between the first P+ isolation region and the second P+ isolation region;

forming a first n+ injection region and a first p+ injection region within the N-epitaxial layer between the first p+ isolation region and the P-well region, and forming a second n+ injection region at a boundary crossing between the N-epitaxial layer and the P-well region, and forming a second p+ injection region and a third n+ injection region within the P-well region; the first P+ injection region is arranged between the first N+ injection region and the P well region; the second P+ injection region is arranged between the second N+ injection region and the third N+ injection region, and the third N+ injection region is arranged between the second P+ injection region and the second P+ isolation region;

forming isolation trenches longitudinally penetrating the N-epitaxial layer between the first N+ injection region and the first P+ injection region and between the P well region and the second P+ isolation region respectively;

wherein the cathode of the ESD protection device is fabricated based on the p+ substrate.

2. The method of manufacturing an ESD protection device according to claim 1, further comprising:

the annealing temperature in the P+ isolation region forming process is 1200-1250 ℃, and the annealing time is 1-2 hours.

3. The method of manufacturing an ESD protection device according to claim 1, further comprising:

the annealing temperature in the P well region forming process is 1000-2000 ℃ and the annealing time is 2-3 hours.

4. The method of manufacturing an ESD protection device according to claim 1, further comprising:

in the process of forming the first P+ injection region and the second P+ injection region, the injected P+ dose is 1.0E15/cm & lt- & gt 1.0E16/cm;

and in the process of forming the first N+ injection region, the second N+ injection region and the third N+ injection region, the injected N+ dose is 1.0E15/cm-1.0E16/cm.

5. The method of manufacturing an ESD protection device according to claim 1 or 4, further comprising:

in the process of forming a first N+ injection region, a first P+ injection region, a second N+ injection region, a second P+ injection region and a third N+ injection region, a first annealing process and a second annealing process are carried out, wherein the annealing temperature of the first annealing process is 1100-1200 ℃ and the annealing time is 10-20 seconds; the annealing temperature of the second annealing process is 800-900 ℃ and the annealing time is 30-60 minutes.

6. The method of claim 1, wherein the step of forming isolation trenches longitudinally penetrating the N-epi layer between the first n+ implant region and the first p+ implant region, and between the P well region and the second p+ isolation region, respectively, comprises:

deep grooves longitudinally penetrating through the N-epitaxial layer are formed between the first N+ injection region and the first P+ injection region and between the P well region and the second P+ isolation region respectively;

filling isolation medium into the two deep grooves until an isolation layer with a preset thickness is formed on the N-epitaxial layer, so that the deep grooves form isolation grooves, wherein the preset thickness is 2-3.5 mu m;

and removing the isolation layer.

7. The method of manufacturing an ESD protection device according to claim 1 or 6, wherein after the step of forming isolation trenches longitudinally penetrating the N-epitaxial layer between the first n+ implantation region and the first p+ implantation region and between the P well region and the second p+ isolation region, respectively, further comprises:

and forming an oxide layer covering the N-epitaxial layer, the first P+ isolation region, the second N+ injection region and the upper surface of the isolation groove on the N-epitaxial layer.

8. The method of manufacturing an ESD protection device of claim 7, wherein after the step of forming an oxide layer on the N-epi layer covering the N-epi layer, the first p+ isolation region, the second n+ implant region, and the upper surface of the isolation trench, further comprising:

forming a first metal layer on the second P+ injection region, the third N+ injection region and the second P+ isolation region so as to electrically connect the second P+ injection region, the third N+ injection region and the second P+ isolation region;

and forming a second metal layer on the first N+ implantation region and the first P+ implantation region to connect the first N+ implantation region and the first P+ implantation region.

9. The method of manufacturing an ESD protection device of claim 8, further comprising:

and forming passivation layers on the first metal layer and the second metal layer, wherein wiring points are reserved in the passivation layer above the second metal layer.

10. An ESD protection device, characterized in that the ESD protection device is manufactured using the manufacturing method of the ESD protection device according to any one of claims 1-9.