JP4918063B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to embedding a gate electrode and a source electrode in a plurality of trenches to obtain a semiconductor device having a low on-resistance and a small gate capacitance. The present invention relates to a semiconductor device and a method for manufacturing the same, in which the inserted source electrode is conductively connected to an auxiliary source electrode disposed in an exposed portion by effective means.

 Generally, in a semiconductor device, a high breakdown voltage type semiconductor device is required according to its application. In order to obtain such a high breakdown voltage type semiconductor device, it is known that the drift region is made of a material having a high specific resistance and the thickness of the drift region is increased. On the other hand, such a high breakdown voltage type semiconductor device exhibits a high on-resistance characteristic due to a large voltage drop in the drift region during operation, and there is a trade-off relationship between the breakdown voltage and the on-resistance. In particular, for unipolar semiconductor devices such as power MOSFETs, there is a physical limit value called silicon limit, and the minimum value of on-resistance at a certain withstand voltage is determined, and the on-resistance cannot be further reduced. It was said.

  In such a technical background, Patent Document 1 proposes a power MOSFET capable of realizing an on-resistance less than 1/4 of the silicon limit.

  FIG. 10 is a cross-sectional view showing the configuration of the main part of the power MOSFET proposed by the above specification.

As shown in FIG. 10, this power MOSFET 100 includes a semiconductor substrate 101, a drift region 102 formed on one surface of the semiconductor substrate 101, a channel region 103 and a source region 104 sequentially formed on one surface of the drift region 102. Trench 105 reaching the drift region 102 from the surface of the source region 104 through the source region 104 and the channel region 103, two-stage gate electrodes 106 ₁ , 106 ₂ embedded in the trench 105, and the gate electrode 106 ₁ and the first insulator 107 ₁ is filled between the trench 105 walls, a second insulator 107 ₂ filled between the gate electrode 106 ₂ and the trench 105 walls, formed on the other surface of the semiconductor substrate 101 Drain electrode 108 and a source electrode 109 formed on the exposed surface of the source region 104. It is. In the power MOSFET 100 shown in FIG. 10, the externally arranged gate electrode is not shown.

In the power MOSFET 100 having such a configuration, the gate electrodes 106 ₁ and 106 ₂ disposed in the trench 105 have a two-stage configuration, and the second insulator 107 ₂ on the bottom side of the trench 105 has a thick film. Since the electric field strength generated at the corner of the trench 105 is relaxed, thereby providing high breakdown voltage characteristics, the impurity concentration of the drift region 102 is configured to change linearly in the thickness direction. Time low on-resistance characteristics. When the power MOSFET 100 is a power MOSFET having a withstand voltage of 60 V, the on-resistance is 40 μΩcm ² and can realize an on-resistance less than ¼ of the silicon limit.

As described above, the power MOSFET 100 disclosed in Patent Document 1 can achieve a low on-resistance, but on the other hand, the area occupied by the gate electrodes 106 ₁ and 106 ₂ is large. Therefore, the capacitance between the gate and the drain increases, and as a result, there is a problem that the power MOSFET 100 cannot be made to respond at high speed.

  To solve this problem, instead of using a two-stage gate electrode arranged in the trench, a source electrode covered with a thick insulator is embedded in the bottom of the trench, and the gate is placed on the source electrode. By forming an electrode, a power MOSFET that can obtain a low on-resistance characteristic while maintaining a high breakdown voltage characteristic and that can reduce the capacitance between the gate and the drain is disclosed in Patent Document 2. Newly proposed.

  FIG. 11 is a cross-sectional view showing a main configuration of a power MOSFET newly proposed by the above specification.

  As shown in FIG. 11, the power MOSFET 110 includes a semiconductor substrate 111, a drift region 112 formed on one surface of the semiconductor substrate 111, a channel region 113 and a source region 114 sequentially formed on one surface of the drift region 112. Trench 115 reaching the drift region 112 from the surface of the source region 114 through the source region 114 and the channel region 113, the source electrode 116 and the gate electrode 117 separately embedded in the trench 115, the source electrode 116 and the trench 115, a first insulator 118 filled between the walls, a second insulator 119 filled between the gate electrode 117 and the trench 115 wall, and a drain electrode 120 formed on the other surface of the semiconductor substrate 111. And a source electrode 121 formed on the exposed surface of the source region 114. Eteiru. In the power MOSFET 110 shown in FIG. 11, the externally arranged gate electrode is not shown.

In the power MOSFET 110 configured as described above, the source electrode 116 filled with the thick first insulator 118 is embedded on the bottom surface side in the trench 115, and the thickness is above the source electrode 116 in the trench 115. By forming the gate electrode 117 filled with the thin second insulator 119, it is possible to obtain a low on-resistance characteristic substantially the same as the characteristic exhibited by the power MOSFET 100 while maintaining a high breakdown voltage characteristic. The capacitance between the gate and the drain can be reduced.
US Pat. No. 5,637,898 US Pat. No. 5,998,833

 The power MOSFET 110 disclosed in Patent Document 2 can achieve low on-resistance characteristics and low gate capacitance characteristics. In this case, in order for the power MOSFET 110 to exhibit the above characteristics, the source electrode 116 embedded in the trench 115 needs to be conductively connected to the externally arranged source electrode 121.

  However, the power MOSFET 110 disclosed in Patent Document 2 is technically related to what connection means is used to conductively connect the source electrode 116 embedded in the trench 115 to the externally arranged source electrode 121. There is no disclosure, and when actually manufacturing such a power MOSFET 110, it is completely unknown what type of connection means should be adopted.

  The present invention has been made in view of such a technical background, and an object thereof is to conductively connect a source electrode embedded in a trench and a source electrode provided on the surface of a semiconductor device by a suitable connection means. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same.

 In order to achieve the above object, the present invention employs the following means.

A first conductivity type first semiconductor layer; a first conductivity type second semiconductor layer adjacent to the first semiconductor layer; a second conductivity type third semiconductor layer adjacent to the second semiconductor layer; A fourth semiconductor layer of the first conductivity type adjacent to the three semiconductor layers, a plurality of trenches that penetrate the third semiconductor layer and reach the second semiconductor layer, and are arranged on the bottom surface side in the trench, A coated internal source electrode; a gate electrode disposed on an upper side of the internal source electrode and coated with an insulating film; a drain electrode electrically connected to the first semiconductor layer; and the fourth semiconductor layer And a source electrode electrically connected to the external gate electrode outside the external gate electrode, the external gate electrode connecting the gate electrode to the outside, and the internal source electrode outside the gate electrode. Equipped with an external source electrode that connects to the outside . In order to achieve the above object, a semiconductor device according to the present invention includes a first conductivity type semiconductor substrate, a drain electrode disposed on one surface of the semiconductor substrate, and a first conductivity formed on the other surface of the semiconductor substrate. Type drift region, a second conductivity type channel region formed on the other surface of the drift region, a first conductivity type source region formed on the other surface of the channel region, and the source region and the channel region, respectively. A plurality of trenches reaching the drift region, an internal source electrode disposed on the bottom surface side in each trench and filled with the first insulating film, a part on the entrance side in each trench, and the remaining part on each trench Are arranged on the outside, partly filled with the second insulating film, the remaining part is covered with the first insulating film, and arranged on the first insulating film, partly extending into the source region External saw And an external gate electrode disposed on the first insulating film and conductively connected to the second conductor, the internal source electrode in each trench being partly along the trench wall A rising portion that rises and an extending portion that is connected to the rising portion and extends in the outer direction of each trench are provided, and the extending portion is electrically connected to the external auxiliary source electrode disposed on the first insulating film. These means are provided.

  According to the first means, in order to conductively connect the internal source electrode embedded in each trench and the external source electrode disposed on the surface of the semiconductor device, the internal source electrode disposed in each trench The structure includes a rising portion that rises along a side wall surface of the trench and a extending portion that extends to the rising portion and extends in the outward direction of the trench. Is electrically connected to the external auxiliary source electrode disposed on the surface of the semiconductor device, so that the internal source electrode embedded in each trench and the external auxiliary source electrode can be easily and An effective conductive connection can be achieved.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes: a step of forming a drift region on one surface of a semiconductor substrate; a step of forming a plurality of trenches by etching in the drift region; A step of forming a first insulating film on the drift region including the step of forming a first conductor in the plurality of trenches and the first insulating film, and etching the first conductor to form a bottom surface in the plurality of trenches. Forming the internal source electrode composed of the arranged internal source electrode, the rising portion rising along the trench wall and the extending portion connected thereto, and forming the first insulating film again on the drift region including the internal source electrode A step of etching the first insulating film to remove each first insulating film on the inlet side and the plurality of trenches in the plurality of trenches, a portion from which the first insulating film has been removed A step of forming a second insulating film, a step of forming a second conductor on the second insulating film including the inside of the plurality of trenches, an interior disposed on the inlet side in the plurality of trenches by etching the second conductor A step of forming a gate electrode and an internal gate electrode connected to the gate electrode; a step of forming a first insulating film three times on a drift region including the internal gate electrode; and a drift region between a plurality of trenches by etching the first insulating film A step of forming an opening reaching the extending portion on the extending portion and the groove portion reaching the extending portion, ion implantation through the groove portion, and a channel region and a source region stacked in the drift region between the trenches, and the same conductivity type region as the channel region Forming a single layer portion, forming a electrode material on the source region including the inside of the groove, the first insulating film, and the other surface of the semiconductor substrate, etching the electrode material, and externally Over the source electrode, the external gate electrode, the external auxiliary source electrode, a semiconductor device and a process of forming the external drain electrodes each of which comprises a second means to be manufactured.

  According to the second means, the internal source embedded in each trench is electrically connected to the internal source electrode embedded in each trench and the external source electrode disposed on the surface of the semiconductor device. When forming the electrodes, a rising portion that rises along the side wall surface of the trench and a extending portion that continues to the rising portion and extends in the outward direction of the trench are formed in a part of each internal source electrode. As a result, there is no need to provide a separate step of forming a connection means between each internal source electrode and the external auxiliary source electrode, and without increasing the number of steps and using simple connection means, The internal source electrode embedded in the semiconductor device and the external source electrode (external auxiliary source electrode) arranged on the surface of the semiconductor device can be conductively connected.

According to the semiconductor device of the present invention, in order to conductively connect the internal source electrode embedded in each trench and the external source electrode disposed on the surface of the semiconductor device, the internal source electrode disposed in each trench The structure includes a rising portion that rises along a side wall surface of the trench and a extending portion that extends to the rising portion and extends in the outward direction of the trench. Is electrically connected to the external auxiliary source electrode disposed on the surface of the semiconductor device, so that the internal source electrode embedded in each trench and the external auxiliary source electrode can be easily and There is an effect that the conductive connection can be effectively performed.

  In addition, according to the method of manufacturing a semiconductor device of the present invention, the internal source electrode embedded in each trench and the external source electrode disposed on the surface of the semiconductor device are electrically connected to each other in the trench. When forming the arranged internal source electrode, a rising portion that rises along the side wall surface of the trench and a extending portion that continues to the rising portion and extends in the outward direction of the trench. Therefore, there is no need to separately provide a step for forming a connection means between each internal source electrode and the external auxiliary source electrode, and the number of steps is not increased and only a simple connection means is used. Thus, the internal source electrode embedded in each trench can be conductively connected to the external source electrode (external auxiliary source electrode) disposed on the surface of the semiconductor device. There is an effect that that.

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 to FIG. 4 show the configuration of the main part of the semiconductor device according to the first embodiment of the present invention, showing an example of an n-type power MOSFET as the semiconductor device. FIG. FIG. 1B is a top view showing an electrode member in the power MOSFET, and FIG. 2A is an AA ′ line in FIGS. 1A and 1B. 2B is a sectional view taken along the line BB ′, FIG. 3A is a sectional view taken along the line CC ′, and FIG. 3B is a sectional view taken along the line DD ′. 4A is a cross-sectional view of the EE ′ line portion, and FIG. 4B is a cross-sectional view of the FF ′ line portion.

In FIGS. 1A and 1B to FIGS. 4A and 4B, 1 is an n-type semiconductor substrate, 2 is an n-type epitaxial region (drift region), 3 is a p-type channel region, and 4 is an n-type. source region, the p-type region 5, the trenches formed in the active region 20 ₁ 6, trench 6S is formed in the peripheral region 20 _2, 7 internal source electrode is embedded in the trench 6, 7 ₁ rising portion, 7 ₂ is an extension portion, 7S is an internal source electrode embedded in the trench 6S, 8 is an internal gate electrode, 8 ₁ is an insertion portion, 8 ₂ is an outer portion, 8 ₃ is a connection portion, and 9 is an oxide film (first insulation) body), the gate oxide film 10 (second insulator), the n + -type (high impurity concentration) regions 11, 12 outside the drain electrode, 13 an external source electrode, 13 ₁ projecting portion, 13A is an external auxiliary source electrode , 13A ₁ connecting portion, 14 an external gate electrode, 14 ₁ connecting portion 15 guard ring 15 ₁ connecting portion, 16 a polysilicon four-layer protective diode, 17 denotes a gate pad. Further, 20 is a semiconductor chip, 20 ₁ active region, 20 ₂ is the peripheral region.

As shown in FIG. 1A, a semiconductor chip 20 constituting a power MOSFET excluding electrode members is provided with a stripe-shaped trench 6 in an active region (no symbol in FIG. 1). An internal source electrode 7 and an internal gate electrode 8 are embedded in 6. The peripheral region of the semiconductor chip 20 (no symbol in FIG. 1) is connected portion 8 ₃ is provided for these interconnections internal gate electrode 8, the rising portion 7 of each internal source electrode 7 so as to surround the connecting portion 8 _{3 1} interconnected extended portion 7 ₂ is provided through. Connection 8 _3, trench 6S is provided in the lower region, the internal source electrode 7S is buried disposed corresponding to the forming position of the trench 6S. In the semiconductor chip 20, a gate pad 17 is provided at one corner, and a protection diode 16 is provided around the gate pad 17.

Further, as shown in FIG. 1B, the electrode member constituting the power MOSFET is made of, for example, aluminum, and occupies a wide position corresponding to the active region (no symbol in FIG. 1). The external source electrode 13 is provided, and the external gate electrode 14 is provided on the three sides excluding one side of the external source electrode 13 with a predetermined distance from the external source electrode 13, and the external gate electrode 14 is provided around the external gate electrode 14. An external auxiliary source electrode 13 </ b> A is provided at a predetermined interval from 14. The external gate electrode 14 is conductively connected to the gate pad 17, and the external auxiliary source electrode 13 A is conductively connected to the external source electrode 13 on one side of the external source electrode 13. A guard ring 15 is provided at the outer edge of the peripheral area (not shown in FIG. 1). In this case, the lower region between the external source electrode 13 and the external gate electrode 14 are disposed connection 8 _3, the internal source electrode 7 in the lower region between the external gate electrode 14 and the external auxiliary source electrode 13A stretching section 7 ₂ are arranged.

Next, as shown in FIG. 2 (a), A-A ' line portion in the power MOSFET is right in the active region 20 _1, the left side is a peripheral region 20 _2, and n-type semiconductor substrate 1, It has an external drain electrode 12 formed on one surface and an n-type epitaxial layer 2 formed on the other surface.

Active region 20 ₁ includes a p-type channel region 3 formed in the n-type epitaxial layer 2, and a p-type channel region 3 n-type source region 4 formed on a plurality of trenches 6, n-type It reaches the n-type epitaxial layer 2 through the source region 4 and the p-type channel region 3. Each trench 6, the internal source electrode 7 filling thicker oxide film 9 on the inner bottom surface side is embedded disposed, the inner insertion portion 8 of the _internal inlet-side internal gate electrode 8 filled thinned by a gate oxide film 10 is buried arranged, linked outer portion ₈₂ is disposed on the inner insertion portion ₈₁ on the outside of the respective trenches 6. The outer portion ₈₂ and upper periphery thereof inside the gate electrode 8 is covered by the oxide film 9, an external source electrodes 13 are formed and arranged on the oxide film 9. The external source electrode 13 is provided between the trenches 6 and includes a plurality of projecting portions 13 ₁ projecting downward. These projecting portions 13 ₁ are formed in the p-type channel region 3 through the oxide film 9 and the n-type source region 4. Has reached. A p-type region is formed in n-type epitaxial layer 2 at the boundary between active region 20 ₁ and peripheral region 20 ₂ .

Peripheral region 20 ₂ is in a position adjacent to the active region 20 _1, extending in the n-type epitaxial layer 2, the trench 6S the same depth as the trenches 6 are formed and arranged. The trench 6S is filled thickly with the oxide film 9, and an internal source electrode 7S having a length substantially equal to the depth of the trench 6S is embedded. Further, as will be described later, the internal source electrode 7 disposed in each trench 6 is connected to the rising portion 7 ₁ rising along the wall of the trench 6 and a rising portion 7 ₁ , and is n-type. the extending portion 7 ₂ is provided extending over the epitaxial layer 2. Each extension part 7 _2, in which also serves as a field plate with an internal source electrode 7S, each rising portion ₇₁ in the peripheral region 20 ₂ with interconnecting is also connected to the internal source electrode 7S in the trench 6S. On stretching section 7 ₂ is covered with the oxide film 9, and the external gate electrode 14 and the external auxiliary source electrode 13 spaced on the oxide film 9 is formed and arranged. An n + type region 11 is formed on the n type epitaxial layer 2 at the edge, and a guard ring 15 is formed and disposed on the n + type region 11. External auxiliary source electrode 13A has a connecting portion 13A ₁ which protrudes downward, the connecting portions 13A ₁ is conductively connected to the extension part 7 ₂ through the opening of the oxide film 9. The guard ring 15 has a connecting portion 15 ₁ which protrudes downward, the connecting portion 15 ₁ is connected to the n + -type region 11 through openings in the oxide film 9. Although not shown in FIG. 2 (a), the external gate electrode 14 is conductively connected to the internal gate electrode 8 through the connecting section 8 _3.

Incidentally, in FIG. 2 (a), but one trench 6S in the peripheral region 20 ₂ are formed and arranged, may increase the number of trenches 6S according to the breakdown voltage level, etc., whereas, formed and arranged trenches 6S You don't have to. When it expand the arrangement interval between the trenches 6 outermost of the active region 20 ₁ adjacent thereto and the trench 6S, electric field becomes stronger at the pn junction between the p-type region 5 and the n-type epitaxial layer 2, an avalanche Since there is a possibility of breakdown, the arrangement interval between the trench 6S and the adjacent trench 6 is preferably 1.2 times or less with respect to the mutual interval between the trenches 6 in consideration of variations in the manufacturing process. .

The field plate constituted by the extending portion 7 ₂ and the internal source electrode 7S is used for relaxing the electric field in the peripheral region 20 ₂ , and the p-type region 5 is located between the trench 6S and the trench 6 adjacent thereto. This is used to relax the electric field of the gate oxide film 10. In this case, if the depth of formation of the p-type region 5 is the same as or deeper than the filling length in the depth direction of the gate oxide film 10, the electric field relaxation of the gate oxide film 10 can be effectively achieved. Can do. The guard ring 15 is used to increase the breakdown voltage around the guard ring 15.

In the above configuration, when a positive voltage is applied to the external gate electrode 14 during operation, the p-type channel region 3 is inverted, and the external source electrode 13 passes through the n-type source region 4, the n-type epitaxial layer 2, and the n-type semiconductor substrate 1 to the outside. A current flows through the drain electrode 12. At this time, since each internal source electrode 7 is connected to the external source electrode 13 through the rising portion 7 ₁ , the extending portion 7 ₂ , and the external auxiliary source electrode 13A, even if the impurity concentration of the n-type epitaxial layer 2 is increased, The electric field in the bottom region of each trench 6 is relaxed, and low on-resistance characteristics can be achieved while maintaining high breakdown voltage characteristics. Further, the area occupied by the internal gate electrode 8 is reduced, and a thick oxide film 9 is provided between the internal gate electrode 8 and the internal source electrode 7 below the internal gate electrode 8, so that it is smaller than a known MOSFET of this type. Thus, the gate-drain capacitance can be reduced, and a power MOSFET capable of high-speed response can be formed.

Next, as shown in FIG. 2 (b), B-B ' line portion in the power MOSFET, i.e. the portion along one trench 6 is left in the active region 20 ₁ and the right side peripheral areas 20 ₂ As in the configuration of FIG. 2A, the semiconductor device includes an n-type semiconductor substrate 1, an external drain electrode 12 formed on one surface, and an n-type epitaxial layer 2 formed on the other surface. Yes.

In the active region 20 ₁ , an internal source electrode 7 filled with a thick oxide film 9 is embedded on the inner bottom surface side of the trench 6, and the insertion portion 8 ₁ of the internal gate electrode 8 is disposed on the inner entrance side of the trench 6 thereon. Is placed. The internal gate electrode 8 has an outer portion 8 ₂ connected to the insertion portion 8 ₁ provided outside the trench 6, and an oxide film 9 is formed on the outer portion 8 ₂ and its periphery. The external source electrode 13 is formed and arranged on the substrate.

Peripheral region 20 _2, the part of the internal source electrode 7, and the rising portion ₇₁ which rises along the trench 6 walls, connected to the rising portion _71, the extending portion 7 ₂ provided that also serves as a field plate It is done. External auxiliary source electrode 13A through the oxide film 9 on the extended portion 7 ₂ is formed and arranged, is conductively connected to the external auxiliary source electrode 13A are in the extension portion 7 ₂ through connecting portions 13A _1. Further, electrically connected to the connection 8 ₃ is disposed through the oxide film 9 on the extended section 7 ₂ to the outer portion _82, the external gate electrode 14 is formed and arranged through the oxide film 9 on the connecting portions 8 ₃ Is done. The external gate electrode 14 is conductively connected to the connection portion 8 ₃ through the connecting portion 14 ₁ . In this way, the internal source electrode 7 buried disposed in each trench 6, in the peripheral region 20 ₂ along the trench 6 wall drawn to the surface area of the power MOSFET, the source electrode 13 through an external auxiliary source electrode 13A Conductive connection is made. The peripheral region 20 _2, similar to the configuration of FIG. 2 (a), formed trench 6S and p-type region 5, the internal source electrode 7S which also serves as a field plate with extended section 7 ₂ in the trench 6S is buried arranged The

If the structure shown in FIG. 2 (b), in the lower region of the connecting part 8 ₃ connected to the external gate electrode 14, the surface area of each internal source electrode 7 MOSFET power along the trench 6 wall drawn to, intended to be conductively connected to the external auxiliary source electrode 13A through the connecting portions 8 _3, it has a low on-resistance characteristics, and low gate - can be obtained MOSFET power having a source capacitance.

  Although not shown in FIG. 2, the external source electrode 13 is connected to one end of the polycrystalline silicon four-layer protection diode 16 together with the external auxiliary source electrode 13A, and the external gate electrode 14 is a polycrystalline silicon four-layer protection diode. 16 is connected to the other end.

Then, as shown in FIG. 3 (a), C-C ' line portion in the power MOSFET, namely portion along between two adjacent trenches 6 are left in the active region 20 _1, the right peripheral region ₂ , and has an n-type semiconductor substrate 1, an external drain electrode 12 formed on one surface thereof, and an n-type epitaxial layer 2 formed on the other surface, as in the configuration of FIG. is doing.

In the active region 20 ₁ , the p-type channel region 3 is formed on the upper side of the n-type epitaxial layer 2, and the protruding portion 13 ₁ between the adjacent trenches 6 extends from the external source electrode 13 through the oxide film 9 to the p-type channel region 3. reached, the protruding portion 13 ₁ and the p-type channel region 3 is connected.

Peripheral region 20 _2, except that the internal source electrode 7 and the rising portion ₇₁ that is not shown, substantially the same as the configuration shown in FIG. 2 (b), the oxide film 9 on the extended portion 7 ₂ through external auxiliary source electrode 13A and is formed and arranged, is conductively connected to the external auxiliary source electrode 13A are in the extension portion 7 ₂ through connecting portions 13A _1. A connecting portion 8 ₃ is disposed on the extending portion 7 ₂ via the oxide film 9, and an external gate electrode 14 is formed and disposed on the connecting portion 8 ₃ via the oxide film 9. The external gate electrode 14 is conductively connected to the connection portion 8 ₃ through the connecting portion 14 ₁ .

Subsequently, as shown in FIG. 3B, the DD ′ portion in the power MOSFET, that is, the portion along the portion close to one trench 6 between two adjacent trenches 6, the left side is the active region. 20 _1, right side a peripheral region 20 _2, similar to the arrangement of FIG. 3 (a), the n-type semiconductor substrate 1, and the external drain electrode 12 formed on one surface thereof, is formed on the other surface and an n-type epitaxial layer 2.

Active region 20 _1, n-type p-type channel region 3 above the epitaxial layer 2 is formed, n-type source region 4 is formed in a portion of the upper p-type channel region 3. An external source electrode 13 is formed and arranged on n type source region 4 with oxide film 9 interposed.

Since the peripheral region 20 ₂ is substantially the same as the configuration of the peripheral region 20 ₂ shown in FIG. 3A, the description of the configuration is omitted.

Next, as shown in FIG. 4 (a), E-E ' portion of the power MOSFET, i.e. the portion along three of the trench 6 and the gate pad 17, right in the active region 20 _1, around the left a region 20 _2, similar to the configuration of FIG. 3 (b), the n-type semiconductor substrate 1, and the external drain electrode 12 formed on one surface thereof, an n-type epitaxial layer 2 formed on the other surface Have.

Active region 20 ₁ is substantially the same as that of the active region 20 ₁ shown in FIG. 2 (a), the description of the configuration is omitted.

Peripheral region 20 _2, around the gate pad 17, n-type region 16n and the p-type region 16p polysilicon four layers arranged alternately protective diode 16 is filled disposed within oxide film 9. The protective diode 16 has one end connected to the auxiliary external source electrode 13A and the other end connected to the external gate electrode 14, and is protected when a voltage exceeding a certain level is applied between the source and gate of the power MOSFET. The diode 16 conducts, and serves to prevent the gate oxide film 10 and the like from being destroyed by a high voltage. The other configuration is substantially the same as that of the active region 20 ₁ shown in FIG. 2 (a), a description of the other configurations will be omitted.

Then, as shown in FIG. 4 (b), F-F ' portion of the power MOSFET, i.e. the portion along one trench 6 and the gate pad 17, right in the active region 20 _1, the left peripheral region a 20 _2, similar to the arrangement of FIG. 4 (a), the organic and n-type semiconductor substrate 1, and the external drain electrode 12 formed on one surface thereof, an n-type epitaxial layer 2 formed on the other surface is doing.

Active region 20 ₁ is substantially the same as that of the active region 20 ₁ shown in FIG. 2 (b), the description of the configuration is omitted.

The peripheral region 20 ₂ is substantially the same as that of the active region 20 ₁ shown in FIG. 4 (a), an explanation about the configuration is omitted.

  As described above, the power MOSFETs illustrated in FIGS. 2A, 2B, 3A, 3B, 3A, and 3B have the following characteristics, respectively. Have.

The first is as illustrated in FIG. 2 (b) and 4 (b), the rising portion ₇₁ provided on a part of the internal source electrode 7 buried disposed in each trench 6, the rising portion 7 ₁ startup along the trench 6 wall and provided extending portion 7 ₂ connected to each rising portion ₇₁ to the outside of the trench 6, by conductively connecting the extended portion 7 ₂ to the auxiliary external source electrodes 13A The point of connection to the external source electrode 13.

Its Second, the extended portion 7 _{and second} internal source electrode 7 are arranged in the peripheral region 20 ₂ of the semiconductor chip 20, in that also serves as the extended section 7 ₂ to the field plate. In general, the field plate may be connected to either the external gate electrode 14 or the external source electrode 13, but by connecting to the external auxiliary source electrode 13A, the internal source electrode 7 and the external auxiliary source electrode 13A There is no need to form a useless area for connecting the two.

  The third is that the trenches 6 of the power MOSFET are arranged in a stripe shape. The advantage of arranging each trench 6 in a stripe shape is that the interval between adjacent trenches 6 is always constant, so that the design for improving the withstand voltage and the avalanche resistance is facilitated, and the surface with high carrier mobility is provided. Can be channel surface, and so on. On the other hand, since the internal gate electrode 8 has a long stripe shape, the gate resistance due to the internal gate electrode 8 is increased. In the power MOSFET according to this embodiment, each stripe-shaped internal gate electrode 8 is provided. Since both ends of each are connected to the external gate electrode 14, it is possible to suppress an increase in gate resistance.

  5 (a), (b), (c) to FIGS. 8 (a), (b) are process diagrams showing one embodiment of a method for manufacturing a power MOSFET according to the present invention. It is sectional drawing which shows the structure of the principal part.

  Here, the manufacturing process of the power MOSFET according to this embodiment will be described with reference to FIGS. 5 (a), 5 (b), 5 (c) to 8 (a), 8 (b).

  First, as shown in FIG. 5A, an n-type epitaxial layer 2 is formed on one surface of an n-type semiconductor substrate 1.

Next, as shown in FIG. 5 (b), a plurality of trenches 6 are formed in the active region 20 ₁ in the exposed surface of the n-type epitaxial layer 2 by the photoresist process and the silicon etching process, simultaneously, the peripheral region 20 ₂ 1 Two trenches 6S are formed, and a thick oxide film 9 is formed on the exposed surface including the inside of each of the trenches 6 and 6S by thermal oxidation treatment and deposit treatment.

  Next, as shown in FIG. 5C, a conductor 7M is embedded in the trenches 6 and 6S, and at the same time, the conductor 7M is deposited on the oxide film 9.

Subsequently, as shown in FIG. 6A, the conductor 7M is subjected to anisotropic etching to form the internal source electrode 7. In this case, in each trench 6 in the active region 20 ₁ was etched with an adjusted etching time so that the internal source electrode 7 portion of the conductor 7M on the bottom portion of the trench 6 remains, also around region in 20 _2, enters an internal source electrode 7S remaining conductor 7M in trench 6S is placed, and the portions to be used as a field plate conductor 7M is a portion to be stretched part 7 ₂ remaining Do not etch.

  Next, as shown in FIG. 6B, a thick oxide film 9 is formed on the exposed surface including the inside of each trench 6.

Next, as shown in FIG. 6C, the oxide film 9 is anisotropically etched. In this case, for the active region 20 _1, etched oxide film 9 was adjusted the etching time so as to remain in an appropriate thickness on the internal source electrode 7 remaining in the trench 6, also in the peripheral region 20 ₂ Since the oxide film 9 is used as an insulating film and an end protection film of the semiconductor chip 20, no etching is performed.

  Subsequently, as shown in FIG. 7A, a thin gate oxide film 10 is formed in each trench 6.

  Next, as shown in FIG. 7B, a conductor 8M is buried in each trench 6, and at the same time, a conductor 8M is deposited on the oxide film 9.

Next, as shown in FIG. 7C, the conductor 8M is subjected to anisotropic etching to form an internal gate electrode 8. In this case, in the active region 20 _1, the inner insertion portion ₈₁ to the inside of each trench 6, external outer portion ₈₂ may remain respectively of each trench 6, and, in the peripheral region 20 _2, connecting portion 8 ₃ Etch so that (not shown) remains.

Subsequently, as shown in FIG. 8A, a thick oxide film 9 is formed again on the exposed surface including the internal gate electrode 8. Thereafter, the oxide film 9 existing between the trenches 6 in the active region 201 is etched. Next, the p-type channel region 3, the p-type region 5, the n-type source region 4 and the n-type region 11 are sequentially formed by ion implantation. At this time, the P-type channel region 3 and the p-type region 5 are simultaneously formed by implanting p-type ions, thereby simplifying the process steps. Thereafter, in order to connect the external source electrode 13, the external auxiliary source electrode 13A, the external gate electrode 14 and the guard ring 15 to the corresponding internal electrode portions, the oxide film 9 is etched to form a coupling hole. To do. Further, in the active region 201, silicon etching is performed in order to connect the p-type channel region 3 and the external source electrode 13, and the deep region from the surface of the oxide film 9 to the P-type channel region 3 through the n-type source region 4 is reached. forming an etch groove 91. In some cases, in order to make ohmic contact between the p-type channel region 3 and the external source electrode 13, p-type ions may be implanted after silicon etching.

Next, as shown in FIG. 8 (b), an aluminum (electrode material) on the exposed surface and the exposed surface of the n-type semiconductor substrate 1 including etching grooves 9 ₁ and the coupling hole. Thereafter, the aluminum is etched to form the external source electrode 13, the external auxiliary source electrode 13A, the external gate electrode 14, the guard ring 15, and the drain electrode 12 to manufacture the power MOSFET.

According to such a manufacturing method, each internal source electrode 7 and the external auxiliary source electrode 13A are electrically connected to each other, so that when the internal source electrode 7 embedded in each trench 6 is formed, each internal source electrode 7 is formed. 7 is formed with a rising portion 7 ₁ rising along the wall surface of the trench 6 and an extending portion 7 ₂ extending to the outside of the trench 6 and extending to the rising portion 7 ₁ . It is not necessary to provide a process for forming connection means between each internal source electrode 7 and external auxiliary source electrode 13A, the number of processes is not increased, and the internal structure embedded in each trench 6 can be used only by using simple means. Conductive connection between the source electrode 7 and the external auxiliary source electrode 13A becomes possible.

  9 (a) and 9 (b) show a second embodiment of the power MOSFET according to the present invention. FIG. 9 (a) excludes the electrode member as in FIG. 1 (a). FIG. 9B is a top view showing a power MOSFET, and FIG. 9B is a cross-sectional view of a portion along the line GG ′ in FIG.

  As shown in FIG. 9A, in the power MOSFET according to the second embodiment, the arrangement shape of the trench 6 is a mesh shape, and the internal source electrode 7 is provided on the bottom side in each trench 6. However, the internal gate electrode 8 is embedded and arranged on the entrance side, and the components other than the arrangement shape of each trench 6 in the power MOSFET of the second embodiment are the same as the power of the first embodiment. This is the same as the structure of the power MOSFET. For this reason, the configuration of the power MOSFET of the second embodiment will not be described further. In the power MOSFET of the second embodiment, the opening shape of each of the trenches 6 arranged in a mesh shape is a square as shown in FIG. 9A as long as it has a regular shape. It may be a shape, a circle, or a hexagon.

Further, as shown in FIG. 9 (b), G-G ' line portion in a power MOSFET of the second embodiment, i.e., the portion along one trench 6 columns, the left is the active region 20 ₁ , right a peripheral region 20 _2, similar to the arrangement in FIG. 2 (a), the n-type semiconductor substrate 1, and the external drain electrode 12 formed on one surface thereof, n-type epitaxial formed other surface Layer 2.

Active region 20 ₁ is substantially the same as that of the active region 20 ₁ shown in FIG. 2 (a), the description of the configuration is omitted.

Further, _second peripheral region 20 is substantially the same as that of the active region 20 ₁ shown in FIG. 2 (b), omitting description thereof for that configuration.

  According to the power MOSFET of the second embodiment, by arranging the trenches 6 in a mesh shape, the degree of integration of the cell portion can be improved and the on-resistance can be further reduced.

  Next, FIG. 12 is a circuit diagram when the power MOSFET according to the present invention is used in a DC-DC converter.

  In FIG. 12, 21 is a high-side power MOSFET, 22 is a low-side power MOSFET, 23 is a control IC, 24 and 25 are diodes, 26 is a Zener diode, 27 is an inductor, and 28 is a capacitor.

  The high-side power MOSFET 21 and the low-side power MOSFET 22 are connected in series, and the input DC voltage Vin is applied to both ends thereof. A diode 24 is connected in parallel to the high-side power MOSFET 21, and a diode 25 and a Zener diode 26 are connected in parallel to the low-side power MOSFET 22. A control IC 23 is connected between the gate of the high-side power MOSFET 21 and the gate of the low-side power MOSFET 22. One end of the inductor 27 is connected to the connection point between the high-side power MOSFET 21 and the low-side power MOSFET 22, and the output DC voltage Vout is taken out between the other end of the inductor 27 and the ground point.

  Generally, a power MOSFET used for synchronous rectification of a DC-DC converter requires a power MOSFET having a low on-resistance characteristic and a low gate capacity characteristic in order to increase the efficiency of the converter.

  In particular, the low-side power MOSFT 22 is mainly required to have high on-resistance characteristics for high efficiency, and the high-side power MOSFET 21 has low on-resistance characteristics and low gate capacitance characteristics. This is necessary for high efficiency.

  Since the power MOSFET according to the present invention can realize a low on-resistance characteristic and a low gate capacitance characteristic, it is effective when applied to either a low-side or high-side power MOSFET of a DC-DC converter. . In particular, since it has a low gate capacitance characteristic, when used for the high side, an improvement in the efficiency of the power supply device can be expected.

  In each of the above embodiments, the case where the semiconductor device is a power MOSFET has been described as an example. However, the semiconductor device according to the present invention is not limited to the power MOSFET, and is similar to the power MOSFET. The present invention can be similarly applied to other semiconductor devices.

1 is a top view showing a power MOSFET excluding an electrode member, and a top view showing an electrode member in the power MOSFET, which are the main configuration of the semiconductor device according to the first embodiment of the present invention. 2A and 2B are cross-sectional views of the A-A ′ line portion and the B-B ′ line portion of the power MOSFET according to the first embodiment in FIGS. 2A and 2B are cross-sectional views of a C-C ′ line portion and a D-D ′ line portion of the power MOSFET according to the first embodiment in FIGS. FIGS. 2A and 2B are cross-sectional views of an E-E ′ line portion and an F-F ′ line portion of the power MOSFET according to the first embodiment in FIGS. FIG. 3 is a first three process charts showing one embodiment of a method for manufacturing a power MOSFET according to the present invention, and is a cross-sectional view showing a configuration of main parts thereof. FIG. 4 is a next three process charts showing one embodiment of a method for manufacturing a power MOSFET according to the present invention, and is a cross-sectional view showing a configuration of a main part thereof. FIG. 4 is a next three process charts showing one embodiment of a method for manufacturing a power MOSFET according to the present invention, and is a cross-sectional view showing a configuration of a main part thereof. FIG. 4 is a final two process charts showing one embodiment of a method for manufacturing a power MOSFET according to the present invention, and is a cross-sectional view showing a configuration of main parts thereof. The 2nd Embodiment of the power MOSFET by this invention is shown, The top view showing the power MOSFET except an electrode member, and sectional drawing of the G-G 'line | wire part. It is sectional drawing which shows the principal part structure of power MOSFET proposed by patent document 2. FIG. FIG. 10 is a cross-sectional view showing a main configuration of a power MOSFET newly proposed by Patent Document 2. It is a circuit diagram at the time of using the power MOSFET by this invention for a DC-DC converter.

Explanation of symbols

1 n-type semiconductor substrate 2 n-type epitaxial region (drift region)
3 p-type channel region 4 n-type source region 5 p-type region 6 trench internal source electrode 6S formed in the active region 6S trench formed in the peripheral region 7 internal source electrode buried in the trench 6 7 ₁ rising portion 7 ₂ extending portion 7S Internal source electrode embedded in trench 6S 8 Internal gate electrode 8 ₁ Insertion portion 8 ₂ Outer portion 8 ₃ Connection portion 9 Oxide film (first insulator)
10 Gate oxide film (second insulator)
11 n + type (high impurity concentration) region 12 external drain electrode 13 external source electrode 13 ₁ protruding portion 13A external auxiliary source electrode 13A ₁ connecting portion 14 external gate electrode 14 ₁ connecting portion 15 guard ring 15 ₁ connecting portion 16 polycrystalline silicon 4 Layer protection diode 17 Gate pad 20 Semiconductor chip 20 ₁ Active area 20 ₂ Peripheral area

Claims (4)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type disposed on the first semiconductor layer;
A third semiconductor layer of a first conductivity type disposed on the second semiconductor layer;
A plurality of trenches penetrating the third semiconductor layer and the second semiconductor layer and reaching the first semiconductor layer;
An internal source electrode disposed on the bottom side in the trench and covered with an insulating film;
An internal gate electrode, at least part of which is disposed in a trench on the upper side of the internal source electrode, and is covered with an insulating film;
A drain electrode electrically connected to the first semiconductor layer;
In a semiconductor device comprising a source electrode electrically connected to the third semiconductor layer,
An external gate electrode for connecting the internal gate electrode to the outside through a connection portion;
An external auxiliary source electrode disposed on the outer periphery of the external gate electrode and connected to the internal source electrode;
A semiconductor device comprising an external source electrode disposed on an inner periphery of the external gate electrode and connecting the internal source electrode to the outside via an external auxiliary source electrode . The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the film thickness of the insulating film covering the internal source electrode in the trench is larger than the film thickness of the insulating film covering the internal gate electrode in the trench. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the external gate electrode is disposed in a peripheral region around an active region where the trench, the internal source electrode, and the internal gate electrode are disposed. The semiconductor device according to claim 1,
A semiconductor device characterized in that a connection portion for connecting an internal gate electrode to an external gate electrode connects a plurality of internal gate electrodes to each other.

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