CN112165329B - Capacitance digital converter for eliminating parasitic capacitance based on SAR logic - Google Patents
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Abstract
本发明公开了一种基于SAR逻辑消除寄生的电容数字转换器，属于新一代信息技术。针对现有技术中电容数字转换器整体性能不足的问题提出本方案，利用寄生补偿电流源阵列逐周期补偿，可消除测量通道的寄生电容影响。通过实现电容变化到连续时间的转换，克服传统C/V结构的限制，提高了电容检测范围。采用两级TDC量化结构，克服电容检测范围和检测精度的矛盾，实现高动态范围、高精度电容检测。除前端C‑T转换的电路之外，其他电路均为数字电路，面积，功耗得到优化。因此，本发明可以广泛应用于复杂环境下电容检测和传感，适用于高度集成的传感电路。
The invention discloses a capacitance-to-digital converter based on SAR logic to eliminate parasitics, which belongs to a new generation of information technology. Aiming at the problem of insufficient overall performance of the capacitance-to-digital converter in the prior art, this solution is proposed, and the parasitic capacitance influence of the measurement channel can be eliminated by using the parasitic compensation current source array to compensate cycle by cycle. By realizing the conversion from capacitance change to continuous time, the limitation of the traditional C/V structure is overcome, and the capacitance detection range is improved. The two-stage TDC quantization structure is adopted to overcome the contradiction between capacitance detection range and detection accuracy, and realize high dynamic range and high precision capacitance detection. Except for the front-end C-T conversion circuit, all other circuits are digital circuits, and the area and power consumption are optimized. Therefore, the present invention can be widely used in capacitance detection and sensing in complex environments, and is suitable for highly integrated sensing circuits.
Description
Technical Field
The present invention relates to a capacitive-to-digital converter, and more particularly, to a capacitive-to-digital converter for eliminating parasitics based on SAR logic.
Background
The capacitance-to-digital converter has the advantages of small volume, light weight, low power consumption and the like. With the increasing development of capacitive-to-digital converters, the performance of the capacitive-to-digital converters in terms of measurement accuracy, reliability and the like is continuously improved, and the capacitive-to-digital converters are widely applied to biomedical treatment, proximity sensing and touch screens. With the requirement of more complex detection environment and faster conversion speed, the capacitive-to-digital converter needs to have the characteristics of high resolution, high parasitic tolerance, high linearity, environmental interference resistance and the like.
In a monolithic integrated system, in a traditional capacitance-to-digital conversion scheme, a capacitor is charged and discharged, a charge amplifier is adopted to convert a capacitance value into a voltage value, and an A/D converter is adopted to convert an analog voltage value into a digital value for output. The above scheme has the following problems: the detection range is limited due to the continuous reduction of the process size and the limitation on the voltage threshold, and the dynamic range is reduced; the reduction of the process size enables the circuit to be more sensitive to the parasitic phenomenon, influences the conversion precision and is not suitable for complex and high-parasitic detection environment; the charge amplifier may cause charge leakage due to non-ideal switching, which reduces the detection accuracy. Each of the above factors reduces the overall performance of the capacitance-to-digital converter.
Disclosure of Invention
The invention aims to provide a capacitance-to-digital converter for eliminating parasitics based on SAR logic, which aims to overcome the problems of linearity and limited dynamic range of the traditional ADC capacitance-to-digital converter, and simultaneously eliminate the influence of high parasitic capacitance on capacitance detection precision through the SAR logic, thereby improving the anti-interference capability of the capacitance-to-digital converter.
In the capacitance-to-digital converter for eliminating the parasitic capacitance based on the SAR logic, a first discharge current source is connected in series with a switch K2 and then connected in parallel with a measured capacitance Cx and a parasitic capacitance Cpara between the negative end of a first high-speed comparator and the ground, and a reference level VhighThe negative end of the first high-speed comparator is connected with a switch K1 in series and then is connected with the negative end of the first high-speed comparator; the output end STO of the first high-speed comparator is respectively connected to the preprocessing logic module and the phase discriminator;
one end of the parasitic compensation current source array is grounded after being connected with the second discharge current source in parallel, and the other end of the parasitic compensation current source array is connected with the negative end of the second high-speed comparator after being connected with the switch K4 in series; the reference level VhighThe switch K3 is connected in series and then is respectively connected to the negative terminal of the second high-speed comparator and is grounded through the reference capacitor Cref; the output terminal STA of the second high-speed comparator is respectively connected into the preprocessing logic module and the phase discriminator;
reference level VlowConnecting the positive terminal of the first high-speed comparator and the second high-speed comparator simultaneouslyA positive terminal;
the phase discriminator outputs a control signal to the parasitic compensation current source array through an SAR control logic module, the SAR control logic module outputs an enable signal to the preprocessing logic module, and the preprocessing logic module outputs a corrected time digital signal to the outside through a time digital converter;
the parasitic compensation current source array comprises N binary current sources and N control switches, and the SAR control logic module controls the on and off of the binary current sources and the control switches one by one; the binary current sources are connected in series with the control switches in a one-to-one correspondence, and are connected between the source of the switch K4 and the ground after being connected in series.
The preprocessing logic module comprises two AND gates, two delay chains, two selectors and a resolver; the enabling signal is simultaneously input into two AND gates, the output end STO is connected with one AND gate and then is respectively connected with the input end of the delay chain Buffer1 and the input end of the resolver, and the output end STA is connected with the other AND gate and then is respectively connected with the input end of the delay chain Buffer2 and the other input end of the resolver; the in-phase signal of the output end of the resolver is input to the gating input end of the selector MUX1, and the reverse-phase signal is input to the gating input end of the selector MUX 2; the output end of the delay chain Buffer1 is respectively input into one input end of the two delay chains, and the output end of the delay chain Buffer2 is respectively input into the other input end of the two delay chains; the selector MUX1 outputs a lead signal to the time-to-digital converter and the selector MUX2 outputs a lag signal to the time-to-digital converter.
The time-to-digital converter is of a two-stage structure and comprises a counter TDC, a residual extraction module and a vernier TDC which are electrically connected in sequence; the TDC of the counter is used as a first-stage quantization circuit, performs coarse quantization on an input signal, and outputs high-order data which is a time digital signal; and the residual error extraction module and the vernier TDC are used as a second-stage quantization circuit, and the residual error of the first-stage quantization circuit is subjected to fine quantization and output as low-bit data of a time digital signal.
The capacitance-to-digital converter for eliminating the parasitic capacitance based on the SAR logic has the advantages that the parasitic capacitance influence of a measuring channel can be eliminated by utilizing the cycle-by-cycle compensation of the parasitic compensation current source array. By realizing the conversion from capacitance change to continuous time, the limitation of the traditional C/V structure is overcome, and the capacitance detection range is improved. And a two-stage TDC quantization structure is adopted, so that the contradiction between the capacitance detection range and the detection precision is overcome, and the high dynamic range and high precision capacitance detection is realized. Except for a front-end C-T conversion circuit, other circuits are digital circuits, and the area and the power consumption are optimized. Therefore, the invention can be widely applied to capacitance detection and sensing in complex environments and is suitable for highly integrated sensing circuits.
Drawings
FIG. 1 is a schematic diagram of a capacitance-to-digital converter for eliminating parasitics based on SAR logic according to the present invention;
FIG. 2 is a timing diagram of SAR logic spurious elimination of the present invention;
FIG. 3 is a block diagram of the preprocessing logic of the present invention;
figure 4 is a schematic block diagram of a TDC circuit of the present invention.
Detailed Description
As shown in fig. 1, the capacitance-to-digital converter for eliminating the parasitic capacitance based on the SAR logic according to the present invention includes a front-end C-T conversion circuit, a phase detector, a parasitic capacitance elimination circuit, a preprocessing logic module U1, and a time-to-digital converter, which are electrically connected in sequence.
The front-end C-T conversion circuit mainly comprises two capacitance charge and discharge channels; the first channel charging and discharging structure comprises a tested capacitor Cx, a parasitic capacitor Cpara, a switch K1, a switch K2, a first discharging current source and a first high-speed comparator. The negative terminals of the capacitor Cx to be measured and the parasitic capacitor Cpara are grounded, the positive terminals are connected to the drain terminals of the switch K1 and the switch K2 and the negative terminal of the first high-speed comparator, the source terminal of the switch K1 is connected to the reference level VhighAnd the source end of the switch K2 is connected to the ground through the first discharging current source. The positive terminal of the first high-speed comparator is connected to a reference level VlowAnd the output end is STO. The second channel charging and discharging structure comprises a referenced capacitor Cref, a switch K3, a switch K4, a second discharging current source and a second high-speed comparator. The negative terminal of the reference capacitor Cref is grounded, the positive terminal is connected to the switch K3, the drain terminal of the switch K4 and the negative terminal of the comparator, and the source terminal of the switch K3 is connected to the reference level VhighAnd the source end of the switch K4 is connected to the ground through a second discharging current source. The positive terminal of the second high-speed comparator is connected to the reference level VlowAnd the output terminal is STA. In this embodiment, the switches K1 and K3 are PMOS switches, and the switches K2 and K4 are NMOS switches.
The phase discriminator is internally provided with a D trigger, the data input end of the D trigger is connected with the output end STO of the first high-speed comparator, the clock input end of the D trigger is connected with the output end STA of the second high-speed comparator, and the output end of the D trigger is connected with the SAR control logic module.
The stray capacitance eliminating circuit comprises an SAR control logic module and a stray compensation current source array, the SAR control logic module outputs Nbit control signals and 1bit enabling signals cycle by cycle according to the output of the phase discriminator, the control signals are connected with a control switch of the stray compensation current source array, and the enabling signals are connected with the preprocessing logic module U1. The parasitic compensation current source array comprises N binary current sources and N control switches, and the SAR control logic module controls the on and off of the N binary current sources and the N control switches one by one. The binary current sources are connected in series with the control switches in a one-to-one correspondence, and are connected between the source of the switch K4 and the ground after being connected in series.
As shown in fig. 3, the preprocessing logic block U1 includes two and gates, a delay chain Buffer1, a delay chain Buffer2, a arbitrator, a selector MUX1, and a selector MUX 2. The enabling signal is simultaneously input into two AND gates, the output end STO is connected with one AND gate and then is respectively connected with the input end of the delay chain Buffer1 and the input end of the resolver, and the output end STA is connected with the other AND gate and then is respectively connected with the input end of the delay chain Buffer2 and the other input end of the resolver; the in-phase signal of the output end of the resolver is input to the gating input end of the selector MUX1, and the reverse-phase signal is input to the gating input end of the selector MUX 2; the output end of the delay chain Buffer1 is respectively input into one input end of the two delay chains, and the output end of the delay chain Buffer2 is respectively input into the other input end of the two delay chains; the selector MUX1 outputs a lead signal to the time-to-digital converter and the selector MUX2 outputs a lag signal to the time-to-digital converter.
As shown in fig. 4, the time-to-digital converter includes a two-stage quantization circuit. The device comprises a counter TDC, a residual extraction module and a vernier TDC which are electrically connected in sequence. The counter TDC is used as a first-stage quantization circuit to perform coarse quantization on an input signal, outputs Dout [ m-1] to Dout [ m-k ] total k-bit digital output, and outputs high-bit data of a time digital signal. And the residual error extraction module and the vernier TDC are used as a second-stage quantization circuit, the residual error of the first-stage quantization circuit is subjected to fine quantization, and m-k bit digital output including Dout [ m-k-1] to Dout [0] is output, so that m-bit quantization of time and digit is realized, and the output is low-bit data of the time and digit signal.
The capacitance digital converter for eliminating the parasitic capacitance based on the SAR logic is used for capacitance detection in a complex environment, and the working principle is as follows:
the front end C-T conversion circuit is used for capacitance readout, converting the detected capacitance into a continuous amount of time, and outputting to the phase detector circuit and the preprocessing logic module U1. The phase discriminator circuit converts the continuous time difference signal into a digital control signal and sends the digital control signal to the parasitic capacitance elimination circuit. The parasitic capacitance eliminating circuit eliminates the parasitic through an SAR control logic front end C-T circuit to form a closed loop. The preprocessing logic module U1 judges whether the output signal of the calibrated front-end C-T conversion circuit is positive or negative, decides the lead and lag signals and outputs the signals to the time-to-digital converter. The time-to-digital converter converts the time difference signal into a digital signal capable of reflecting the time difference.
As shown in FIG. 2, the calibration phase has N cycles, the parasitic capacitor Cpara and the reference capacitor Cref are charged and discharged in the nth clock cycle, and the charging voltage V is sethighVDD. The negative terminal voltages of the two high-speed comparators are respectively VXAnd VREFThe discharge current determines the voltage drop slope, and the positive terminal of the high-speed comparator is connected with a level VlowVDD/2. According to the different turnover time of the two high-speed comparators, pulse signals STO and STA with different phases are generated. The phase discriminator correspondingly generates a control signal Q which is input to the SAR control logic module, and the SAR control logic module outputs D [ n-1 ]]And the bit control signal controls the corresponding binary current source to perform current compensation. And after the N periods are finished, closing the parasitic elimination logic and outputting a post-stage circuit enable signal. The arbitrator judges the two-channel STO and STA time sequence signals and outputsThe output end sign is connected to the gating input ends of the two MUXs, the control signal is gated, the START is output to be a leading signal, and the STOP is output to be a lagging signal.
The SAR control logic module is an analog-to-digital conversion function for realizing successive approximation, and a person skilled in the art can directly apply various SAR control logic modules in the prior art without creative work. The specific physical meaning of the SAR control logic module is common knowledge of those skilled in the art, such as patents CN110995264A, CN110190850A, CN110190849A, CN109412593A, CN108495067A, etc., all of which are directly applied to the SAR control logic module as known technologies.
The binary current source is a current source realizing on/off states, and those skilled in the art can directly apply various binary current sources in the prior art without creative efforts. The specific physical meaning of the binary current source is common knowledge of those skilled in the art, such as patents CN105610441A, CN106652963A, CN206178524U, CN106953622A, CN109921798A, CN111313900A, etc., all of which directly apply the binary current source as the known technology.
In conclusion, the invention is based on SAR logic and two-stage TDC structure, carries out calibration and measurement in stages, and has the advantages of high linearity, small area, strong anti-interference capability, large detection dynamic range and the like. Meanwhile, the capacitance detection adopts a differential input structure, and the same reference voltage source is used for capacitance charging and discharging, so that the PVT robustness is higher; the SAR control logic and TDC may multiplex clocks.
It will be apparent to those skilled in the art that various other changes and modifications may be made in the above-described embodiments and concepts and all such changes and modifications are intended to be within the scope of the appended claims.
Claims (3)
1. A capacitance-to-digital converter based on SAR logic elimination parasitics is characterized in that a first discharging current source is connected in series with a switch K2 and then connected in parallel with a capacitor Cx and a parasitic capacitor Cpara to be detected between the negative end of a first high-speed comparator and the ground, and a reference level V is providedhighThe negative end of the first high-speed comparator is connected with a switch K1 in series and then is connected with the negative end of the first high-speed comparator; the output end STO of the first high-speed comparator is respectively connected to the preprocessing logic module and the phase discriminator;
one end of the parasitic compensation current source array is grounded after being connected with the second discharge current source in parallel, and the other end of the parasitic compensation current source array is connected with the negative end of the second high-speed comparator after being connected with the switch K4 in series; the reference level VhighThe switch K3 is connected in series and then is respectively connected to the negative terminal of the second high-speed comparator and is grounded through the reference capacitor Cref; the output terminal STA of the second high-speed comparator is respectively connected into the preprocessing logic module and the phase discriminator;
reference level VlowSimultaneously connecting the positive terminal of the first high-speed comparator and the positive terminal of the second high-speed comparator;
the phase discriminator outputs a control signal to the parasitic compensation current source array through an SAR control logic module, the SAR control logic module outputs an enable signal to the preprocessing logic module, and the preprocessing logic module outputs a corrected time digital signal to the outside through a time digital converter;
the parasitic compensation current source array comprises N binary current sources and N control switches, and the SAR control logic module controls the on and off of the binary current sources and the control switches one by one; the binary current sources are connected in series with the control switches in a one-to-one correspondence, and are connected between the source of the switch K4 and the ground after being connected in series.
2. The SAR-logic-based spurious elimination based capacitive-to-digital converter of claim 1, wherein the preprocessing logic module comprises two AND gates, two delay chains, two selectors and an arbitrator; the enabling signal is simultaneously input into two AND gates, the output end STO is connected with one AND gate and then is respectively connected with the input end of the delay chain Buffer1 and the input end of the resolver, and the output end STA is connected with the other AND gate and then is respectively connected with the input end of the delay chain Buffer2 and the other input end of the resolver; the in-phase signal of the output end of the resolver is input to the gating input end of the selector MUX1, and the reverse-phase signal is input to the gating input end of the selector MUX 2; the output end of the delay chain Buffer1 is respectively input into one input end of the two delay chains, and the output end of the delay chain Buffer2 is respectively input into the other input end of the two delay chains; the selector MUX1 outputs a lead signal to the time-to-digital converter and the selector MUX2 outputs a lag signal to the time-to-digital converter.
3. The SAR-logic-based parasitical capacitance-to-digital converter of claim 2, wherein the time-to-digital converter is of a two-stage structure and comprises a counter TDC, a residual extraction module and a vernier TDC, which are electrically connected in sequence; the TDC of the counter is used as a first-stage quantization circuit, performs coarse quantization on an input signal, and outputs high-order data which is a time digital signal; and the residual error extraction module and the vernier TDC are used as a second-stage quantization circuit, and the residual error of the first-stage quantization circuit is subjected to fine quantization and output as low-bit data of a time digital signal.
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| CN114114211B (en) * | 2021-12-03 | 2022-09-06 | 武汉市聚芯微电子有限责任公司 | TDC unit, TDC array and ranging system |
| CN114448439B (en) * | 2022-04-07 | 2022-07-29 | 电子科技大学 | A Two-Step Successive Approximation Analog-to-Digital Converter Based on TDC |
| US12176915B1 (en) | 2023-07-23 | 2024-12-24 | Beijing University Of Technology | Time signal processor based on multiplying phase interpolation circuit |
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