CN108398590B - Digital output voltage peak value detection method - Google Patents
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- G—PHYSICS
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- G01R19/04—Measuring peak values or amplitude or envelope of AC or of pulses
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/255—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques using analogue/digital converters of the type with counting of pulses during a period of time proportional to voltage or current, delivered by a pulse generator with fixed frequency
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Abstract
The invention discloses a digital output voltage peak value detection circuit, which adopts a voltage follower, a zero crossing voltage comparator, an A/D converter, a register, a binary value comparator, a three-input one-output AND gate and other circuits to realize digital output voltage peak value detection, thereby avoiding the situation that an analog voltage peak value detection circuit is firstly used for obtaining a peak value in the traditional scheme, and then the analog voltage peak value is used for obtaining digital output through the A/D conversion circuit. Compared with the prior art, the circuit is simple and reliable, is suitable for converting the voltage peak value of the high-frequency and low-frequency measured signal into the number, has high response speed and high measurement conversion precision, has large dynamic range of the peak detection voltage and can measure the voltage of mu V magnitude at the minimum, has strong digital facultative, and is suitable for main logic circuits such as TTL, COMS and the like, and small dynamic energy loss.
Description
Technical Field
The present invention relates to an electronic circuit structure, and more particularly, to a method for detecting a voltage peak value of a digital output.
Background
Peak detectors are widely used in feedback protection systems for nuclear radiation detection, geology, automatic gain control, oscillators, and RF power op-amps. The peak detector has analog output and digital output peak detector, and tracks weak signals under noise or interference environment, which requires the peak detector to have the characteristics of high detection precision, strong anti-interference capability, easy control and signal processing, etc., and the analog output peak detector cannot meet the design requirements due to the limitation of principle structure, and generally adopts the digital output peak detector. The current peak detection circuit for digital output has the defects of low peak detection precision, low sampling frequency, poor anti-interference capability, large capacitance integral nonlinearity, signal distortion, difficult system debugging and the like due to the adoption of the principle of analog peak detection and digital conversion.
The digital output voltage signal peak value measuring circuit is a core circuit for signal data acquisition in a basic electric quantity testing instrument, and traditionally, voltage signal peak value to digital conversion is mainly realized by firstly using an analog voltage peak value detecting circuit to obtain a voltage peak value, and then obtaining digital output through an A/D (analog to digital) converting circuit. The analog voltage peak detection circuit is mainly two kinds, one is a voltage type peak measurement circuit, and the other is a transconductance type peak measurement circuit. The voltage type peak value measuring circuit has simple principle, but has large integral nonlinearity, small passband and small dynamic range (the response to small-amplitude signals is poor, the signal is generally required to be more than 200 mV), and the effect of processing fast signals is not satisfactory. Although the transconductance type peak measurement circuit performs better than the voltage type, there are difficulties in circuit design. Since a transconductance amplifier is used, an integral factor is related to the capacitor C in the loop gain, in order to improve the linearity performance of the circuit, a capacitor C as large as possible is needed, and increasing the capacitor C reduces the passband and slew rate of the circuit. The voltage peak value detected by the two circuits has hysteresis, when the peak value changes from low level to high level, the subsequent circuit detects the level change, namely the peak value comes, and simultaneously starts to perform A/D conversion on the peak value output by the peak value detection circuit, so that obvious conversion errors are brought, the reliability of the circuit not only depends on the stability of the integral circuit, but also depends on the waveform of the detected signal, false triggering is easily caused on some slowly-changed signals, and the measurement result is seriously influenced.
Disclosure of Invention
The invention aims to provide a voltage peak value detection method of digital output, and aims to overcome the defects that the existing voltage peak value detection circuit of digital output mainly has low conversion accuracy from small signal analog voltage peak value to digital voltage peak value, low conversion speed, poor anti-interference capability, large signal distortion caused by capacitance integral nonlinearity, difficulty in system debugging and the like.
The invention solves the technical problems as follows: a voltage peak detection circuit for a digital output, comprising: the output end of the voltage follower is connected with the inverting input end of the voltage follower, the analog signal input end of the A/D converter and the non-inverting input end of the zero crossing voltage comparator, the N-bit binary digital signal output end of the A/D converter is connected with the N-bit binary digital input end of the register and one N-bit binary digital comparison input end of the binary value comparator in parallel according to the binary weight order, the N-bit binary digital output end of the register is connected with the other N-bit binary digital comparison input end of the binary value comparator in parallel according to the binary weight order, the system working clock is connected with the clock end of the A/D converter and the first input end of the AND gate, the output end of the zero crossing voltage comparator is connected with the second input end of the AND gate, the inverting input end of the zero crossing voltage comparator is connected with the ground, the output end of the binary value comparator is connected with the third input end of the AND gate, the output end of the AND gate is connected with the control end of the register, the binary value comparator is used for comparing the value of the N-bit binary number output by the digital signal output end of the A/D converter when one working pulse arrives and the value of the N-bit binary number registered by the register when the last working pulse arrives, when the zero crossing voltage comparator outputs a high level, when the value output by the digital signal output end of the A/D converter is larger than the value registered by the current register, the output end of the binary value comparator outputs a high level, when one working pulse arrives, the output end of the AND gate outputs a high level, the register is controlled by the high level output by the AND gate to store the N-bit binary digits output by the digital signal output end of the A/D converter when one working pulse arrives, when the value output by the digital signal output end of the A/D converter is smaller than or equal to the value registered by the current register, the output end of the binary value comparator outputs a low level, the output end of the AND gate outputs a low level, the register keeps the data registered when the last working pulse arrives under the control of the low level output by the AND gate, the binary value comparator continuously compares under the action of a system working clock, the register registers and outputs the maximum N-bit binary digits of a measured signal before the next working pulse, namely the output of the register tracks the peak value of the measured signal, when the output voltage of the register is smaller than or equal to the current value, the output end of the binary value comparator keeps the peak value, namely the output signal is equal to zero-crossing when the output voltage of the binary value is detected by the AND gate is not equal to the peak value, the high-level is detected, the output by the AND gate keeps the signal, and the output value is equal to zero-level, and the output by the logic circuit is kept.
The beneficial effects of the invention are as follows: the circuit adopts the circuits such as a voltage follower, a zero-crossing voltage comparator, an A/D converter, a register, a binary value comparator, a three-input one-output AND gate and the like to realize the voltage peak detection of digital output, thereby avoiding the situation that an analog voltage peak detection circuit is firstly used for obtaining a peak value in the traditional scheme, and then the analog voltage peak value is used for obtaining the digital output through the A/D conversion circuit. Compared with the prior art, the circuit is simple and reliable, is suitable for converting the voltage peak value of the high-frequency and low-frequency measured signal into the number, has high response speed and high measurement conversion precision, has large dynamic range of the peak detection voltage and can measure the voltage of mu V magnitude at the minimum, has strong digital facultative, and is suitable for main logic circuits such as TTL, COMS and the like, and small dynamic energy loss.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is evident that the drawings described are only some embodiments of the invention, but not all embodiments, and that other designs and drawings can be obtained from these drawings by a person skilled in the art without inventive effort.
Fig. 1 is a schematic circuit diagram of a voltage peak detection circuit of the present invention.
Detailed Description
The conception, specific structure, and technical effects produced by the present invention will be clearly and completely described below with reference to the embodiments and the drawings to fully understand the objects, features, and effects of the present invention. It is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and that other embodiments obtained by those skilled in the art without inventive effort are within the scope of the present invention based on the embodiments of the present invention. In addition, all connection relationships mentioned herein are not directly connected by single finger elements, but rather, a preferred circuit structure may be formed by adding or subtracting connection elements depending on the specific implementation. The technical features in the invention can be interactively combined on the premise of no contradiction and conflict.
Embodiment 1, referring to fig. 1, a voltage peak detection circuit of digital output includes: voltage follower, A/D converter, register composed of operational amplifier A 1, zero crossing voltage comparator a2 composed of voltage comparator, binary value comparator, three-input one-output AND gate
The IN-phase input end of the voltage follower a1 is connected with the tested signal U i, the output end of the voltage follower a1 is connected with the inverting input end of the voltage follower a1, the analog signal input end IN + of the A/D converter and the IN-phase input end of the zero-crossing voltage comparator a2, the N-bit binary digital signal output end D OUT of the A/D converter is connected with the N-bit binary digital input end D of the register and one N-bit binary digital comparison input end A of the binary value comparator IN a binary weight order, the N-bit binary digital output end Q of the register is connected with the other N-bit binary digital comparison input end B of the binary value comparator IN a binary weight order, the system working clock is connected with the clock end CLK of the A/D converter and the first input end X of the AND gate, the output end of the A/D converter a2 is connected with the second input end Y of the AND gate, the inverting input end of the voltage comparator a2 is connected with the ground, the output end Q of the binary value comparator is connected with the third input end of the AND gate,
The binary value comparator is used for comparing the value of the N-bit binary digits output by the A/D converter digital signal output end D OUT when one working pulse arrives and the value of the N-bit binary digits registered by the register when the last working pulse arrives, when the value output by the A/D converter digital signal output end D OUT is larger than the value registered by the register when the zero crossing voltage comparator a2 outputs a high level, the binary value comparator output end A > B outputs a high level, when one working pulse arrives, the AND gate output end W outputs a high level, the register is controlled by the high level output by the AND gate to store the N-bit binary digits output by the A/D converter digital signal output end D OUT when one working pulse arrives, when the value output by the digital signal output end D OUT of the A/D converter is smaller than or equal to the value registered by the register, the output end A > B of the binary value comparator outputs a low level, the output end W of the AND gate outputs a low level, the register is controlled by the low level output by the AND gate to keep the registered data unchanged when the last working pulse is kept, the binary value comparator continuously compares under the action of the system working clock, and the value O OUT of the maximum N-bit binary digit of the measured signal before the next working pulse arrives is registered and output by the register, namely the output of the register tracks the peak value of the measured signal. When the zero-crossing voltage comparator a2 outputs low level, the AND gate output end W outputs low level, the register is controlled by the low level output by the AND gate to keep the registered data unchanged, namely the voltage peak detection circuit of the digital output only tracks the tested signal Ui which is larger than or equal to zero, in addition, the gain of the voltage follower a1 is 1, the tested signal Ui is isolated, and the conversion precision of the circuit is improved.
Further description of the principles of the present invention: in the initial state, the voltage peak detection circuit of the digital output works under the action of the system working clock, when no working pulse exists, namely, before the detection circuit starts working, the register is reset and controlled by the register reset end R, at the moment, the register registers N-bit binary digit 0, because the working pulse state is low level 0, the signal is added to the input end X of the AND gate, the output end W of the AND gate outputs low level 0, the low level 0 is added to the control end CP of the register, at the moment, the register is locked, the register keeps registering N-bit binary digit 0, and the output end Q of the register outputs N-bit binary digit 0.
IN the working state, when the measured signal U i =0v, the output end of the voltage follower a1 is added to the analog signal input end IN + of the a/D converter, because the system working clock is connected to the clock end CLK of the a/D converter, under the action of the working pulse of the system working clock, the digital signal output end D OUT of the a/D converter outputs N-bit binary digits 0 IN parallel, the N-bit binary digits 0 are outputted to the N-bit binary digits input end D of the register and one N-bit binary digits comparison input end a of the binary value comparator IN parallel according to the binary digits high-low order, at this time, the output end Q of the register outputs N-bit binary digits to the other N-bit binary digits comparison input end B of the binary value comparator IN parallel, because the initial state of the register is N-bit binary digits 0, namely, the comparison input end B added to the binary value comparator is obviously the N-bit binary digits 0, the comparison end a is identical with the data on the comparison end B, the comparison state bit "a" B "is outputted by the low level" of the binary value comparator is controlled by the and the output end is not locked by the and the gate level 0, at this time, the output end is controlled by the gate level of the low level register.
When U i >0V, the digital signal output end D OUT of the A/D converter outputs N-bit binary digits larger than zero, the N-bit binary digits are output to the N-bit binary digit input end D of the register and one N-bit binary digit comparison input end A of the binary value comparator in parallel according to the binary weight bit order, the other N-bit binary digit comparison input end B added to the binary value comparator is N-bit binary digit 0, obviously, the data input to the comparison input end A of the binary value comparator is larger than the data input to the comparison input end B of the binary value comparator, the comparison state bit "A > B" of the binary value comparator outputs high level "1", and U i >0V, the zero crossing voltage comparator a2 outputs high level "1", when the working pulse of the system working clock is high level "1", the output end W of the AND gate is high level "1", the high level "1" is added to the control end CP of the register, the data output by the digital signal output end D OUT of the A/D converter is written into the register, similarly, under the action of the working pulse, the detection circuit constantly compares the N-bit binary digit output by the digital signal output end D OUT of the A/D converter (the N-bit binary digit comparison input end A added to the binary value comparator) with the N-bit binary digit output by the output end Q of the register (the N-bit binary digit comparison input end B added to the binary value comparator), if the data of the comparison input end A is larger than the data of the comparison input end B, the data output by the digital signal output end D OUT of the A/D converter replaces the original data of the register, if the data at the comparison input terminal a is smaller than the data at the comparison input terminal B, the original data of the register is kept unchanged, i.e. the N-bit binary digits output by the output terminal Q of the register are the peak signal O OUT of the digital output of the measured signal U i before the next working pulse arrives.
When U i is smaller than 0V, the zero-crossing voltage comparator a2 outputs low level 0, the AND gate output end W outputs low level, the low level 0 is added to the control end CP of the register through the AND gate, the register is locked, the register data is unchanged, and therefore the circuit is prevented from being interfered by negative level signals, in addition, the gain of the voltage follower a1 is 1, the tested signal U i is isolated, and the conversion precision of the circuit is improved.
The number of bits of the A/D converter is selected according to the measurement precision requirement, and the higher the number of bits of the A/D converter is, the higher the voltage peak value measurement is, and eight-bit, ten-bit, twelve-bit and sixteen-bit A/D converters can be adopted; the number of bits of the register and the binary value comparator is determined according to the selected number of bits of the A/D converter, namely the number of bits of the A/D converter is the same as the number of bits of the register and the binary value comparator, and the number of bits of the A/D converter is N.
The circuit adopts a voltage follower a1 formed by an operational amplifier A 1, a zero crossing voltage comparator a2 formed by a voltage comparator, an A/D converter, a register, a binary value comparator, a three-input one-output AND gate and other circuits to realize the voltage peak detection of digital output, thereby avoiding the situation that an analog voltage peak detection circuit is firstly used for obtaining a peak value in the traditional scheme, and then the analog voltage peak value is used for obtaining the digital output through the A/D conversion circuit. Compared with the prior art, the circuit is simple and reliable, is suitable for converting the voltage peak value of the high-frequency and low-frequency measured signal into the number, has high response speed and high measurement conversion precision, has large dynamic range of the peak detection voltage and can measure the voltage of mu V magnitude at the minimum, has strong digital facultative, and is suitable for main logic circuits such as TTL, COMS and the like, and small dynamic energy loss.
While the preferred embodiment of the present application has been described in detail, the application is not limited to the embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the application, and these modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (1)
1. A method of voltage peak detection for a digital output, wherein a voltage peak detection circuit for a digital output is applied, said circuit comprising: the device comprises a voltage follower, an A/D converter, a register, a zero crossing voltage comparator, a binary value comparator and a three-input one-output AND gate; the output end of the voltage follower is connected with the inverting input end of the voltage follower, the analog signal input end of the A/D converter and the non-inverting input end of the zero-crossing voltage comparator, the N-bit binary digital signal output end of the A/D converter is connected with the N-bit binary digital input end of the register and one N-bit binary digital comparison input end of the binary value comparator in parallel according to the binary weight order, the N-bit binary digital output end of the register is connected with the other N-bit binary digital comparison input end of the binary value comparator in parallel according to the binary weight order, the system working clock is connected with the clock end of the A/D converter and the first input end of the AND gate, the output end of the zero-crossing voltage comparator is connected with the second input end of the AND gate, the inverting input end of the A/D converter is connected with the ground, the output end of the binary value comparator is connected with the third input end of the AND gate, and the output end of the AND gate is connected with the control end of the AND gate;
The detection method comprises the following steps:
The binary value comparator is used for comparing the value of the N-bit binary digits output by the digital signal output end of the A/D converter when one working pulse arrives and the value of the N-bit binary digits registered by the register when the last working pulse arrives, when the zero crossing voltage comparator outputs a high level, the output end of the binary value comparator outputs a high level when the value output by the digital signal output end of the A/D converter is larger than the value registered by the register at present, when one working pulse arrives, the output end of the AND gate outputs a high level, the register is controlled by the high level output by the AND gate to store the N-bit binary digits output by the digital signal output end of the A/D converter when one working pulse arrives, when the value output by the digital signal output end of the A/D converter is smaller than or equal to the value registered by the register at present, the output end of the binary value comparator outputs low level, the output end of the AND gate outputs low level, the register is controlled by the low level output by the AND gate to keep the registered data unchanged when the last working pulse is carried out, the binary value comparator continuously compares under the action of a system working clock, the register registers and outputs the value of the maximum N-bit binary number of the measured signal before the next working pulse arrives, namely the output of the register tracks the peak value of the measured signal, when the zero crossing voltage comparator outputs low level, the output end of the AND gate outputs low level, the register is controlled by the low level output by the AND gate to keep the registered data unchanged, namely the voltage peak value detection circuit of the digital output only tracks the measured signal which is greater than or equal to zero, the gain of the voltage follower is 1, for isolation of the signal under test.
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| CN113608111B (en) * | 2021-06-10 | 2022-05-03 | 苏州瀚宸科技有限公司 | System for accurately detecting input signal amplitude |
| CN114584113A (en) * | 2022-04-15 | 2022-06-03 | 苏州大学 | Inverse integral peak detection system, method and apparatus |
| CN115060958B (en) * | 2022-06-20 | 2025-09-16 | 深圳市必易微电子股份有限公司 | Peak signal detection method with hysteresis, detection circuit and power supply circuit |
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| CN207164127U (en) * | 2017-07-07 | 2018-03-30 | 佛山科学技术学院 | A kind of voltage peak detection circuit of numeral output |
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| US3973197A (en) * | 1974-07-22 | 1976-08-03 | Koehring Company | Peak detector |
| US4769613A (en) * | 1985-12-05 | 1988-09-06 | Nec Corporation | Digitalized amplitude detection circuit for analog input signal |
| US4843307A (en) * | 1986-04-24 | 1989-06-27 | Kabushiki Kaisha Kenwood | Voltage difference measuring equipment |
| CN2172873Y (en) * | 1993-04-29 | 1994-07-27 | 西安交通大学 | Pulse peak voltmeter |
| CN1116743A (en) * | 1994-07-26 | 1996-02-14 | 黎民 | Arithmetic and processing unit for pulsing signal |
| JP4895161B2 (en) * | 2005-10-31 | 2012-03-14 | 横河電機株式会社 | Peak detection circuit and radiation measurement device |
| US20080048641A1 (en) * | 2006-07-06 | 2008-02-28 | Denso Corporation | Peak voltage detector circuit and binarizing circuit including the same circuit |
| CN101656536B (en) * | 2008-08-18 | 2012-06-20 | 中芯国际集成电路制造(上海)有限公司 | Phase-locked loop, and locking detection device and method thereof |
| JP5493916B2 (en) * | 2010-01-28 | 2014-05-14 | ミツミ電機株式会社 | Buck-boost DC-DC converter and switching control circuit |
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| CN104320094B (en) * | 2014-09-09 | 2017-06-16 | 成都四威功率电子科技有限公司 | Pulse signal standing-wave protecting circuit |
| JP6489605B2 (en) * | 2014-11-06 | 2019-03-27 | 合同会社ＳＰＣｈａｎｇｅ | A / D converter |
| CN206193088U (en) * | 2016-11-25 | 2017-05-24 | 佛山科学技术学院 | Detection circuitry of trackable peak value |
| CN106645881A (en) * | 2016-11-25 | 2017-05-10 | 佛山科学技术学院 | Detection circuit capable of tracking peak value |
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| CN207164127U (en) * | 2017-07-07 | 2018-03-30 | 佛山科学技术学院 | A kind of voltage peak detection circuit of numeral output |
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| GR01 | Patent grant |