CN104253613B - A kind of low pressure ultra-low-power high-precision comparator of SAR ADC - Google Patents

Abstract

The present invention relates to electronic circuit technology, and in particular to a kind of low pressure ultra-low-power high-precision comparator of SAR ADC.Including preamplifier, renewable latch, detector, comparator clock generator and transmission gate switch.Single renewable latch constitutes the relatively low thick comparator of precision；Preamplifier cascades renewable latch and constitutes precision smart comparator higher.A voltage range is given, when the input voltage of comparator falls outside voltage range, smart comparator does not work；When it falls within voltage range, smart comparator work.Beneficial effects of the present invention are that the comparator that different accuracy is selected by the size of detection comparator input voltage is worked, so as to reduce the power consumption of comparator in the case where comparator precision is not influenceed.Present invention is particularly suitable for low pressure super low-power consumption SAR ADC.

Description

A low-voltage, ultra-low-power, high-precision comparator for SAR ADC

technical field

The invention relates to electronic circuit technology, in particular to a low-voltage ultra-low power consumption high-precision comparator for SAR ADC.

Background technique

The analog-to-digital converter (ADC) is a bridge from analog signals to digital signals in the real world. Some biomedical signals such as electrocardiogram, electroencephalogram, and electromyography need to pass a medium resolution (8-14bits) and sampling rate (1 -1000kHz) ADC to digitize. Successive approximation analog-to-digital converters (SAR ADCs) are well suited for biomedical applications because of their good compromise between energy efficiency, conversion accuracy, and design complexity.

Generally speaking, for SAR ADCs with a resolution of 10 bits or less, a dynamic regenerable latch is usually used as a comparator. However, such comparators are not suitable for higher resolution SAR ADCs such as 12-bit or above due to the large noise of the dynamically regenerable latch. Usually, in order to improve the accuracy of the comparator, one or more stages of amplifiers are cascaded before the dynamic regenerative latch. This is done at the cost of greatly increasing the power consumption of the comparator.

The accuracy of SAR ADCs currently reported for measuring biomedical signals is generally 10 bits or less, and the power consumption is at the nanowatt level. For higher-precision measurement requirements, due to the limitation of comparator power consumption, it is often very difficult to achieve nanowatt-level ultra-low power consumption SAR ADC.

Contents of the invention

In view of the above problems, the present invention proposes a low-voltage ultra-low power consumption high-precision comparator for SAR ADC.

Its specific technical scheme is:

Low-voltage ultra-low-power high-precision comparator for this SAR ADC, including preamplifier, regenerative latch, detector, comparator clock generator, and transmission gate switch;

The comparator clock generator is used to generate the preamplifier control signal and the regenerable latch clock, the detector is used to set the size of the voltage range and detect the range of the comparator input voltage difference, and the transmission gate switch is used to select the transmission path of the signal.

The input end of the preamplifier is connected to the input end of the regenerative latch through a pair of transmission gate switches, and its output end is connected to the input end of the regenerative latch through another pair of transmission gate switches; the regenerative latch The output terminal of the detector is connected with the input terminal of the detector, the output terminal of the detector is respectively connected with the input terminal of the comparator clock generator and the control terminal of the transmission gate switch, and the output terminal of the comparator clock generator is respectively connected with the control terminal of the preamplifier terminal and the clock terminal of the regenerable latch.

The detector includes a delay unit with adjustable delay, an OR gate and 2 D flip-flops (DFF), and the 2 D flip-flops are DFF1 and DFF2; The clock input of the latch is connected, and its output is connected to the clock input of DFF2, and the input of the OR gate is connected to the output of the regenerable latch, and its output is connected to the clock input of DFF1 , the output terminal of DFF1 is connected with the data input terminal of DFF2.

The comparator clock generator includes a delay unit with fixed delay, an NOR gate, an AND gate, three D flip-flops DFF and 3 inverters, and the 3 D flip-flops are DFF3, DFF4 and DFF5; the output of the above-mentioned detector is respectively connected to the input of the delay fixed delay unit, the clock input of DFF5 and the input of another inverter after inversion, and the output of the delay fixed delay unit is connected to DFF4 The clock input terminals are connected, the inverting output terminal of DFF4 is connected with the data input terminal of DFF4, the inverting output terminal of DFF5 is connected with the data input terminal of DFF5, and the non-inverting output terminals of DFF4 and DFF5 are connected with the input terminal of the NOR gate. The output terminal of the NOR gate and the output terminal of DFF3 are connected with the input terminal of the AND gate, and the reset terminal of DFF3 is connected with the output terminal of the inverter.

A coarse comparator with low precision is composed of a single regenerative latch, and a fine comparator with high precision is composed of preamplifier cascaded regenerative latches. The output terminals of the comparator are connected, and the output terminal is connected with the input terminal of the precision comparator through another pair of transmission gate switches. Given a voltage range, when the input voltage of the comparator falls outside the voltage range, the fine comparator does not work; when the input voltage of the comparator falls within the voltage range, the fine comparator works.

For a fully differential charge redistribution SAR ADC, during the conversion process, the voltage at the output of the DAC, that is, the input voltage of the comparator, approaches the common-mode voltage successively. Referring to Figure 1, in the successive approximation process, not every bit conversion requires a high-precision comparator for comparison. When the DAC output voltage falls outside a certain voltage range, a coarse comparator with low precision is used for comparison; when the DAC output voltage falls within the voltage range, a fine comparator with high precision is used for comparison. Since the fine comparator has much larger power consumption than the coarse comparator, the power consumption of the comparator can be reduced by reducing the working times of the fine comparator during the conversion process by setting the size of the voltage range.

In summary, the beneficial effects of the present invention are as follows: by detecting the size of the comparator input voltage to select a comparator with different precision to work, and by setting the size of the voltage range to reduce the number of operations of the fine comparator, thus without affecting the accuracy case to reduce comparator power consumption.

Description of drawings

Figure 1 shows the conversion process of a traditional SAR ADC;

Fig. 2 is a schematic diagram of the principle of the low-voltage ultra-low power consumption high-precision comparator applied to the SAR ADC of the present invention;

Fig. 3 is the schematic diagram of the structure of the comparison circuit for the first time at the beginning of each bit conversion;

Figure 4 is a schematic diagram of the circuit structure during the secondary comparison;

Figure 5 is a schematic diagram of the principle of a preamplifier and a regenerative latch with offset correction;

Fig. 6 is a relation diagram of the comparison time and the input voltage difference of the regenerable latch;

Fig. 7 is the schematic diagram of detector principle;

Fig. 8 is a schematic diagram of the principle of the comparator clock generator;

FIG. 9 is a schematic diagram of the working sequence of the comparator;

Fig. 10 is the schematic diagram of the embodiment circuit;

Fig. 11 is a spectrum diagram of the output result of the embodiment.

Reference numerals: clk-1 regenerable latch clock, PWD preamplifier clock.

detailed description

Below according to accompanying drawing and embodiment, the present invention is described in further detail:

Referring to Figure 2, a low-voltage, ultra-low-power, and high-precision comparator for SAR ADCs includes a preamplifier, a regenerative latch, a detector, a comparator clock generator, and a transmission gate switch; the preamplifier input Connected to the input of the regenerative latch through a pair of transmission gate switches, and its output is connected to the input of the regenerative latch through another pair of transmission gate switches; the output of the regenerative latch is connected to the input of the detector The output terminals of the detector are respectively connected with the input terminal of the comparator clock generator and the control terminal of the transmission gate switch, and the output terminals of the comparator clock generator are respectively connected with the control terminal of the preamplifier and the regenerative latch connected to the clock terminal.

The present invention can be regarded as being composed of two comparators: a coarse comparator with low precision composed of a single regenerable latch; a fine comparator with high precision composed of preamplifier cascaded regenerable latches . Referring to Figure 3, at the beginning of each bit conversion, the switches S ₁ and S ₂ are turned on, S ₃ and S ₄ are turned off, the preamplifier is turned off, and the output signal of the DAC is transmitted to the input terminal of the coarse comparator for comparison. Then the detector judges the input voltage difference range of the coarse comparator. If the input voltage difference is large, the result of this comparison is the final result of the bit conversion; refer to Figure 4, if the input voltage difference is small, the switches S ₁ , S ₂ is disconnected, S ₃ and S ₄ are turned on, the preamplifier is turned on, the output signal of the DAC is transmitted to the input terminal of the fine comparator for a second comparison, and the result of the second comparison is the final result of the bit conversion. Referring to FIG. 5 , the offset of the comparator will affect the performance of the system, and the comparators used in the present invention all have offset correction.

Referring to Figure 6, the comparison time of the regenerative latch is inversely proportional to the input voltage difference. When the input voltage difference is large, the comparison time is short, and when the input voltage difference is small, the comparison time is long. The range of input voltage difference can be judged by the detector. Referring to FIG. 7 , the detector includes a delay unit with adjustable delay, an OR gate and 2 DFFs, and the 2 DFFs are DFF1 and DFF2. In the reset phase, DFF1 is reset, DFF2 is set and the clock clk_l is set low, at this time the output nodes cp and cn of the regenerative latch are precharged to the supply voltage. The input voltage of the OR gate is low, and the output eol is also low. After clk_l changes from low to high, the comparison process begins, and the voltages of nodes cp and cn drop at different rates. When the comparison is complete, the voltage at one end is high and the voltage at the other end is low. The output eol of the OR gate changes from low to high, DFF1 is triggered, and the output also changes from low to high. The interval between the rising edge of clk_l and the rising edge of the DFF1 output signal is the comparison time T _comp of the regenerative latch. The function of the adjustable delay unit is to set the size of the voltage range by performing a fixed delay (T _d ) on the clock clk_l. If the output out of DFF2 is high level, it means that the input signal falls outside the voltage range; if the output out of DFF2 is low level, it means that the input signal falls within the voltage range, and a second comparison is required.

Refer to Figure 8, which is a schematic diagram of the principle of the comparator clock generator, including a delay unit with fixed delay, an NOR gate, an AND gate, three DFFs and three inverters, and the three DFFs are DFF3, DFF4 and DFF5 . Refer to Figure 9 for its working sequence diagram. At the beginning of each bit comparison, clk_l is a high level, and the regenerable latch starts to work. When the input voltage difference is large, the detector output out is high level, and node A remains high level. At the same time, the regenerative latch comparison completion signal eol is high, DFF3 is reset, clk_l becomes low level, the comparison ends, and the next bit comparison starts. During this process, the PWD signal is always at a high level, and the preamplifier is turned off. When the input voltage difference is small, the detector output out is low, which produces a negative pulse at node A. Since the regenerative latch has not completed the comparison, the eol signal remains low and the output of DFF3 remains high. In this way, clk_l also generates a negative pulse to form a second comparison. During this process, the PWD signal changes from high to low, and the preamplifier turns from off state to working state.

Fig. 10 is a SAR ADC circuit applying the present invention, its resolution is 12 bits, the clock frequency is 10kHz, the power supply voltage VDD and the reference voltage VREF are both 0.6V. Combined with Figure 1 and Figure 9, phase1 and phase2 are used to illustrate the working process of the comparator in this circuit:

In phase1, switches S ₁ and S ₂ are turned on, S ₃ and S ₄ are turned off, and the preamplifier is turned off. The comparator clock generator generates a comparison signal, and the detector output is high because the input voltage of the comparator is outside the preset voltage range. Switches S _1-4 and the preamplifier remain in the same state. The comparison result at this time is the final result of the bit comparison.

In phase2, switches S ₁ and S ₂ are turned on, S ₃ and S ₄ are turned off, and the preamplifier is turned off. The comparator clock generator generates a comparison signal, and since the input voltage of the comparator is within the preset voltage range, the detector output is low. At this time, switches S ₁ and S ₂ are turned off, S ₃ and S ₄ are turned on, the preamplifier is turned on, the comparator clock generator generates a secondary comparison signal, and the fine comparator starts to work. The result of the second comparison is the final result of the bit comparison.

Referring to Figure 11, the comparator input signal voltage range is set to 3LSB (1LSB=VDD/2 ¹¹ ), the input signal frequency is 3.3594kHz, and the amplitude is 0.57V, and the conversion result of the SAR ADC is converted by Fast Fourier Transform (FFT) to obtain the output The frequency spectrum of the digital signal is calculated to obtain a spurious-free dynamic range (SFDR) of 83.9dB, a signal-to-noise-distortion ratio (SNDR) of 73.2dB, and an effective number of bits (ENOB) of about 11.86bits. Wherein the power consumption of the comparator is 96nW; if the present invention is not adopted, that is, the fine comparator works once when each bit is compared, and the power consumption of the comparator is 409nW.

The invention selects comparators with different precision to work by detecting the input voltage of the comparator, reduces the working times of the precision comparator by setting the size of the voltage range, and reduces the power consumption of the comparator without affecting the precision of the comparator.

The embodiments of the present invention are disclosed as preferred implementation modes, but their specific implementation is not limited thereto. Those of ordinary skill in the art can easily understand the spirit of the present invention based on the above-mentioned embodiments, and make different extensions and changes, as long as Anything that does not depart from the spirit of the present invention falls within the protection scope of the present invention.

Claims (2)

1. A SAR ADC comparator, comprising preamplifier, regenerable latch, is characterized in that: also comprises detector, comparator clock generator and transmission gate switch; The comparator clock generator is used to generate the preamplifier control signal and the regenerable latch clock, the detector is used to set the size of the voltage range and detect the range of the comparator input voltage difference, and the transmission gate switch is used to select the transmission path of the signal; The input end of the preamplifier is connected to the input end of the regenerative latch through a pair of transmission gate switches, and its output end is connected to the input end of the regenerative latch through another pair of transmission gate switches; the regenerative latch The output terminal of the detector is connected with the input terminal of the detector, the output terminal of the detector is respectively connected with the input terminal of the comparator clock generator and the control terminal of the transmission gate switch, and the output terminal of the comparator clock generator is respectively connected with the control terminal of the preamplifier terminal and the clock terminal of the regenerable latch are connected; The detector includes a delay unit with adjustable delay, an OR gate and 2 D flip-flops (DFF), and the 2 D flip-flops are DFF1 and DFF2; The clock input of the latch is connected, and its output is connected to the clock input of DFF2, and the input of the OR gate is connected to the output of the regenerable latch, and its output is connected to the clock input of DFF1 , the output end of DFF1 is connected with the data input end of DFF2; The comparator clock generator includes a delay unit with fixed delay, an NOR gate, an AND gate, three D flip-flops DFF and 3 inverters, and the 3 D flip-flops are DFF3, DFF4 and DFF5; the output of the above-mentioned detector is respectively connected to the input of the delay fixed delay unit, the clock input of DFF5 and the input of another inverter after inversion, and the output of the delay fixed delay unit is connected to DFF4 The clock input terminals are connected, the inverting output terminal of DFF4 is connected with the data input terminal of DFF4, the inverting output terminal of DFF5 is connected with the data input terminal of DFF5, and the non-inverting output terminals of DFF4 and DFF5 are connected with the input terminal of the NOR gate. The output end of the NOR gate and the output end of DFF3 are connected with the input end of the AND gate, and the reset end of DFF3 is connected with the output end of the inverter; A coarse comparator with low precision is composed of a single regenerative latch, and a fine comparator with high precision is composed of preamplifier cascaded regenerative latches. The output terminal of the comparator is connected, and its output terminal is connected to the input terminal of the fine comparator through another pair of transmission gate switches; given a voltage range, when the input voltage of the comparator falls outside the voltage range, the fine comparator does not Work; when the input voltage of the comparator falls within the voltage range, the fine comparator works. 2. SAR ADC comparator as claimed in claim 1, is characterized in that: comparator input signal voltage range size is set to 3LSB, input signal frequency is 3.3594kHz and amplitude is 0.57V, SAR ADC resolution is 12, and clock frequency It is 10kHz, the power supply voltage VDD and the reference voltage VREF are both 0.6V.