CN113341232A - Measuring range self-adaptive high-precision capacitance detection method and detection circuit - Google Patents
Measuring range self-adaptive high-precision capacitance detection method and detection circuit Download PDFInfo
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Abstract
The invention discloses a measuring range self-adaptive high-precision capacitance detection method and a detection circuit, wherein the detection circuit comprises: the capacitance detection circuit is used for generating a voltage signal related to the capacitance value of the capacitor to be detected through the constant current characteristic of the reference current source in a certain voltage range; the control circuit is used for generating a clock signal, controlling the periodic charging and discharging of the capacitor to be detected through the frequency division result of the clock signal, converting a voltage signal output by the capacitor detection circuit into a level signal and providing a quantization starting signal and a quantization ending signal for the quantization circuit; the range detection circuit is used for detecting the signal and the frequency division result output by the control circuit, adjusting the frequency division ratio of the frequency divider, and increasing the range of the circuit to finish the measurement of the capacitor to be measured; and the quantization circuit is used for carrying out capacitance quantization based on the time domain and outputting a quantization result. The invention has the characteristics of full integration, high precision and high linearity, and simultaneously gives consideration to the measurement range and the measurement precision of the capacitance quantization circuit.
Description
Technical Field
The invention belongs to the technical field of sensing, and relates to a measuring range self-adaptive high-precision capacitance detection method and a detection circuit.
Background
In recent years, with the continuous development of the internet and the semiconductor industry, the world has gradually moved to the internet of things age with the interconnection of everything, and by 2018, the internet of things has been taken out of the industry and popularized to various fields such as household appliances, medical treatment, transportation and logistics. The flying-method-level capacitive sensor is one of the most critical supporting technologies, and is greatly driven by market demands. A capacitance sensor is a conversion device that converts a physical quantity to be measured into a change in capacitance. Due to its advantages of simple structure, high sensitivity, etc., it has been widely used in various fields, such as capacitive pressure sensors for pressure detection, capacitive fingerprint sensors for biometric identification, capacitive accelerometers for medical detection, etc.
The traditional capacitance detection methods mainly include frequency type, switch capacitance type, resistance discharge type and other detection methods. For the frequency type detection method, the detection precision can not reach the grade of a femtofarad. For the switched capacitor detection method, when the capacitance is quantized, the conversion from the capacitance to the voltage is firstly completed, and then the voltage-image-digital signal conversion is completed by using an ADC (analog-to-digital converter); however, the resolution of the capacitor to be measured is limited by problems such as the accuracy of the switched capacitor circuit and noise. The resistor discharge type circuit generally charges a capacitor, discharges through an accurate resistor outside a chip, and quantifies discharge time. Although the circuit can achieve higher precision, the capacitor discharges through the resistor to indicate a waveform, and the signal needs to be linearized when being quantized, so that the algorithm is more complex, the corresponding quantization rate and the integration level of the quantization circuit are lower, and the quantization mode has higher requirement on the precision of the time measurement circuit. The above-described circuit itself has drawbacks that limit the further development of high-precision capacitive sensors. In addition, the above circuits often have a relationship in which the range and the quantization accuracy are restricted from each other, and the measurement range is almost constant even at the same quantization accuracy. Once the capacitance to be measured exceeds the preset measuring range, the measuring circuits cannot complete the measurement or need to reduce the quantization precision to complete the measurement.
Disclosure of Invention
In order to solve the above problems, embodiments of the present invention provide a range-adaptive high-precision capacitance detection circuit, which has the characteristics of full integration, high precision and high linearity, and simultaneously considers both the measurement range and the measurement precision of a capacitance quantization circuit, thereby solving the problems in the prior art.
Another object of the embodiments of the present invention is to provide a range-adaptive high-precision capacitance detection method.
The technical scheme adopted by the invention is that the range self-adaptive high-precision capacitance detection circuit comprises a capacitance detection circuit, a control circuit, a range detection circuit and a quantization circuit;
the capacitance detection circuit is used for generating a voltage signal related to the capacitance value of the capacitor to be detected through the constant current characteristic of the reference current source in a certain voltage range, namely a signal S2;
the control circuit is used for generating a clock signal, namely a signal S5, controlling the periodic charging and discharging of the capacitor to be detected through the frequency division result S1 of the clock signal, and converting a voltage signal output by the capacitor detection circuit into a level signal, namely a signal S3; providing a start quantization and an end quantization signal to the quantization circuit according to signal S3;
the measuring range detection circuit is used for detecting a signal S3 and a frequency division result S1 output by the control circuit, the falling edge of the frequency division result S1 temporarily judges whether the signal S3 is at a high level, and if the signal S3 is at the high level, the current measuring range is used for quantifying the capacitor to be measured; if the signal S3 is at a low level, indicating that the capacitor to be measured exceeds a preset range, performing shift register on a current output signal S6 of the range detection circuit and outputting the signal, wherein the output signal S6 is sent to an IN1 end of the frequency divider, adjusting the frequency dividing ratio of the frequency divider, and increasing the range of the circuit to complete the measurement of the capacitor to be measured;
the quantization circuit is used for calculating the quantization value according to a formula
Determining the capacitance value of the capacitor to be measured, wherein C represents the capacitance value of the capacitor to be measured, I represents the discharge current generated by the reference current source, Δ V represents the discharge voltage of the capacitor to be measured, and Δ t represents the time spent by the capacitor to be discharged; and carrying out capacitance quantization based on the time domain and outputting a quantization result.
Furthermore, the capacitance detection circuit comprises a power supply VDD, an alternative selector, a PMOS tube and a reference current source;
the power supply VDD is used for charging the capacitor to be tested, the power supply VDD is connected to two ends of the capacitor to be tested, and one end of the capacitor to be tested, which is connected with the cathode of the power supply VDD, is grounded;
the PMOS tube is used for controlling the periodic charging and discharging of the capacitor to be measured according to the frequency division result S1; the PMOS tube is connected to a connecting loop of the capacitor to be tested and a power supply VDD, and a frequency division result S1 is input to the gate end of the PMOS tube to control the opening and closing of the PMOS tube;
the alternative selector is used for determining to connect the reference current source to the power supply VDD or to connect the reference current source to the capacitor to be tested according to the frequency division result S1; the frequency division result S1 is input to the input terminal of the one-of-two selector, and the output terminal of the one-of-two selector outputs the voltage signal S2.
Further, the frequency division result S1 is a periodic square wave, and the high and low levels of the frequency division result S1 are determined by the system clock signal S5 and the frequency division ratio.
Furthermore, the control circuit comprises a clock generation circuit, a comparator, a rising edge detector, a frequency divider and a reference voltage source;
the clock generating circuit is used for generating a system clock signal, namely a signal S5, and inputting a signal S5 to the control end of the rising edge detector and the input end of the frequency divider respectively;
the comparator is used for converting the signal S2 into a signal S3 and inputting the signal S3 into the rising edge detector; the inverting input end of the comparator is connected with the output end of the capacitance detection circuit, and the output end of the comparator is connected with the input end of the rising edge detector;
the rising edge detector is used for detecting the output of the comparator, and when the signal S3 output by the comparator jumps from low level to high level, the rising edge detector outputs a rectangular pulse, namely the signal S4, when the next rising edge of the signal S5 comes;
the reference voltage source is used for calibrating a discharge interval of the capacitor to be measured and is connected with the non-inverting input end of the comparator;
the frequency divider comprises a delay chain module formed by cascading delay units, wherein the middle delay units are all connected end to end except the first delay unit and the last delay unit, the output of each delay unit is connected with the input of the next delay unit, the output section of each delay unit is connected with a D trigger, a signal S3 is input to the input end of the first delay unit of the delay chain module, and a signal S4 is input to the clock end of each D trigger; when the rising edge of the signal S4 comes, the D flip-flop sends the level output by the corresponding delay unit to the Q terminal thereof, the Q terminal of the D flip-flop of the frequency divider is not connected back to the D terminal to form 1 divide-by-two divider, the input signal S5 is divided by 2, and the Q terminal outputs the division result, i.e., S1.
Further, during the charging period of the capacitor to be tested, when the signal S2 is the power supply VDD, the signal S3 is at a low level, during the discharging period of the capacitor to be tested, the signal S2 is continuously decreased along with the decrease of the capacitor voltage, and when the level of the signal S2 is slightly lower than VREF, the output signal S3 of the comparator is inverted from the low level to a high level, which marks the end of the discharging of the capacitor to be tested.
Further, the output signal S6 of the range detection circuit is a binary signal with a bit width of M, which is represented by a binary number of [ M-1,0] bits, where a bit is 1 and corresponds to a high level, and a bit is 0 and corresponds to a low level; the signal S6 has M bits in total and can control M switches, a switch is arranged on a cascade node of the delay unit behind the lowest bit S6[0] of the signal S6, each bit of the signal S6 is connected to a corresponding switch, when a certain bit of the signal S6 is 0, the corresponding switch is disconnected, and when the certain bit of the signal S6 is 1, the corresponding switch is closed; when the circuit is powered on, the preset frequency dividing ratio is determined by the number of D triggers before S6[0 ]; when the circuit is at the preset range, the value of the signal S6 is S6 ═ 00 … 1, that is, only the lowest bit S6[0] of the signal S6 is 1, and its corresponding switch is closed; all other bits are 0, and all corresponding switches are switched off; at this time, the D flip-flop corresponding to the switch controlled by S6[0] outputs a frequency division result S1; when the circuit adjusts the measuring range each time, the bit of the signal S6 which is 1 moves forward by one bit, 1 more D trigger participates in frequency division, the frequency dividing ratio is doubled, and the measuring range of the circuit is doubled.
Further, when the output signal S6 of the range detection circuit has moved to the last position and cannot complete the measurement, the output signal S7 of the range detection circuit is 1, which indicates that the capacitance to be measured has exceeded the maximum range of the circuit; otherwise, the output signal S7 of the range detection circuit is always 0.
Furthermore, the quantization circuit comprises a counter, a delay chain module and an arithmetic unit;
the first counter has 3 input signals, wherein the frequency division result S1 and the signal S3 are control signals of the counter, the signal S5 is an input signal of the counter, when the frequency division result S1 is at a low level, the counter stops counting, when the frequency division result S1 is at a high level and the signal S3 is at a low level, the counter starts counting, and at the moment, the corresponding circuit state is that the capacitor starts to discharge, but the capacitor does not discharge to a nominal voltage; when the signal S3 is high, indicating that the comparator has flipped, at this time, the counter stops counting and outputs a count result N of the clock period;
the output of each D trigger of the delay chain module is connected to the input of the arithmetic unit;
and the operation unit is used for calculating the time delta T elapsed by the discharging of the capacitor to be tested according to a formula delta T-NT, wherein T represents the clock period of the clock generation circuit, n represents the number of levels of 1 in all D flip-flops in the delay chain in the interval of the rising edge of the signal S3 and the rising edge of the signal S4, and T represents the delay of the delay unit.
Further, the precision of the comparator is 0.1 mV.
A detection method of a range self-adaptive high-precision capacitance detection circuit adopts the range self-adaptive high-precision capacitance detection circuit and specifically comprises the following steps:
step 1: when the circuit is powered on, the initial frequency dividing ratio is set, and the S6 value is S6 ═ 00 … 1;
step 2: when the capacitor is quantized for the first time after being electrified, the range detection circuit judges whether a frequency division result S1 falling edge coming time signal S3 is a low level, and if not, the current range is used for quantizing the capacitor to be measured; if yes, shifting and registering the S6 signal, judging whether the falling edge of the frequency division result S1 comes in the temporary signal S3 to be low level after each shifting and registering, and if not, quantizing by using the current measuring range; if yes, continuing to shift register the S6 signal; in the process of shift register by the S6 signal, it needs to be determined whether S6 reaches S6 ═ 1 … 00 ];
and step 3: if S6 is reached to [1 … 00], continuously judging whether the falling edge of the frequency division result S1 is low level or not when the signal S3 is low level, if not, quantizing by using the current measuring range; if yes, the maximum range is exceeded, and a mark signal S7 is given.
The invention has the beneficial effects that:
the high-precision quantization circuit with the self-adaptive measuring range adopts an on-chip integrated reference current source discharge mode, and only simple linear operation is needed when the variable quantity of the capacitor is quantized, so that the problem of complex algorithm of the traditional quantization circuit is solved, and the complexity of the quantization algorithm is reduced; meanwhile, other external elements are not needed, so that the integration level of the capacitance quantization circuit is improved, and the volume of the quantization circuit is greatly reduced.
The quantization range of the circuit is determined by the frequency dividing ratio of the frequency divider and the maximum count value of the counter, the quantization precision is determined by the precision of the delay unit of the delay chain, and the problem of compromise between the range and the precision does not exist in the maximum range, so that the problem of mutual restriction between the quantization range and the quantization precision is solved. The measuring range can be adjusted in a self-adaptive mode, the measuring range of the circuit is not increased at the cost of quantization precision in the adjusting process, and the circuit can still finish the measurement of the capacitor to be measured even if the measuring range exceeds the preset measuring range of the circuit. Meanwhile, when the capacitance quantization is carried out, the quantization can be completed quickly because the quantization algorithm is simple.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic block diagram of a quantization method according to an embodiment of the present invention.
Fig. 2 is a configuration of a capacitance detection circuit according to an embodiment of the present invention.
Fig. 3 is a configuration of a control circuit and a range detection circuit according to an embodiment of the present invention.
Fig. 4 shows the structure of the frequency divider according to the embodiment of the present invention.
FIG. 5 is a logic block diagram of a regulating circuit according to an embodiment of the present invention.
Fig. 6 is a block diagram of a quantization circuit according to an embodiment of the present invention.
FIG. 7 is a timing waveform diagram of each key signal in a single measurement process according to an embodiment of the present invention.
Fig. 8a-8d are simulation results of embodiments of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The basic principle of the circuit is as follows: according to the principle of charging and discharging the capacitor,
the method can obtain that under the condition of ensuring that the discharge current I of the capacitor is constant, the discharge voltage delta V of the capacitor is set as a fixed interval, the discharge time delta t of the capacitor and the capacitance value of the capacitor C are in a linear relation, so that the linearity of a quantization result is greatly improved, and the capacitance is reducedComplexity when quantizing, the circuit can be realized in the integrated circuit without external connection of other components, the size of the quantizing circuit is reduced, and the integration level of the quantizing circuit is improved. When the circuit quantizes the capacitor to be measured, the current measuring range is detected, and if the current measuring range cannot be quantized, the current measuring range is quantized by adjusting the measuring range of the circuit.
In the case of the example 1, the following examples are given,
a range-adaptive high-precision capacitance detection circuit is shown in figure 1 and comprises a capacitance detection circuit, a control circuit, a range detection circuit and a quantization circuit.
The capacitance detection circuit is used for detecting the voltage of a capacitor to be detected (Ctest), generating a voltage signal related to the capacitance value of the capacitor to be detected, namely a signal S2, through the constant current characteristic of the reference current source (Iref) within a certain voltage range, and transmitting the voltage signal to the control circuit.
And the control circuit is used for generating a clock signal, a charging and discharging control signal and a starting and ending signal of the quantization circuit. The clock generating circuit generates a clock signal, controls the periodic charging and discharging of the capacitor to be detected through the frequency division result S1 of the clock signal, and converts the voltage signal output by the capacitor detection circuit into a level signal, namely a signal S3; the quantization circuit is provided with start quantization and end quantization signals in accordance with signal S3.
The measuring range detection circuit is used for detecting a signal S3 and a frequency division result S1 output by the control circuit, judging whether the signal S3 is at a high level when a falling edge of the frequency division result S1 comes (namely when each frequency division period is finished), if so, indicating that the current measuring range can finish the measurement of the capacitor to be measured, and quantizing the capacitor to be measured by using the current measuring range; if the signal S3 is at a low level, it indicates that the capacitor to be measured exceeds the preset range, that is, the reference current source cannot discharge the capacitor to be measured to the calibration voltage, the current output signal S6 of the range detection circuit is output after shift registration, the output signal S6 is sent to the IN1 end of the frequency divider, the frequency dividing ratio of the frequency divider is adjusted, the discharge time of the capacitor IN a single measurement process is increased, so that the reference current source can discharge the capacitor to be measured to the calibration voltage, and the range of the circuit is increased to complete the measurement of the capacitor to be measured. The frequency divider generates a frequency division result S1 according to the signal S5, and the frequency divider can adjust the frequency division ratio according to the output signal (S6) of the range detection circuit.
A quantization circuit for quantizing the digital video signal according to a formula
Determining the capacitance value of the capacitor to be measured, wherein C represents the capacitance value of the capacitor to be measured, I represents the discharge current generated by the reference current source, Δ V represents the discharge voltage of the capacitor to be measured, and Δ t represents the time spent by the capacitor to be discharged; and finally, outputting a quantization result. The time spent by the capacitor discharge is determined by measuring the time interval of the two control signals, binary data is output, the conversion to the digital signals is completed, and DOUT is the final quantization result; the adopted capacitance quantization mode is carried out based on a time domain, and the measuring range detection circuit is closely matched with the specific capacitance quantization mode, so that the function of automatically adjusting the measuring range is realized.
Referring to fig. 2, the capacitance detection circuit includes a power supply VDD, an alternative selector (MUX2), a PMOS transistor, and a reference current source (Iref) that generates a reference current of 1uA (microampere).
The power supply VDD is used for charging the capacitor to be detected, the power supply VDD is connected to two ends of the capacitor to be detected, and one end of the capacitor to be detected, which is connected with the cathode of the power supply VDD, is grounded;
the PMOS tube is used for controlling the periodic charging and discharging of the capacitor to be measured according to the frequency division result S1; the PMOS tube is connected to a connecting loop of the capacitor to be tested and a power supply VDD, and a frequency division result S1 is input to the gate end of the PMOS tube to control the opening and closing of the PMOS tube;
the alternative selector is used for determining to connect the reference current source to the power supply VDD or to connect the reference current source to the capacitor to be detected according to the frequency division result S1; the frequency division result S1 is input to the input terminal of the one-of-two selector, and the output terminal of the one-of-two selector outputs the voltage signal S2. The A path of the MUX2 is used for connecting the reference current source to the capacitor to be tested, the B path of the MUX2 is used for connecting the reference current source to the power supply VDD, and the frequency division result S1 is connected with the control end (S) of the MUX 2.
The frequency division result S1 is a periodic square wave, which is divided by the system clock signal S5, and the high and low levels of the square wave are determined by the system clock signal S5 and the frequency division ratio, see fig. 7. When the frequency division result S1 is low level, the PMOS transistor is turned on, and the MUX2 selects the VDD terminal, and the power supply VDD is directly used to complete charging, so the signal S2 is always the voltage of the power supply VDD; when the frequency division result S1 is at a high level, the PMOS transistor is turned off, the MUX2 selects the end of the capacitor to be tested, the signal S2 is the output voltage of the capacitor to be tested, and the constant current source discharges the capacitor to be tested, so as to ensure that the discharge current of the capacitor is constant, and the voltage on the capacitor to be tested is reduced, that is, the slope of the signal S2 is fixed, and the slopes of the voltage signals are different for different capacitor values. When the capacitor is charged, the reference current source (Iref) is connected to the power supply voltage, although certain static power consumption can be increased, the voltage at two ends of the current source can not jump during the process of completing the conversion from charging to discharging of the capacitor to be detected, the working state of the MOS tube in the current source can not change, the constant of discharging current is ensured, the constant current characteristic of the reference current source is prevented from being changed due to the conversion of the working state of the MOS tube, and the nonlinearity of a quantization result is introduced.
Referring to fig. 3, the control circuit includes a clock generation circuit, a comparator, a rising edge detector (CLK), a frequency divider, and a reference voltage source (VREF).
And a clock generation circuit for generating a system clock signal (signal S5) and inputting the signal S5 to the control terminal of the rising edge detector and the input terminal of the frequency divider, respectively.
A comparator for converting the signal S2 into a signal S3 and inputting the signal S3 to the rising edge detector; the inverting input end of the comparator is connected with the output end of the capacitance detection circuit, and the output end of the comparator is connected with the input end of the rising edge detector; during the charging period of the capacitor to be tested, when the signal S2 is the power supply VDD, the signal S3 is at a low level, during the discharging period of the capacitor to be tested, the signal S2 is continuously decreased along with the decrease of the capacitor voltage, and when the level of the signal S2 is slightly lower than VREF, the output signal S3 of the comparator is inverted from the low level to a high level, which marks the end of the discharging of the capacitor to be tested. In some embodiments, the precision of the comparator is 0.1mV, the discharge interval of the capacitor is ensured to be 1V, and the higher the precision of the comparator is, the better the precision is.
And a rising edge detector for detecting the output of the comparator, wherein when the signal S3 output by the comparator changes from low level to high level, the rising edge detector outputs a rectangular pulse, namely the signal S4, when the next rising edge of the signal S5 arrives.
And the reference voltage source is used for calibrating the discharge interval of the capacitor to be measured and is connected with the non-inverting input end of the comparator.
The frequency divider comprises a delay chain module formed by cascading delay units, wherein the middle delay units are all connected end to end except the first delay unit and the last delay unit, the output of each delay unit is connected with the input of the next delay unit, the output section of each delay unit is connected with a D trigger, a signal S3 is input to the input end of the first delay unit of the delay chain module, and a signal S4 is input to the clock end of each D trigger; when the rising edge of the signal S4 comes, the D trigger sends the level output by the corresponding delay unit to the Q end of the D trigger, and the Q end of the D trigger of the frequency divider is not connected back to the D end to form 1 frequency divider, so that the function of frequency division by two is completed; dividing the input signal S5 by 2, and outputting a frequency division result at a Q end, namely S1; refer to fig. 4. The cascade of m units can realize 2mThe frequency division function, the output of each D trigger of the delay chain module is connected to the input of the arithmetic unit.
The output signal S6 of the range detection circuit is a binary signal with a bit width of M, which is represented by a binary number of [ M-1,0], where a bit is 1 and corresponds to a high level, and a bit is 0 and corresponds to a low level; the signal S6 has M bits in total and can control M switches. Referring to fig. 4, a switch is disposed on the cascade node of the delay unit after the lowest bit S6[0] of the signal S6, each bit (0-M-1) of the signal S6 is connected to the corresponding switch, when a certain bit of the signal S6 is 0, the corresponding switch is open, and when the certain bit is 1, the corresponding switch is closed; when the circuit is powered on, the preset frequency dividing ratio is determined by the number of D triggers before S6[0 ]; when the circuit is at the preset range, the value of the signal S6 is S6 ═ 00 … 1, that is, only the lowest bit S6[0] of the signal S6 is 1, and its corresponding switch is closed; the other bits (such as S6[1], S6[2] … S6[ M-1]) are all 0, and the corresponding switches are all off; at this time, the D flip-flop corresponding to the switch controlled by S6[0] outputs a frequency division result S1; each time the circuit adjusts the range, the bit of the signal S6 with the value of 1 is moved forward by one bit, and it is assumed that the circuit only adjusts the range once, that is, the value of S6 is S6 ═ 00 … 10], at this time, the D flip-flop output signal S1 corresponding to the switch controlled by S6[1], as can be known from fig. 4, 1 more D flip-flops participate in frequency division, so the frequency division ratio is doubled, and the range of the circuit is doubled. Each time the output of the S6 is shifted, one more D trigger participates in frequency division, the frequency division ratio is doubled, the longer the duration time of the high level of the signal S1 after frequency division is, the longer the discharge time of the reference current source is, the larger capacitor can be discharged to the calibration voltage by the reference power supply, the larger the capacitor which can be measured by the circuit is, and the function of automatically adjusting the circuit range is completed by the frequency division module and the range detection circuit together.
In the above process, the signal S7 is always 0, and if the value of S6 is S6 ═ 10 … 00, that is, the last bit has been shifted to, and the measurement cannot be completed, the output signal S7 is 1, which indicates that the capacitance to be measured has exceeded the maximum range of the circuit; if the capacitor to be measured exceeds the preset range, the reference current source cannot discharge the capacitor to the calibration voltage when the falling edge of the frequency division signal comes, and the output of the comparator cannot be turned from low to high.
Referring to fig. 6, the quantization circuit includes a Counter (Counter), a Delay chain module (Delay line), and an arithmetic unit (ALU).
The first counter has 3 input signals, wherein the frequency division result S1 and the signal S3 are control signals of the counter, the signal S5 is an input signal of the counter, when the frequency division result S1 is at a low level, the counter stops counting, when the frequency division result S1 is at a high level and the signal S3 is at a low level, the counter starts counting, and at the moment, the corresponding circuit state is that the capacitor starts to discharge, but the capacitor does not discharge to a nominal voltage; when the signal S3 is high, indicating that the comparator has flipped, the counter stops counting and outputs a count result N of the clock period, and the count result is multiplied by the period of the clock signal S5, so that the coarse time that the entire capacitor has elapsed from the beginning to the end of discharging can be obtained, and the coarse quantization is completed. Since the period of the clock generation circuit is fixed, each period of the signal S5 is also fixed. However, the rising edge of the output of the comparator is not substantially aligned with the edge of S5 at all times, and therefore, using only the counter output as the quantization result brings about a great error.
The output of each D trigger of the delay chain module is connected to the input of the arithmetic unit, and the arithmetic unit reads the counting result of the counter and the result of the delay unit and then carries out operation;
and the operation unit is used for calculating the time delta T elapsed by the discharging of the capacitor to be tested according to a formula delta T-NT, wherein T represents the clock period of the clock generation circuit, n represents the number of the levels of all the D flip-flops in the delay chain to be 1 in the interval of the rising edges of the signal S3 and the signal S4, and T represents the delay of the delay unit.
Referring to fig. 7, S1 is the result of the frequency division at S5, when S1 is low, the capacitor is charged to VDD, and at time t1, S1 becomes high, the capacitor starts to discharge, and the counter starts to count. At the time t2, the capacitor discharges to 0.8V, the output result of the comparator (S3) is inverted, and at this time, the counter is controlled to stop counting, as can be seen from FIG. 7, the quantization result of the counter is the time period from t1 to t3, but the actual discharge time of the capacitor to be measured is the time period from t1 to t2, so the time period from t2 to t3 is the quantization error introduced by coarse quantization.
Upon the rising edge of S3, the signal S3 propagates inside the delay chain, and the output of one delay cell is high every time interval of one delay cell. During the time interval between the rising edges of the signal S3 and the signal S4, only a limited number of delay cells will have their outputs changed to high, and the outputs of the other delay cells will remain at 0. After the rising edge of the signal S4, the output of the D flip-flop is read out by the arithmetic unit ALU. The time interval between the rising edges of the signals S3 and S4 can be known by counting the number of "1" levels in all D flip-flops.
As can be seen from FIG. 7, the result of subtracting the time period t2-t3 from the quantization result (time period t1-t 3) of the counter is the actual discharge time of the capacitor. At time t2, the rising edge of the S3 signal comes, which begins to travel in the delay chain. At time t3, the rising edge detector in the control module outputs a rectangular pulse, that is, the waveform of the signal S4, the rising edge of the signal is used as the control signal of the D flip-flop of the delay chain, the number of "1" in the multi-bit output of the read delay chain is n at time t3, t represents the delay of the delay unit, and the time period t2-t3 is:
t3-t2＝nt
assume that the capacitor is charged to 1.8V during charging, the comparator non-inverting input voltage is 0.8V, and the discharge current generated by the reference current source is 1 uA. Then the quantization result is:
where F represents the unit farad of capacitance.
The delay chain module is internally composed of a delay unit and a D trigger, and is used for measuring the rising edge time interval of S3 and S4 signals, and DOUT is a final capacitance quantization result. The quantization circuit adopts a mode of combining fine quantization and coarse quantization, the coarse quantization is completed by a counter, the fine quantization is completed by a delay chain module, and both the quantization range and the quantization precision can be considered; the operation unit completes binary conversion according to the results of the coarse quantization and the fine quantization, and finally completes the function of converting the capacitance value of the capacitor to be measured into the binary number. The shorter the delay of the delay unit, the higher the accuracy that can be achieved by the present application, and the quantization range is determined by the time when S1 is high, and the longer the duration of high level, the longer the discharge time of the constant current source, the larger the quantization range of the circuit. It follows that the accuracy of the circuit is determined by the delay of the delay means, the quantization range of the circuit is determined by the time when S1 is at the high level, and both parameters do not have a relationship of constraint with each other, so that both the quantization range and the quantization accuracy can be satisfied.
Referring to FIGS. 8a-8d, abscissa CtestIs the capacitance value of the capacitor to be measured, the ordinate CmearThe simulation result is corresponding to the quantization circuit. Fig. 8a is a simulation result of increasing the capacitance of the capacitor to be measured by 1fF when the bulk value of the capacitor to be measured is 310 fF. Fig. 8b shows the simulation result of increasing the capacitance of the capacitor to be measured by 1fF when the bulk value of the capacitor to be measured is 1005 fF.Fig. 8c is a simulation result of increasing the capacitance of the capacitor to be measured by 10fF each time the bulk value of the capacitor to be measured is 300 fF. Fig. 8d is a simulation result of increasing the capacitance of the capacitor to be measured by 100fF when the bulk value of the capacitor to be measured is 300 fF. From simulation results, even if the bulk values of the capacitors to be measured are different, the quantization circuit can still achieve the quantization precision of 1 fF. Meanwhile, as can be seen from the simulation results of fig. 8c and 8d, the circuit can still accurately complete the measurement even if the capacitance value of the capacitor to be measured changes greatly. The non-ideal factors are considered, the simulation result in the graph has extremely small quantitative deviation with the actual value of the capacitor to be measured, the deviation does not affect the quantitative linearity, and the translation calibration with the actual value can be realized through single-point calibration in the initialization process in the later product use. In conclusion, when the quantization circuit is used for capacitance measurement, the quantization precision of 1fF can be achieved, and meanwhile, the quantization result has better linearity in a large range.
The maximum range depends on the number of frequency dividers additionally added after the frequency dividing circuit ensures initial frequency division, the maximum range is doubled by one more frequency divider, and the maximum range is 12 pF; while ensuring that the quantization accuracy is in the range of 0-1.5 pF. The range of the existing detection circuit is 0-1.5pF, and the quantization precision is 1 fF.
In the case of the example 2, the following examples are given,
a measuring range self-adaptive high-precision capacitance detection method is disclosed, as shown in FIG. 5, the detection circuit is adopted, and the method specifically comprises the following steps:
step 1: when the circuit is powered on, the initial frequency dividing ratio is set, and the S6 value is S6 ═ 00 … 1;
step 2: when the capacitor is quantized for the first time after being electrified, the range detection circuit judges whether a frequency division result S1 falling edge coming time signal S3 is a low level, and if not, the current range is used for quantizing the capacitor to be measured; if yes, shifting and registering the S6 signal, judging whether the falling edge of the frequency division result S1 comes in the temporary signal S3 to be low level after each shifting and registering, and if not, quantizing by using the current measuring range; if yes, continuing to shift register the S6 signal; in the process of shift register by the S6 signal, it needs to be determined whether S6 reaches S6 ═ 1 … 00 ];
and step 3: if S6 is reached to [1 … 00], continuously judging whether the falling edge of the frequency division result S1 is low level or not when the signal S3 is low level, if not, quantizing by using the current measuring range; if yes, the maximum range is exceeded, and a mark signal S7 is given.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (10)
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