CN111785689A - CMOS device and method of forming the same - Google Patents

Abstract

The invention provides a CMOS device and a forming method thereof, comprising the following steps: providing a substrate, and forming a first well region and a second well region on the substrate; forming a gate oxide layer on the first well region and the second well region; sequentially forming a polycrystalline silicon layer, a protective layer and a hard mask layer on the gate oxide layer of the first well region and the gate oxide layer of the second well region; etching the hard mask layer, the protective layer and the polycrystalline silicon layer to form polycrystalline silicon grid electrodes respectively positioned above the first well region and the second well region; forming a side wall at least covering the side wall of the polysilicon gate; and performing drain light doping by taking the hard mask layer as a mask. The hard mask layer and the protection layer are arranged at the top of the polysilicon gate in the process of drain light doping (LDD), and the side wall of the polysilicon gate is protected by a side wall, so that the polysilicon gate is prevented from penetrating in the LDD process, and the consistency of threshold voltage/leakage current (Vt/ID) of the CMOS device is improved.

Description

CMOS device and method of forming the same

technical field

The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a CMOS device and a method for forming the same.

Background technique

As the semiconductor industry has become the mainstream of emerging industries, integrated circuits have developed into ultra-large integrated circuits that can accommodate tens of millions of transistors in a single die, and CMOS (Complementary Metal Oxide Semiconductor) devices are due to their capabilities. Low power consumption, high integration, low noise, strong radiation resistance and other advantages have become the main process in VLSI, but the power supply voltage of traditional CMOS devices is relatively single, for example, the power supply voltage of most CMOS devices is 5V, which cannot meet the Diversified power supply needs. Therefore, CMOS products with different operating voltages are provided in the related art.

With the continuous development of integrated circuit technology, the feature size of CMOS devices continues to shrink, and at the same time, the thickness of the polysilicon gate layer becomes thinner and thinner. The main purpose of a thinner polysilicon gate layer is to allow a larger lithography or etch process window. For dual-gate processes with power supply voltages of 5V and 1.2V/1.5V, in order to increase the 5V drain penetration voltage, it is usually necessary to increase the lightly doped drain (LDD) diffusion ion implantation dose. However, as the polysilicon gate layer becomes thinner, it is easy to penetrate the polysilicon gate layer during the LDD process, so the threshold voltage/leakage current (Vt/ID) consistency of the CMOS device is poor.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for forming a CMOS device, which can effectively protect the polysilicon gate layer to avoid penetration during the LDD process, and improve the threshold voltage/leakage current (Vt/ID) consistency of the CMOS device.

The present invention provides a method for forming a CMOS device, comprising:

providing a substrate on which a first well region and a second well region are formed;

forming a gate oxide layer on the first well region and the second well region, the thickness of the gate oxide layer located in the first well region is smaller than the thickness of the gate oxide layer located in the second well region;

forming a polysilicon layer, a protective layer and a hard mask layer in sequence on the gate oxide layer of the first well region and the gate oxide layer of the second well region;

Etching the hard mask layer, the protective layer and the polysilicon layer to form polysilicon gate levels respectively located above the first well region and the second well region;

forming spacers covering at least the sidewalls of the polysilicon gates; and

Drain light doping is performed using the hard mask layer as a mask.

Further, the spacers are formed by depositing a thin high temperature oxide film.

Further, after performing light source-drain doping using the hard mask layer as a mask, the method further includes:

The hard mask layer is removed.

Further, after forming the polysilicon gate level, and before forming the sidewall spacers covering at least the sidewalls of the polysilicon gate level, the method further includes: performing rapid thermal oxidation annealing.

Further, the rapid thermal oxidation annealing process includes: in a dry O ₂ environment, the annealing temperature range is 1000° C.˜1200° C., and the annealing time is 30s˜60s.

Further, a first voltage transistor is formed on the first well region, a second voltage transistor is formed on the second well region, and the first voltage is lower than the second voltage.

Further, the first voltage includes: 1.2V or 1.5V; the second voltage includes: 5V or 12V.

The present invention also provides a CMOS device, comprising:

A substrate, on which a first well region and a second well region are formed; a gate oxide layer is formed on both the first well region and the second well region, and the gate of the first well region is located The thickness of the oxide layer is smaller than the thickness of the gate oxide layer located in the second well region;

The gate oxide layer of the first well region and the gate oxide layer of the second well region are stacked in order to form a polysilicon gate, a protective layer and a hard mask layer;

sidewalls of the polysilicon gate are formed with sidewalls;

Both the first well region and the second well region are formed with lightly doped drain regions.

Further, the sidewall spacers also cover the sidewalls of the protective layer, and the bottoms of the sidewall spacers cover the exposed portions of both ends of the gate oxide layer by the polysilicon gate.

Further, the hard mask layer includes a silicon nitride layer, and the protective layer includes a silicon oxide layer.

Compared with the prior art, the present invention has the following beneficial effects:

The invention provides a CMOS device and a method for forming the same, including: providing a substrate, forming a first well region and a second well region on the substrate; forming a gate oxide layer on the first well region and the second well region; A polysilicon layer, a protective layer and a hard mask layer are sequentially formed on the gate oxide layer of a well region and the gate oxide layer of the second well region; the hard mask layer, the protective layer and the polysilicon layer are etched forming a polysilicon gate level above the first well region and the second well region respectively; forming sidewall spacers covering at least the sidewalls of the polysilicon gate level; using the hard mask layer as a mask to perform drain Lightly doped. During the light drain doping (LDD) process, the top of the polysilicon gate level is protected by the hard mask layer and the protective layer, and the sidewalls of the polysilicon gate level are protected by spacers, so that the polysilicon gate level is protected by spacers. The level avoids penetration during LDD and improves the threshold voltage/leakage current (Vt/ID) consistency of CMOS devices.

Description of drawings

FIG. 1 is a schematic flowchart of a method for forming a CMOS device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a CMOS device according to an embodiment of the present invention after a first well region and a second well region are formed.

FIG. 3 is a schematic diagram of a CMOS device according to an embodiment of the present invention after a gate oxide layer is formed.

FIG. 4 is a schematic diagram of a CMOS device after forming sidewall spacers according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a CMOS device according to an embodiment of the present invention after lightly doped source and drain regions and drains are formed.

Among them, the reference numerals are as follows:

10-substrate; 20-shallow trench isolation; 31-first well region; 32-second well region; 40-gate oxide layer; 50-polysilicon gate; 51-protective layer; 52-hard mask layer; 53-spacers; 61, 63-source regions; 62, 64-drain regions; 71/73-lightly doped source regions; 72/74-lightly doped drain regions.

Detailed ways

Based on the above research, embodiments of the present invention provide a CMOS device and a method for forming the same. The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

An embodiment of the present invention provides a method for forming a CMOS device, as shown in FIG. 1 , including:

providing a substrate on which a first well region and a second well region are formed;

forming a gate oxide layer on the first well region and the second well region, the thickness of the gate oxide layer located in the first well region is smaller than the thickness of the gate oxide layer located in the second well region;

forming a polysilicon layer, a protective layer and a hard mask layer in sequence on the gate oxide layer of the first well region and the gate oxide layer of the second well region;

Etching the hard mask layer, the protective layer and the polysilicon layer to form polysilicon gate levels respectively located above the first well region and the second well region;

forming spacers covering at least the sidewalls of the polysilicon gates; and

Drain light doping is performed using the hard mask layer as a mask.

The steps of the method for forming a CMOS device according to an embodiment of the present invention are described below with reference to FIGS. 2 to 4 .

As shown in FIG. 2 , a substrate 10 is provided on which a first well region 31 and a second well region 32 are formed. Specifically, the active region of the low-voltage device and the active region of the high-voltage device are defined on the substrate 10 by the shallow trench isolation (STI) 20; the active region of the low-voltage device and the active region of the high-voltage device are respectively ion implanted to form a first Well region 31 and second well region 32 .

As shown in FIG. 3, a gate oxide layer 40 is formed on the first well region 31 and the second well region 32, and the thickness of the gate oxide layer 40a in the first well region 31 is smaller than that in the second well region gate oxide 40b thickness of region 32. A low-voltage transistor, such as a transistor with a power supply voltage of 1.2V/1.5V, is formed on the first well region 31 . A high-voltage transistor, such as a transistor with a power supply voltage of 5V/12V, is formed on the second well region 32 . The gate oxide layer 40 may be grown by a thermal oxidation growth process. The temperature for growing the gate oxide layer is, for example, 900°C to 1150°C.

Specifically, after the gate oxide layer is grown on the surfaces of the first well region 31 and the second well region 32, the gate oxide layer with a predetermined thickness on the surface of the first well region 31 is etched away, so that the gate oxide layer located in the first well region 31 is etched away. The thickness of the gate oxide layer 40 a is smaller than the thickness of the gate oxide layer 40 b located in the second well region 32 . The gate oxide layer with a predetermined thickness on the surface of the first well region 31 can be etched by wet etching (good etching effect), dry etching (fast etching speed), or A method of combining dry etching and wet etching is adopted to improve the etching speed of the gate oxide layer on the premise of ensuring the etching effect. The thickness difference between the thickness of the gate oxide layer 40a located in the first well region 31 and the thickness of the gate oxide layer 40b located in the second well region 32 ranges from 150 angstroms to 1000 angstroms, for example. Therefore, when manufacturing a double-gate oxide CMOS high and low voltage device, only one gate oxide growth process is needed to meet the requirement of thickness difference between the two gate oxide layers in the double gate oxide CMOS high and low voltage device. The manufacturing process of the double-gate oxygen CMOS high and low voltage device is optimized, the manufacturing efficiency of the CMOS device is improved, and at the same time, the working time of the furnace tube is shortened, and the working capacity of the furnace tube is improved.

As shown in FIG. 4 and FIG. 5 , a polysilicon layer covering the gate oxide layer 40 is formed; a protective layer 51 covering the polysilicon layer is formed; the protective layer includes a silicon oxide layer. A hard mask layer 52 covering the protective layer 51 is formed; the hard mask layer includes a silicon nitride layer. A layer covering the hard mask layer 52 and silicon oxide may also be formed. The hard mask layer 52, the protective layer 51 and the polysilicon layer are sequentially etched to form a polysilicon gate level 50; a rapid thermal oxidation annealing (RTO) is performed on the CMOS device forming the polysilicon gate level 50 to eliminate the CMOS device stress of each layer. The rapid thermal oxidation annealing (RTO) process includes: in a dry O ₂ environment, the annealing temperature range is: 1000°C to 1200°C, and the annealing time is 30s to 60s.

A sidewall 53 covering at least the sidewall of the polysilicon gate level 50 is formed, further, the sidewall 53 also covers the sidewall of the protective layer 51, and the bottom of the sidewall 53 respectively covers the two ends of the gate oxide layer 40a and is covered by the polysilicon gate. The exposed part of the gate 50 also covers the part exposed by the polysilicon gate 50 at both ends of the gate oxide layer 40b. A thin high temperature oxide film (HTO) is deposited and etched to form the spacers 53 .

Lightly drain doping (LDD) is performed using the hard mask layer 52 as a mask. Specifically, the drain light doping is performed on the drain region near the drain region 62 in the first well region 31 and the drain region 64 in the second well region 32 to form lightly doped drain regions 72 and 74 respectively, and at the same time lightly doped drain regions 72 and 74 are formed. Doping source regions 71/73. By performing light-drain doping (LDD), the short channel effect and hot carrier effect are suppressed, the concentration gradient between the channel, the drain and the source junction is reduced, and the source-drain is reduced to a certain extent. the electric field strength. By performing lightly doped drain (LDD), the lightly doped drain regions 72 and 74 are lightly doped in the overlapping region with the polysilicon gate 50, the penetration voltage of the LDD junction can be increased, and the device performance can be improved. The channel penetration characteristics can also reduce the hot carrier effect and improve the reliability of the device.

Through SD (Source Drain, source drain) ion implantation, the source region 61 and the drain region 62 of the low-voltage transistor are respectively formed in the regions on both sides of the polysilicon gate in the first well region 31 , and the polysilicon gate in the second well region 32 is formed. The regions on both sides of the electrode respectively form the source region 63 and the drain region 64 of the high-voltage transistor.

In this embodiment, the ion type of the lightly doped drain (LDD) ion implantation is the same as that of the SD ion implantation. When the ions implanted by SD ions are N-type ions, the ions implanted by the lightly doped drain (LDD) ions are N-type ions, and when the ions implanted by SD ions are P-type ions, the lightly doped drain (LDD) ions are The implanted ions are P-type ions.

In the above embodiment, in order to reduce more lattice damage, the implanted ions are preferably elements with lower atomic numbers. For example, the implanted ions can be boron ions (B+), boron fluoride ions (BF+) and phosphorus ions. at least one of (P+).

The hard mask layer 52 is removed. In this step, the gate oxide layer 40 a and the gate oxide layer 40 b are protected by the spacers 53 . The sidewall spacers 53 formed by depositing a thin high temperature oxide film (HTO) are thinner, and a silicon oxide layer can also be deposited on the outside of the sidewall spacers 53, or an ONO layer (silicon oxide layer-silicon nitride layer-silicon oxide layer) is formed. Thick spacers are used to protect the sidewalls of the polysilicon gate 50 . In the subsequent process, the outermost oxide layer in the ONO layer is easily consumed, leaving the innermost oxide layer and silicon nitride layer.

A low-voltage transistor is formed on the first well region 31 , and a gate oxide layer 40 a , a polysilicon gate level 50 , a protective layer 51 and a hard mask layer 52 are sequentially formed on the first well region 31 from bottom to top. A high voltage transistor is formed on the second well region 32, and a gate oxide layer 40a, a polysilicon gate level 50, a protection layer 51 and a hard mask layer 52 are sequentially formed on the second well region 32 from bottom to top.

Subsequent processes include: depositing a dielectric layer by using a PECVD method, using a chemical mechanical polishing (CMP) process to complete the planarization process of the dielectric layer, and then using a dry etching process to complete the device contact hole processing. The device contact hole filling process is completed by tungsten sputtering process and tungsten chemical mechanical planarization process. The source and drain regions can be drawn out through contact holes. Sputtering Al-Si-Cu film and completing metal wiring etching.

The CMOS device according to the embodiment of the present invention, as shown in FIG. 4 ,

A substrate 10, on which a first well region 31 and a second well region 32 are formed; a gate oxide layer is formed on both the first well region 31 and the second well region 32, and is located in the The thickness of the gate oxide layer 40a in the first well region is smaller than the thickness of the gate oxide layer 40b in the second well region;

On the gate oxide layer 40a of the first well region and the gate oxide layer 40b of the second well region, a polysilicon gate 50, a protective layer 51 and a hard mask layer 52 are formed in sequence;

Sidewalls 51 are formed on the sidewalls of the polysilicon gate 50;

Both the first well region 31 and the second well region 32 are formed with lightly doped drain regions.

The sidewall spacers 53 also cover the sidewalls of the protection layer 51 , and the bottoms of the sidewall spacers 53 cover the portions of the gate oxide layer exposed by the polysilicon gate 50 at both ends. The hard mask layer includes a silicon nitride layer, and the protective layer includes a silicon oxide layer.

In summary, the present invention provides a CMOS device and a method for forming the same, including: providing a substrate, forming a first well region and a second well region on the substrate; forming a gate on the first well region and the second well region an oxide layer; a polysilicon layer, a protective layer and a hard mask layer are sequentially formed on the gate oxide layer of the first well region and the gate oxide layer of the second well region; the hard mask layer and the protective layer are etched and the polysilicon layer, forming polysilicon gates located above the first well region and the second well region respectively; forming sidewall spacers covering at least the sidewalls of the polysilicon gates; using the hard mask layer as The mask performs light doping of the drain. During the light drain doping (LDD) process, the top of the polysilicon gate level is protected by the hard mask layer and the protective layer, and the sidewalls of the polysilicon gate level are protected by spacers, so that the polysilicon gate level is protected by spacers. The level avoids penetration during LDD and improves the threshold voltage/leakage current (Vt/ID) consistency of CMOS devices.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. As for the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (10)

1. A method for forming a CMOS device, comprising: providing a substrate on which a first well region and a second well region are formed; forming a gate oxide layer on the first well region and the second well region, the thickness of the gate oxide layer located in the first well region is smaller than the thickness of the gate oxide layer located in the second well region; forming a polysilicon layer, a protective layer and a hard mask layer in sequence on the gate oxide layer of the first well region and the gate oxide layer of the second well region; Etching the hard mask layer, the protective layer and the polysilicon layer to form polysilicon gate levels respectively located above the first well region and the second well region; forming spacers covering at least the sidewalls of the polysilicon gates; and Drain light doping is performed using the hard mask layer as a mask. 2. The method for forming a CMOS device according to claim 1, wherein the sidewall spacers are formed by depositing a thin high temperature oxide film. 3. The method for forming a CMOS device according to claim 1, wherein after performing light source-drain doping using the hard mask layer as a mask, the method further comprises: The hard mask layer is removed. 4 . The method for forming a CMOS device according to claim 1 , wherein after forming the polysilicon gate, and before forming the sidewall spacers covering at least sidewalls of the polysilicon gate, the method further comprises: performing rapid thermal oxidation. 5 . annealing. 5 . The method for forming a CMOS device according to claim 4 , wherein the rapid thermal oxidation annealing process comprises: in a dry O ₂ environment, the annealing temperature range is: 1000° C.˜1200° C., and the annealing time is 30s˜60s. 6 . . 6 . The method for forming a CMOS device according to claim 1 , wherein a first voltage transistor is formed on the first well region, a second voltage transistor is formed on the second well region, and the first voltage transistor less than the second voltage. 7. The method for forming a CMOS device according to claim 6, wherein the first voltage comprises: 1.2V or 1.5V; the second voltage comprises: 5V or 12V. 8. A CMOS device, comprising: A substrate, on which a first well region and a second well region are formed; a gate oxide layer is formed on both the first well region and the second well region, and the gate of the first well region is located The thickness of the oxide layer is smaller than the thickness of the gate oxide layer located in the second well region; The gate oxide layer of the first well region and the gate oxide layer of the second well region are stacked in order to form a polysilicon gate, a protective layer and a hard mask layer; sidewalls of the polysilicon gate are formed with sidewalls; Both the first well region and the second well region are formed with lightly doped drain regions. 9 . The CMOS device according to claim 8 , wherein the sidewall spacers further cover sidewalls of the protective layer, and the bottoms of the sidewall spacers cover the gate oxide layer and both ends of the gate oxide layer are covered by the polysilicon gate. 10 . Extremely exposed part. 10. The CMOS device of claim 8, wherein the hard mask layer comprises a silicon nitride layer, and the protective layer comprises a silicon oxide layer.

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