CN103367128A - Method for forming ultra-steep inverted doped channel, semiconductor device and manufacturing method thereof - Google Patents

Abstract

The application discloses a method for forming a super-steep retrograde doped channel, a semiconductor device including a super-steep retrograde doped channel and a manufacturing method thereof. The method includes: forming a mask exposing a semiconductor substrate region corresponding to a channel region and a source/drain extension region of a semiconductor device; performing a first ion implantation using the mask, implanting and semiconductor first ions of the same conductivity type of the substrate; and performing a second ion implantation using a mask to implant second ions of the same conductivity type as the semiconductor substrate into the semiconductor substrate, wherein the first ion implantation and the second ion implantation The implanted regions formed by secondary ion implantation are partially overlapped to form a super-steep retrograde doping region.

Description

Method for forming ultra-steep retrograde doped channel, semiconductor device and manufacturing method thereof

technical field

The present invention relates to a semiconductor device and a manufacturing method thereof, more specifically, to a method for forming an ultra-steep retrograde doped channel, a semiconductor device including a super-steep retrograde doped channel and a manufacturing method thereof.

Background technique

An important development direction of integrated circuit technology is to scale down the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) to improve integration and reduce manufacturing costs. However, it is well known that short-channel effects occur as the size of MOSFETs decreases. As the size of the MOSFET is scaled down, the effective length of the gate is reduced, so that the proportion of depletion layer charge that is actually controlled by the gate voltage is reduced, so that the threshold voltage decreases as the channel length decreases.

On the one hand, in order to suppress the short channel effect, the doping concentration of the channel can be increased to increase the threshold voltage of the semiconductor device. However, if the doping concentration of the channel is greater than 6×10 ¹⁸ /cm ³ , the conventional channel doping method will bring a series of serious problems, such as too high threshold voltage, significantly increased junction capacitance, and current-carrying Sub-effective mobility μ _eff seriously decreased. As a result, the circuit performance of the MOSFET deteriorates, and both the operating frequency and the driving capability are reduced.

On the other hand, it may be desirable to reduce the threshold voltage of a semiconductor device in an application. For example, in semiconductor devices of 20 nanometers and below, the power supply voltage used has been reduced to about 0.8V. Correspondingly, the threshold voltage of the semiconductor device should be controlled at about ±0.2V to obtain a small off-state leakage current I _off and logic noise tolerance. In order to reduce the threshold voltage, the doping concentration of the channel can be reduced. However, reducing the doping concentration of the channel may lead to the above-mentioned short channel effect.

In the method of adjusting the threshold voltage by channel doping, an improved technique includes forming a super-steep retrograde doping region under the channel region, and using the super-steep retrograde doping method to form a steep doping concentration distribution in the channel region . The doping concentration of the ultra-steep retrograde doping region is higher than that of the channel region. The channel region and the ultra-steep retrograde doping region together form a super-steep retrograde doped channel, and its advantages include suppressing the short channel effect, improving carrier mobility in the channel region, and reducing parasitic capacitance. Thus, the operating frequency and driving capability can be improved while adjusting the threshold voltage of the semiconductor device.

The difficulty in forming the ultra-steep retrograde doped channel is that the dopant in the super-steep retrograde doped region diffuses outwards, and as a result, it is difficult to achieve the required steep doping concentration distribution.

Contents of the invention

The object of the present invention is to provide an improved method for manufacturing an ultra-steep retrograde doped channel, a semiconductor device including a super-steep retrograde doped channel and a manufacturing method thereof.

According to one aspect of the present invention, there is provided a method for forming an ultra-steep retrograde doped channel, comprising: forming a mask exposing a semiconductor substrate region corresponding to a channel region and a source/drain extension region of a semiconductor device ; using a mask to perform the first ion implantation, implanting first ions of the same conductivity type as the semiconductor substrate into the semiconductor substrate; and using a mask to perform the second ion implantation, implanting into the semiconductor substrate Second ions of the same conductivity type at the bottom, wherein the implanted regions formed by the first ion implantation and the second ion implantation are partially overlapped to form a super-steep retrograde doping region.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming an isolation structure on a semiconductor substrate to define an active region of the semiconductor device; forming an ultra-steep retrograde doped channel according to the above method; Forming a gate stack including a gate dielectric and a gate conductor over the channel region, wherein the gate dielectric is sandwiched between the gate conductor and the channel region; forming first spacers on both sides of the gate stack; using The gate stack, the first side wall and the isolation structure are used as a hard mask to pre-amorphize the semiconductor substrate; the gate stack, the first side wall and the isolation structure are used as a hard mask to pre-amorphize the semiconductor substrate Implanting the extension region; forming a second sidewall on the first sidewall; using the gate stack, the first sidewall, the second sidewall and the isolation structure as a hard mask, and performing source/drain implantation on the semiconductor substrate.

According to another aspect of the present invention, a semiconductor device is provided, including: a semiconductor substrate; a source/drain region and a source/drain extension region formed in the semiconductor substrate; a channel region between the extension regions; an ultra-steep retrograde doped region formed in the semiconductor substrate and located below the channel region and source/drain extension regions; a gate dielectric located above the channel region; and a gate dielectric located The upper gate conductor, wherein the doping ions in the super-steep retrograde doping region include first ions and second ions of the same conductivity type as the semiconductor substrate, wherein the second ions have a larger atomic weight than the first ions .

The invention utilizes the doping of two kinds of ions to form a super-steep retrograde doping region, in which heavy ions have a low diffusion coefficient and are mainly gathered near the channel region to form a steep doping concentration distribution. The doping concentration near the surface of the channel region can be low enough to obtain a suitably low threshold voltage while obtaining high carrier mobility. The ultra-steep retrograde doping region below the channel region excellently suppresses severe short channel effects (SCE) and DIBL effects from occurring close to the surface of the channel region. The mask can also be used to limit the lateral extension of the super-steep retrograde doping region, so as to reduce the junction capacitance, which is beneficial to the improvement of the speed.

Furthermore, the semiconductor device of the present invention can use the halo region to further suppress the occurrence of severe short channel effect (SCE) and DIBL effect in the body.

Description of drawings

1 to 8 show schematic cross-sectional views of different stages of manufacturing a semiconductor device including an ultra-steep retrograde channel according to an embodiment of the present invention.

FIG. 9 shows the simulation results of the doping concentration distribution of the ultra-steep retrograde doped channel formed according to the embodiment of the present invention.

FIG. 10 shows simulation results of sub-threshold characteristics of a semiconductor device formed according to an embodiment of the present invention.

Detailed ways

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various figures, identical elements are indicated with similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale.

For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.

If it is to describe the situation of being directly on another layer or another area, the expression "directly on" or "on and adjacent to" will be used herein.

In the present application, the term "semiconductor structure" refers to a general designation of the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.

In the following, many specific details of the present invention are described, such as device structures, materials, dimensions, processing techniques and techniques, for a clearer understanding of the present invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art.

Unless otherwise specified below, various parts in the semiconductor device may be composed of materials known to those skilled in the art. The semiconductor material includes, for example, Group III-V semiconductors, such as GaAs, InP, GaN, SiC, and Group IV semiconductors, such as Si and Ge. The gate conductor layer can be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaTbN , TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni ₃ Si, Pt, Ru, Ir, Mo, HfRu, RuOx| and the various combination of conductive materials. The gate dielectric layer can be made of _SiO2 or a material with a dielectric constant greater than _SiO2 , such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, where the oxides include SiO _2. HfO ₂ , ZrO ₂ , Al ₂ O ₃ , TiO ₂ , La ₂ O ₃ , nitrides such as Si ₃ N ₄ , silicates such as HfSiOx, aluminates such as LaAlO ₃ , titanates such as SrTiO ₃ , oxynitrides include, for example, SiON. Moreover, the gate dielectric layer can be formed not only from materials known to those skilled in the art, but also from materials developed in the future for the gate dielectric layer.

According to an embodiment of the present invention, the following steps shown in FIGS. 1 to 8 are performed to fabricate a semiconductor device including an ultra-steep retrograde doped channel, in which cross-sectional views of semiconductor structures at different stages are shown.

As shown in FIG. 1, a pad oxide is formed on a semiconductor substrate 101 by a known deposition process, such as electron beam evaporation (EBM), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, etc. layer 102 and pad nitride layer 103 . In one example, the pad oxide layer 102 is formed by thermal oxidation, and the pad nitride layer 103 is formed by chemical vapor deposition. The pad oxide layer 102 can relieve stress between the substrate 101 and the pad nitride layer 103 , and has a thickness of, for example, 2-15 nanometers. The substrate nitride layer 103 is used as a stop layer in a subsequent chemical mechanical polishing (CMP) process, and has a thickness of, for example, 50-150 nm. Then, a photoresist layer 201 is formed on the substrate nitride layer 103 by spin coating, and is patterned by a photolithography process including exposure and development.

Then, using the photoresist layer 201 as a mask, by dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by wet etching in which an etchant solution is used, from top to Next, the exposed portions of the pad nitride layer 103 and the pad oxide layer 102 , and a part of the semiconductor substrate 101 are sequentially removed to form a trench in the semiconductor substrate 101 . The etching time is controlled so that etching stops at a certain depth in the semiconductor substrate 101 . Then, the photoresist layer 201 is removed by dissolving in a solvent or ashing. By means of the known deposition processes described above, a covering oxide layer is formed over the entire surface of the semiconductor structure. Then, using the pad oxide layer 103 as a stop layer, the entire semiconductor structure is chemically mechanically planarized to obtain a flat surface. The chemical mechanical planarization removes the oxide outside the trenches in the semiconductor substrate 101 such that the oxide remaining inside the trenches forms shallow trench isolations (STIs) 104 , as shown in FIG. 2 .

Then, the pad nitride layer 103 is removed, for example, by wet etching using hot phosphoric acid (eg, 160° C.), and the pad oxide layer 102 is removed by wet etching using a hydrofluoric acid buffer. For example, an oxide protective layer (screen layer) 105 with a thickness of about 5 nanometers is grown on the surface of the semiconductor substrate 101 by thermal oxidation, as shown in FIG. 3 . The oxide protection layer 105 is used to protect the crystal structure of the surface of the semiconductor substrate 101 from being damaged in a subsequent ion implantation step. The oxide protection layer 105 has a uniform thickness so that ions can pass through the oxide protection layer 105 to reach the same depth in the semiconductor substrate 101 in a subsequent ion implantation step.

Then, a photoresist layer 202 is formed on the entire surface of the semiconductor structure by spin coating, and is patterned by a photolithography process including exposure and development. The photoresist layer 202 includes windows exposing at least the channel region and source/drain extension regions of the semiconductor device to be formed. Using the photoresist layer 202 as a mask, the first ion implantation is performed. The first ion implantation implants conventional ions of the same conductivity type as the semiconductor substrate 101 into the semiconductor substrate 101 through the window in the photoresist layer 202 , as shown in FIG. 4 . For NMOS devices, the conductivity type of the semiconductor substrate 101 is P-type, and the first ion implantation uses P-type conventional ions, such as boron ions ( ¹¹ B), with an energy of 40-50KeV and a dose of 1-1.4E13cm ⁻² . For PMOS devices, the conductivity type of the semiconductor substrate 101 is N-type, and the first ion implantation uses N-type conventional ions, such as phosphorus ion ( ³¹ P) implantation, with an energy of 100-120KeV and a dose of 1-1.4E13cm ⁻² .

The first ion implantation forms a first implantation region 106 under the channel region to be formed in the semiconductor substrate 101 . Then, still using photoresist layer 202 as a mask, a second ion implantation is performed. The second ion implantation implants heavy ions of the same conductivity type as the semiconductor substrate 101 into the semiconductor substrate 101 through the window in the photoresist layer 202 , as shown in FIG. 5 . For NMOS devices, the conductivity type of the semiconductor substrate 101 is P-type, and the second ion implantation uses P-type heavy ions, such as indium ions ( ¹¹⁵ In), with an energy of 170-210KeV and a dose of 1-1.4E13cm ⁻² . For PMOS devices, the conductivity type of the semiconductor substrate 101 is N-type, and the second ion implantation uses N-type heavy ions, such as antimony ions ( ¹²³ Sb ), with an energy of 170-210KeV and a dose of 1-1.4E13cm ⁻² . In this application, heavy ions refer to ions having an atomic mass greater than that of conventional dopant ions.

After the second ion implantation, the photoresist layer 202 is removed by dissolving in a solvent or ashing.

The energy of the second ion implantation is greater than that of the first ion implantation, so that the implanted regions of the two ion implantations partially overlap to form a super-steep retrograde doping region 106 , as shown in FIG. 6 . A part of the semiconductor substrate 101 above the super-steep retrograde doping region 107 serves as a channel region (not shown) of a semiconductor device to be formed.

Then, the oxide protective layer 105 is removed by wet etching using a hydrofluoric acid buffer to expose the surface of the semiconductor substrate 101 . A conformal dielectric layer followed by an overlying polysilicon layer is sequentially formed and patterned over the entire surface of the semiconductor structure by known processes described above to form a gate stack comprising a gate dielectric 108 and a gate conductor 109 . Next, through the above-mentioned known process, a nitride layer of, for example, 10-50 nanometers is deposited on the entire surface of the semiconductor structure, and then the first sidewalls 110 located on both sides of the gate stack are formed by anisotropic etching, as shown in FIG. 7.

Then, the exposed portion of the semiconductor substrate 101 is pre-amorphized by using the gate stack, the first sidewall and the shallow trench isolation 104 as a hard mask. In one example, the pre-amorphization includes implanting Ge ions into the semiconductor substrate 101 with an energy of 15-25KeV and a dose of 4-9E14. The pre-amorphization forms an amorphization region in the semiconductor substrate 101, which is beneficial to forming a shallow junction in a subsequent implantation step.

Further, using the gate stack, the first spacer 110 and the shallow trench isolation 104 as a hard mask, an extension region implantation is performed on the semiconductor substrate 101 to form a source/drain extension region 111 . The extension region implantation implants ions of a conductivity type opposite to that of the semiconductor substrate 101 into the semiconductor substrate 101 . For NMOS devices, N-type dopants, such as As ions, are used for implantation in the extension region, with an implantation energy of 1-3KeV and a dose of 6-10E14. For PMOS devices, the extension region is implanted with P-type dopants, such as BF2 ions, with an implantation energy of 1-3KeV and a dose of 2-6E14.

Further, by using the gate stack, the first spacer 110 and the shallow trench isolation 104 as a hard mask, a halo implantation is performed on the semiconductor substrate 101 to form a source/drain halo 112 . In the halo implantation, ions of the same conductivity type as the semiconductor substrate 101 are implanted into the semiconductor substrate 101 at an oblique angle. For NMOS devices, halo implantation uses P-type dopants, such as BF ₂ ions, with implantation energy of 40-60KeV, dose of 4-8E13, and inclination angle of 25-30 degrees. For PMOS devices, the halo implant uses N-type dopants, such as As ions, with implantation energy of 50-60KeV, dose of 2-5E13, and inclination angle of 25-30 degrees.

Since the halo implantation is performed at an oblique angle, and the depth of the halo implantation is greater than that of the extension region, the halo 112 is located below the extension region 111 and is closer to the center of the channel.

Further, in a manner similar to that of the first side wall 110 , a second side wall 113 is formed on the first side wall 110 . Using the gate stack, the first spacer 110 , the second spacer 113 and the shallow trench isolation 104 as a hard mask, source/drain implantation is performed on the semiconductor substrate 101 to form the source/drain region 114 .

Then, for example, a spike anneal is performed at a temperature of about 1000-1080° C. for 3-5 seconds to activate the dopant ions implanted by the previous implantation step and eliminate the damage caused by the implantation.

The semiconductor device formed according to the above steps includes a source/drain region 114 , a source/drain extension region 111 and a source/drain halo 112 , as shown in FIG. 8 . However, source/drain extensions 111 and source/drain halos 112 are optional, as will be understood by those skilled in the art. In an alternative embodiment, the semiconductor device may only include the source/drain region 114, thus the steps of forming the first spacer, pre-amorphization, extension region implantation and halo implantation may be omitted in the above steps. In alternative embodiments, the semiconductor device may only include source/drain regions 114 and source/drain extension regions 111 . Therefore, the step of halo implantation can be omitted in the above steps.

In the above embodiments, it is shown that the semiconductor device includes the shallow trench isolation 104 for defining the active region of the semiconductor device. However, in alternative embodiments, LOCOS isolation may be used instead of shallow trench isolation.

In the above embodiments, conventional ions are implanted in the first ion implantation, and heavy ions are implanted in the second ion implantation, so as to form the super-steep retrograde doped region 106 . However, in an alternative embodiment, heavy ions may be implanted in the first ion implantation and regular ions may be implanted in the second ion implantation. Although this alternative embodiment is not the most preferred, it still provides an advantageously steep doping concentration profile.

FIG. 9 shows the simulation results of the doping concentration distribution of the ultra-steep retrograde doped channel formed according to the embodiment of the present invention. Curve c1 represents the doping concentration distribution of the P-type well formed by well implantation and high-temperature boost before forming the super-steep retrograde doping region 107, and curve c2 represents the doping concentration distribution after the super-steep retrograde doping region 107 is formed , where the abscissa represents the depth from the main surface of the semiconductor substrate 101 , and the ordinate represents the doping concentration.

The well implantation can be performed before or simultaneously with the ion implantation step for forming the super-steep retrograde doped region 107 .

As shown by the curve c2, due to the low diffusion coefficient of heavy ions, the concentration peak of the ultra-steep retrograde doping region 107 appears at a depth of about 64 nanometers from the main surface of the semiconductor substrate 101, thereby achieving a steep doping concentration distribution.

FIG. 10 shows simulation results of sub-threshold characteristics of a semiconductor device formed according to an embodiment of the present invention. Due to the use of the above-mentioned ultra-steep retrograde doping channel, for NMOS (gate length about 20nm) and PMOS (gate length about 15nm) devices using metal gate/high-K dielectric, suitable values are obtained at different voltages V _D Low threshold voltage and well controlled short channel effects.

The above description is only for illustration and description of the present invention, not intended to be exhaustive and limitative of the present invention. Accordingly, the invention is not limited to the described embodiments. Variations or changes that are obvious to those skilled in the art are within the protection scope of the present invention.

Claims (16)

1. A method for forming an ultra-steep retrograde doped channel, comprising: forming a mask exposing regions of the semiconductor substrate corresponding to channel regions and source/drain extension regions of the semiconductor device; performing a first ion implantation using a mask to implant first ions of the same conductivity type as the semiconductor substrate into the semiconductor substrate; and performing a second ion implantation using a mask, implanting second ions of the same conductivity type as the semiconductor substrate into the semiconductor substrate, The implanted regions formed by the first ion implantation and the second ion implantation are partially superimposed to form a super-steep retrograde doping region. 2. The method of claim 1, wherein the atomic mass of the first ion is less than the atomic mass of the second ion. 3. The method of claim 1, wherein the atomic mass of the first ion is greater than the atomic mass of the second ion. 4. The method according to claim 1, wherein the energy of the first ion implantation is 30-60KeV, and the energy of the second ion implantation is 160-210KeV. 5. The method of claim 2, wherein the semiconductor device is an NMOS device, and the first ions are boron ions and the second ions are indium ions. 6. The method of claim 3, wherein the semiconductor device is an NMOS device, and the first ions are indium ions and the second ions are boron ions. 7. The method of claim 2, wherein the semiconductor device is a PMOS device, and the first ions are phosphorous ions and the second ions are antimony ions. 8. The method of claim 3, wherein the semiconductor device is a PMOS device, and the first ions are antimony ions and the second ions are phosphorus ions. 9. The method of claim 1, further comprising forming an oxide protection layer on the surface of the half substrate before forming the mask. 10. A method of manufacturing a semiconductor device, comprising: forming an isolation structure on a semiconductor substrate to define an active region of a semiconductor device; forming an ultra-steep retrograde doped channel according to the method described in any one of claims 1 to 9; forming a gate stack comprising a gate dielectric and a gate conductor over the channel region, wherein the gate dielectric is sandwiched between the gate conductor and the channel region; forming first spacers on both sides of the gate stack; Pre-amorphizing the semiconductor substrate by using the gate stack, the first sidewall and the isolation structure as a hard mask; Using the gate stack, the first sidewall and the isolation structure as a hard mask, performing extension region implantation on the semiconductor substrate; forming a second side wall on the first side wall; Source/drain implantation is performed on the semiconductor substrate by using the gate stack, the first side wall, the second side wall and the isolation structure as a hard mask. 11. The method according to claim 10, between the step of implanting the extension region and the step of forming the second spacer, further comprising using the gate stack, the first spacer and the isolation structure as a hard mask, for The semiconductor substrate is halo-implanted in an oblique manner. 12. A semiconductor device comprising: semiconductor substrate; source/drain regions and source/drain extension regions formed in the semiconductor substrate; a channel region formed in a semiconductor substrate and sandwiched between source/drain extension regions; an ultra-steep retrograde region formed in the semiconductor substrate and located below the channel region and source/drain extension regions; a gate dielectric over the channel region; and a gate conductor over the gate dielectric, Wherein, the doping ions in the super-steep retrograde doping region include first ions and second ions of the same conductivity type as the semiconductor substrate, wherein the second ions have a larger atomic weight than the first ions. 13. The semiconductor device according to claim 12, wherein the ultra-steep retrograde doping region has a peak value of doping concentration near the channel region. 14. The semiconductor device according to claim 12, wherein the semiconductor device is an NMOS device, and the first ions are boron ions and the second ions are indium ions. 15. The semiconductor device according to claim 12, wherein the semiconductor device is a PMOS device, and the first ions are phosphorous ions and the second ions are antimony ions. 16. The semiconductor device of claim 12, further comprising a source/drain halo region.

Images