CN113437148B - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same provide a substrate including a first region, a second region, and a third region, the second region being located between the first region and the third region; forming a drift region in the substrate of the second region, wherein the drift region extends into the first region and the third region of the substrate; forming a drain doping layer on the first region and the third region; forming a channel column on the drain doped layer of the first region; and forming a grid structure on the side wall surface of the channel column. In the technical scheme of the invention, the area of the channel region is effectively increased because the grid structure fully surrounds the side wall surface of the channel column, so that the working current of the transverse double-diffusion field effect transistor is increased; in addition, the channel column is arranged perpendicular to the surface direction of the substrate, the occupied area is small, the design size of a finally formed semiconductor structure can be effectively reduced, and the density of devices in the semiconductor structure is improved.

Description

Semiconductor structures and methods of forming them

Technical field

The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a forming method thereof.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density, higher integration and higher performance.

LDMOS (Laterally Diffused Metal Oxide Semiconductor) is a power device with a double diffusion structure. This technology involves two ion implantations into the substrate, one with a higher concentration of arsenic (As) and the other with a smaller concentration of boron (B). After the implantation, a high-temperature annealing process is performed. Since boron diffuses faster than arsenic, it will diffuse farther along the lateral direction under the gate boundary, forming a channel with a concentration gradient. Its channel length is determined by these two lateral diffusions. determined by the distance difference. In order to increase the breakdown voltage, there is a drift region between the source and drain regions.

The drift region in LDMOS is the key to the design of this type of device. The impurity concentration in the drift region is relatively low. Therefore, when the LDMOS is connected to a high voltage, the drift region can withstand higher voltages due to its high resistance. In addition, LDMOS has the characteristics of high gain, good reliability, and has good process compatibility with CMOS. Therefore, LDMOS is being widely used.

However, existing lateral double-diffusion field effect transistors (LDMOS transistors) still have certain problems.

Contents of the invention

The technical problem solved by the present invention is to provide a semiconductor structure and a forming method thereof, which can effectively reduce the design size of the final formed semiconductor structure and increase the device density in the semiconductor structure.

In order to solve the above problems, the present invention provides a semiconductor structure, including: a substrate, the substrate includes a first region, a second region and a third region, the second region is located between the first region and the third region. Between the three regions; a drift region located in the second region of the substrate, the drift region extending into the first region and the third region of the substrate; located in the first region and the third region of the substrate a drain doped layer on the drain doped layer, the drain doped layer is doped with first ions; a channel pillar located on the drain doped layer of the first region; a gate electrode located on the sidewall surface of the channel pillar structure.

Optionally, the method further includes: second ions doped in the drift region, and the conductivity type of the second ions is the same as the conductivity type of the first ions.

Optionally, the first ions include N-type ions or P-type ions.

Optionally, when the first ions are N-type ions, the second ions include phosphorus ions or arsenic ions, and the implantation dose of the second ions is 1E18atm/cm ³ to 3E20atm/cm ³ ; The implantation energy of secondary ions is 10keV~50keV.

Optionally, when the first ions are P-type ions, the second ions include boron ions or indium ions, and the implantation dose of the second ions is 2E18atm/cm ³ to 5E20atm/cm ³ ; The implantation energy of diions is 5keV~45keV.

Optionally, it also includes: an isolation structure located on the substrate, the isolation structure covers the drift region and part of the sidewall surface of the channel column, and the top surface of the isolation structure is lower than the trench. The top surface of the pillar.

Optionally, it also includes: a source doping layer located on the top of the channel column.

Optionally, it also includes: a dielectric layer located on the substrate, the dielectric layer covering the gate structure, channel column and source doping layer; and a conductive structure located in the dielectric layer.

Optionally, the conductive structure includes: a first conductive plug connected to the source doped layer; a second conductive plug connected to the gate structure; and a drain doped layer of the third region. Connect the third conductive plug.

Optionally, the second area is adjacent to the first area and the third area respectively.

Correspondingly, the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region, a second region and a third region, the second region is located in the first region and the third region; a drift region is formed in the substrate of the second region, and the drift region extends toward the first region and the third region of the substrate; in the first region A drain doped layer is formed on the first region and the third region, and the drain doped layer is doped with first ions; a channel pillar is formed on the drain doped layer of the first region; in the channel The sidewall surface of the pillar forms a gate structure.

Optionally, the method of forming a drain doped layer on the first region and the third region includes: forming an initial drain doped layer on the substrate; forming a mask on the initial drain doped layer. film layer; forming a patterned layer on the mask layer, the patterned layer exposing part of the top surface of the mask layer; using the patterned layer as a mask to etch the mask layer and the an initial drain doping layer on the second region substrate until the top surface of the second region substrate is exposed, and the drain doping layer is formed on the first region and the third region; in After the drain doping layer is formed on the first region and the third region, the patterned layer and the mask layer are etched away.

Optionally, before forming the mask layer, the method further includes: forming protective sidewalls on sidewall surfaces of the channel pillars;

Optionally, after etching and removing the patterned layer and the mask layer, the protective spacers are removed.

Optionally, the formation method of the protective spacers includes: forming a spacer material layer on the sidewall surface and the top surface of the channel pillar and the top surface of the initial drain doped layer; etching back the Protect the spacer material layer until the top surface of the channel pillar and the top surface of the initial drain doping layer are exposed, and form the protective spacer on the sidewall surface of the channel pillar.

Optionally, the material of the protective sidewall includes silicon nitride.

Optionally, the formation process of the protective spacer material layer includes an atomic layer deposition process.

Optionally, before etching away the patterned layer and the mask layer, the method further includes: performing ion implantation into the second region of the substrate, doping the drift region with second ions, The conductivity type of the second ions is the same as the conductivity type of the first ions.

Optionally, the first ions include N-type ions or P-type ions.

Optionally, when the first ions are N-type ions, the second ions include phosphorus ions or arsenic ions, and the implantation dose of the second ions is 1E18atm/cm ³ to 3E20atm/cm ³ ; The implantation energy of secondary ions is 10keV~50keV.

Optionally, when the first ions are P-type ions, the second ions include boron ions or indium ions, and the implantation dose of the second ions is 2E18atm/cm ³ to 5E20atm/cm ³ ; The implantation energy of diions is 5keV~45keV.

Optionally, before forming a gate structure on the sidewall surface of the channel pillar, the method further includes: forming an isolation structure on the substrate, the isolation structure covering the drift region and part of the channel pillar. The sidewall surface and the top surface of the isolation structure are lower than the top surface of the channel pillar.

Optionally, after forming a gate structure on the sidewall surface of the channel pillar, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the gate structure and the channel pillar; Conductive structures are formed within the dielectric layer.

Optionally, after forming the dielectric layer and before forming the conductive structure, the method further includes: forming a source doping layer on top of the channel pillar.

Optionally, the conductive structure includes: a first conductive plug connected to the source doped layer; a second conductive plug connected to the gate structure; and a drain doped layer of the third region. Connect the third conductive plug.

Optionally, the second area is adjacent to the first area and the third area respectively.

Compared with the existing technology, the technical solution of the present invention has the following advantages:

In the semiconductor structure of the technical solution of the present invention, through the drift region located in the second region of the substrate, the drift region extends to the first region and the third region of the substrate and is located in the first region. and a drain doped layer on the substrate in the third region, a channel column located on the drain doped layer in the first region, a gate structure located on the sidewall of the channel column, and in subsequent processes The source doping layer formed in the gate structure enables the gate structure, source doping layer and drain doping layer to form a conductive path when turned on, thereby forming a lateral double diffusion field effect transistor based on the channel column perpendicular to the substrate surface. On the one hand, since the gate structure completely surrounds the sidewall surface of the channel column, the area of the channel region is effectively increased, thereby increasing the operating current of the lateral double diffusion field effect transistor; on the other hand, the channel The pillars are arranged perpendicular to the surface of the substrate and occupy a small area, which can effectively reduce the design size of the final semiconductor structure and increase the device density in the semiconductor structure.

Further, in the semiconductor structure of the technical solution of the present invention, it also includes: performing ion implantation into the second region of the substrate, doping the second ions in the drift region, and the conductivity type of the second ions is the same as that of the second region. The conductivity type of the first ion is the same. By doping the second ions in the drift region, the resistance in the drift region is increased, thereby increasing the breakdown voltage of the lateral double diffusion field effect transistor and improving the electrical performance of the finally formed semiconductor structure.

In the method for forming a semiconductor structure according to the technical solution of the present invention, before forming the drain doped layer on the first region and the third region, the method further includes: forming a protective layer on the sidewall surface of the channel pillar. side walls. In the subsequent doping process, the protective sidewall can prevent second ions from being implanted into the channel column during the ion implantation process. If there are second ions implanted into the channel column, it will cause the channel The ion migration efficiency in the channel region decreases, thereby affecting the electrical properties of the final semiconductor structure.

Description of the drawings

Figure 1 is a schematic structural diagram of each step in a method for forming a semiconductor structure;

2 to 14 are schematic structural diagrams of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed ways

As mentioned in the background art, existing lateral double diffusion field effect transistors still have certain problems. A detailed description will be given below with reference to the accompanying drawings.

Figure 1 is a schematic structural diagram of each step in the formation process of a semiconductor structure.

Referring to Figure 1, a semiconductor substrate (not shown in the figure) is provided; a P well 100 is formed in the semiconductor substrate; an N-type drift region 101 is formed in the P-well 100; in the N-type drift region The shallow trench isolation structure 104 in 101; the P-type body region 106 formed in the P-well 100 on one side of the N-type drift region 101; the gate structure 105 on the semiconductor substrate, the gate structure 105 spans the P-type body region 106 and the N-type drift region 101, and is partially located on the shallow trench isolation structure 104. The gate structure 105 includes a gate dielectric layer located on the semiconductor substrate, and is located on the gate dielectric layer. The gate electrode, the spacers located on the gate dielectric layer and the sidewalls on both sides of the gate electrode.

Please continue to refer to FIG. 1. After the gate structure is formed, a source region 102 is formed in the P-type body region 106 on one side of the gate structure 105, and an N-type body region is formed on the other side of the gate structure 105. The doping type of the drain region 103, the source region 102 and the drain region 103 in the type drift region 101 is N type.

In the above embodiments, the lateral double-diffusion field effect transistor formed has a planar structure. The problem of the planar lateral double-diffusion field effect transistor is that the volume used as the channel region A is small and only the gate area is small. The area in contact between the pole structure 105 and the P-well 100 has a small volume as the channel region A, which imposes limitations on increasing the operating current of the lateral double-diffusion field effect transistor. If you want to increase the lateral double-diffusion field effect To increase the working current of the tube, the volume of the semiconductor structure needs to be increased. However, with the further development of semiconductor technology, the size requirements for integrated circuit devices are getting smaller and smaller. The lateral double diffusion field effect transistor in this embodiment is further increasing. There are limitations on maximum operating current.

On this basis, the present invention provides a semiconductor structure and a method for forming the same. Through a drift region located in the second region of the substrate, the drift region extends to the first region and the third region of the substrate. , a drain doped layer located on the substrate in the first region and the third region, a channel pillar located on the drain doped layer located in the first area, and a gate located on the sidewall of the channel pillar. The gate structure, as well as the source doping layer formed in the subsequent process, enable the gate structure, source doping layer and drain doping layer to form a conductive path when turned on, thereby forming a channel pillar perpendicular to the substrate surface. Lateral double diffusion field effect tube. On the one hand, since the gate structure completely surrounds the sidewall surface of the channel column, the area of the channel region is effectively increased, thereby increasing the operating current of the lateral double diffusion field effect transistor; on the other hand, the channel The pillars are arranged perpendicular to the surface of the substrate and occupy a small area, which can effectively reduce the design size of the final semiconductor structure and increase the device density in the semiconductor structure.

In order to make the above objects, features and advantages of the present invention more obvious and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

2 to 14 are structural schematic diagrams of the formation process of a semiconductor structure according to embodiments of the present invention.

Referring to FIG. 2 , a substrate 200 is provided. The substrate includes a first region I, a second region II and a third region III. The second region II is located in the first region I and the third region III. between.

The material of the substrate 200 includes silicon (Si), germanium (Ge), silicon germanium (GeSi), and silicon carbide (SiC); it may also include silicon on insulator (SOI), germanium on insulator (GOI); or it may also include It can be other materials, such as gallium arsenide and other group III-V compounds. In this implementation, the material of the substrate 200 is silicon.

In this embodiment, the second area II is adjacent to the first area I and the third area III respectively.

Referring to FIG. 3 , a drift region 201 is formed in the substrate 200 in the second region II, and the drift region 201 extends into the first region I and the third region III of the substrate 200 .

The formation method of the drift region 201 includes: forming a well region 202 in the substrate 200; forming a first mask layer (not shown) on the substrate 200, and the first mask layer is exposed The area to be implanted; use the first mask layer as a mask to perform an ion doping process on the substrate 200 to form the drift region 201 in the well region 202. The depth of the drift region 201 is less than The depth of the well region 202.

In this embodiment, the well region 202 and the drift region 201 are formed through an ion implantation process.

In this embodiment, the formed lateral double-diffusion field effect transistor (LDMOS) is P-type, the well region 202 is doped with N-type impurity ions, and the drift region 201 is doped with P-type impurity ions; in In other embodiments, the formed lateral double-diffusion field effect transistor may also be N-type, the well region is doped with P-type impurity ions, and the drift region is doped with N-type impurity ions.

The N-type impurity ions are one or more of phosphorus ions, arsenic ions, and antimony ions; the P-type impurity ions are one or more of boron ions, indium ions, and gallium ions. In this embodiment, the N-type impurity ions are phosphorus ions, and the P-type impurity ions are boron ions.

After the drift region 201 is formed, a drain doped layer is formed on the first region I and the third region III, and the drain doped layer is doped with first ions; in the first region A channel pillar is formed on the drain doped layer of I. Please refer to Figure 4 to Figure 7 for the specific formation process of the channel pillar and the drain doped layer.

Referring to FIG. 4 , an initial drain doped layer 203 is formed on the substrate 200 .

In this embodiment, the initial drain doped layer 203 is formed using an ion implantation process.

Since the lateral double-diffusion field effect transistor formed in this embodiment is P-type, the first ions doped in the initial drain doping layer 203 are also P-type ions; in other embodiments, when the lateral double-diffusion field effect transistor formed in When the diffused field effect transistor is N-type, the first ions in the initial drain doping layer are N-type.

Referring to FIG. 5 , a channel pillar 204 is formed on the initial drain doped layer 203 .

The formation method of the channel pillar 204 includes: forming a channel material layer (not shown) on the initial drain doped layer 203; forming a second mask layer (not shown) on the surface of the channel material layer. ), the second mask layer exposes part of the surface of the channel material layer; use the second mask layer as a mask to etch the channel material layer until the initial drain doping layer is exposed 203 to the top surface, the channel pillar 204 is formed on the initial drain doped layer 203, and the channel pillar 204 is located on the first region I.

In this embodiment, the process of etching the channel material layer includes a dry etching process.

In this embodiment, the material of the channel pillar 204 includes silicon; in other embodiments, the material of the channel pillar may also include semiconductor materials such as germanium, silicon germanium, and gallium arsenide.

In this embodiment, the process of forming the channel material layer includes an epitaxial growth process; in other embodiments, the process of forming the channel material layer includes a physical vapor deposition process or an atomic layer deposition process.

After the channel pillars 204 are formed, the second mask layer is removed. In this embodiment, the process of removing the second mask layer includes an ashing process.

Referring to FIG. 6 , protective sidewalls 205 are formed on the sidewall surfaces of the channel pillars 204 .

The function of the protective spacers 205 is to perform ion implantation into the drift region 201 in the subsequent process, so that the drift region 201 is doped with second ions. The protective spacers 205 can prevent ions from being implanted during the ion implantation process. The second ions are implanted into the channel pillar 204. If there are second ions implanted into the channel pillar 204, the ion migration efficiency in the channel region will be reduced, thereby affecting the electrical properties of the finally formed semiconductor structure. performance.

The formation method of the protective spacers 205 includes: forming a spacer material layer (not shown) on the sidewall surface and the top surface of the channel pillar 204 and the top surface of the initial drain doped layer 203; back The protective spacer material layer is etched until the top surface of the channel pillar 204 and the top surface of the initial drain doped layer 203 are exposed, and the sidewall surface of the channel pillar 204 is formed. The protective side wall 205 is described.

In this embodiment, the formation process of the protective sidewall material layer includes an atomic layer deposition process; in other embodiments, the formation process of the protective sidewall material layer may also include a physical vapor deposition process or a chemical vapor deposition process. .

In this embodiment, the material of the protective sidewall 205 includes silicon oxide.

Referring to Figure 7, a mask layer 206 is formed on the initial drain doped layer 203; a patterned layer (not shown) is formed on the mask layer 206, and the patterned layer exposes part of the mask. The top surface of the film layer; use the patterned layer as a mask to etch the mask layer 206 and the initial drain doping layer 203 on the second region II substrate 200 until the second region II is exposed. The drain doped layer 207 is formed on the first region I and the third region III to the top surface of the substrate 200; after the drain doped layer 207 is formed, the patterned layer is removed.

The opening 208 is formed by etching and removing the initial drain doping layer 203 located on the second region II substrate 200. In the subsequent process, the opening 208 is filled through the isolation structure in order to pass through the isolation structure. The isolation structure in the opening 208 is used to increase the conduction path of the lateral double-diffusion field effect transistor, so as to increase the breakdown voltage of the lateral double-diffusion field effect transistor.

In this embodiment, the process used to etch the mask layer 206 and the initial drain doped layer 203 on the second region II substrate 200 includes a wet etching process; in other embodiments, etching The process used for the mask layer and the initial drain doping layer on the second region substrate includes a dry etching process.

In this embodiment, the material of the patterned layer includes photoresist, and the process of removing the patterned layer includes an ashing process.

Referring to FIG. 8, after forming the channel pillar 204 and the drain doped layer 207, ions are implanted into the second region II of the substrate 200, and the drift region 201 is doped with a second ions, the second ions having the same conductivity type as the first ions.

By doping the second ions in the drift region 201, the resistance in the drift region 201 is increased, thereby increasing the breakdown voltage of the lateral double diffusion field effect transistor, and improving the electrical properties of the final semiconductor structure. performance.

In this embodiment, the first ions are P-type ions, the second ions include boron ions or indium ions, and the implantation dose of the second ions is 2E18atm/cm ³ to 5E20atm/cm ³ ; The implantation energy of diions is 5keV~45keV.

In other embodiments, when the first ions are N-type ions, the second ions include phosphorus ions or arsenic ions, and the implantation dose of the second ions is 1E18atm/cm ³ to 3E20atm/cm ³ ; so The implantation energy of the second ions is 10keV˜50keV.

Referring to FIG. 9 , after ion implantation, the mask layer 206 and the protective spacer 205 are removed by etching.

In this embodiment, the process of etching and removing the mask layer 206 and the protective sidewall 205 adopts a dry etching process; in other embodiments, the process of etching and removing the mask layer and the protective sidewall 205 adopts a dry etching process. Wet etching process.

Referring to FIG. 10 , after etching and removing the mask layer 206 and protective spacers 205 , an isolation structure 209 is formed on the substrate 200 , and the isolation structure 209 covers the drift region 201 and the channel. Part of the sidewall surface of the pillar 204 and the top surface of the isolation structure 209 are lower than the top surface of the channel pillar 204 .

The formation method of the isolation structure 209 includes: forming an initial isolation structure (not shown) on the substrate 200, and the initial isolation structure covers the drain doped layer 207 and the second region II of the substrate 200. The drift region 201 and the channel pillar 204 on the upper surface are planarized until the top surface of the channel pillar 204 is exposed; part of the initial isolation structure is etched to form the The isolation structure 209 covers the drain doped layer 207, the drift region 201 on the second region II of the substrate 200, and part of the sidewall surface of the channel pillar 204.

In this embodiment, the material of the isolation structure 209 includes silicon oxide; in other embodiments, the material of the isolation structure may also be silicon nitride, silicon oxynitride, or low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) and one or more combinations of ultra-low K dielectric materials.

Referring to FIG. 11 , after forming the isolation structure 209 , a gate structure 210 is formed on the sidewall surface of the channel pillar 204 .

The gate structure 210 includes a first part surrounding the channel pillar 204 and a second part located on the surface of the isolation structure 209 .

The first part of the gate structure 210 includes: a gate dielectric layer located on the sidewall of the channel pillar 204, a work function layer located on the surface of the gate dielectric layer, and a gate layer located on the surface of the work function layer; In other embodiments, the first part of the gate structure may not include the work function layer.

The second part of the gate structure 210 includes: a work function layer located on the surface of the isolation structure 209, and a gate layer located on the surface of the work function layer; in other embodiments, the second part of the gate structure also The work function layer may not be included.

The formation method of the gate dielectric layer includes: forming a gate dielectric material layer (not shown) on the surface of the isolation structure 209 and the sidewall surface and top surface of the channel pillar 204; Form a third mask layer (not shown), the third mask layer exposes part of the surface of the gate dielectric material layer; use the third mask layer as a mask to etch the gate dielectric material layer, Until the surface of the isolation structure 209 is exposed, the gate dielectric layer is formed on the sidewall of the channel pillar 204 .

In other embodiments, the gate dielectric layer and the gate electrode layer may be formed at the same time. The formation method of the gate dielectric layer and the gate electrode layer includes: forming on the surface of the isolation structure and the channel pillar. A gate dielectric material layer is formed on the sidewall surface and the top surface; a gate material layer is formed on the gate dielectric material layer; a third mask layer is formed on the surface of the gate material layer, and the third mask layer is exposed Part of the surface of the gate material layer; use the third mask layer as a mask to etch the gate material layer and the gate dielectric material layer until the surface of the isolation structure is exposed, and in the channel Pillar sidewalls form the gate electrode layer and the gate dielectric layer.

In this embodiment, the material of the gate dielectric layer includes a high dielectric constant material, and the dielectric constant of the high dielectric constant material is greater than 3.9; the high dielectric constant material includes hafnium oxide or aluminum oxide; in other cases In an embodiment, the material of the gate dielectric layer includes silicon oxide.

In this embodiment, the process of forming the gate dielectric material layer includes a chemical vapor deposition process; in other embodiments, the process of forming the gate dielectric material layer includes an atomic layer deposition process.

The method for forming the work function layer and the gate layer includes: forming a work function material layer (not shown) on the surface of the isolation structure 209 and the gate dielectric layer; A gate material layer (not shown); forming a fourth mask layer (not shown) on the surface of the gate material layer, and the fourth mask layer exposes part of the surface of the gate material layer; so The fourth mask layer is a mask used to etch the gate material layer and the work function material layer until the surface of the isolation structure 209 is exposed. The work function layer and the gate layer located on the work function layer are formed on the surface.

The material of the work function layer includes titanium nitride, aluminum titanium or tantalum nitride. In this embodiment, the material of the work function layer includes titanium nitride.

The gate layer is made of polysilicon or metal. In this embodiment, the material of the gate layer includes metal, and the metal includes tungsten.

In this embodiment, the process of forming the work function material layer includes a chemical vapor deposition process or a physical vapor deposition process.

In this embodiment, the process of forming the gate material layer includes a physical vapor deposition process or an electroplating process.

In this embodiment, the process of etching the gate material layer and the work function material layer includes a dry etching process.

Referring to FIG. 12 , after the gate structure 210 is formed, a dielectric layer 211 is formed on the substrate 200 , and the dielectric layer 211 covers the gate structure 210 and the channel pillar 204 .

The formation method of the dielectric layer 211 includes: forming an initial dielectric layer (not shown) on the surface of the isolation structure 209, the initial dielectric layer covering the channel pillar 204 and the gate structure 210; The initial dielectric layer is planarized to form the dielectric layer 211.

In this embodiment, the material of the dielectric layer 211 includes silicon oxide; in other embodiments, the material of the dielectric layer may also include a low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or One or more combinations of ultra-low-k dielectric materials (referring to dielectric materials with a relative dielectric constant lower than 2.5).

Referring to FIG. 13 , after forming the dielectric layer 211 , a source doping layer 212 is formed on the top of the channel pillar 204 .

The formation method of the source doped layer 212 includes: forming a dielectric layer opening (not shown) in the dielectric layer 211, the dielectric layer opening exposing the top surface of the channel pillar 204; The channel pillar 204 exposed by the layer opening is subjected to an ion implantation process, and the source doping layer 212 is formed on the top of the channel pillar 204 .

In this embodiment, the lateral double-diffusion field effect transistor formed is P-type, and the implanted ions in the source doping layer 212 are also P-type ions; in other embodiments, when the lateral double-diffusion field effect transistor is formed, When it is N-type, the first ions in the initial drain doped layer are N-type.

Referring to FIG. 14 , after forming the source doping layer 212 , a conductive structure is formed in the dielectric layer 211 .

The conductive structure includes: a first conductive plug 213 connected to the source doped layer 211; a second conductive plug 214 connected to the gate structure 210; and a drain dopant of the third region III. Layer 207 is connected to a third conductive plug 215 .

Through the drift region 201 located in the second region II of the substrate 200, the drift region 201 extends to the first region I and the third region III of the substrate 200, and is located in the first region I and the third region III. The drain doped layer 207 on the substrate 200 in the third region III, the drain doped layer 207 in the first region I has a channel pillar 204, and a gate structure located on the sidewall of the channel pillar 204. 210, and the formed source doped layer 212. The conductive structure is used to enable the gate structure 210, the source doped layer 212 and the drain doped layer 207 to form a conductive path when turned on, so that the gate structure 210, the source doped layer 212 and the drain doped layer 207 can form a conductive path based on the trench perpendicular to the surface of the substrate 200. The track pillars 204 form a lateral double diffusion field effect tube. On the one hand, since the gate structure 210 completely surrounds the sidewall surface of the channel pillar 204, the area of the channel region is effectively increased, thereby increasing the operating current of the lateral double diffusion field effect transistor; on the other hand, the The channel pillars 204 are arranged perpendicular to the surface direction of the substrate 200 and occupy a small area, which can effectively reduce the design size of the final semiconductor structure and increase the device density in the semiconductor structure.

In this embodiment, the first conductive plug 213 , the second conductive plug 214 and the third conductive plug 215 are made of copper; in other embodiments, the first conductive plug 214 and the third conductive plug 215 are made of copper. The material of the plug and the third conductive plug may also include one or more of cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride and ruthenium.

Correspondingly, embodiments of the present invention also provide a semiconductor structure. Please continue to refer to Figure 11. The semiconductor structure includes: a substrate, and the substrate includes a first region, a second region and a third region. The second region is located between the first region and the third region; a drift region is located in the second region of the substrate, and the drift region is toward the first region and the third region of the substrate. Extension; a drain doped layer located on the first and third regions of the substrate, the drain doped layer being doped with first ions; a channel located on the drain doped layer of the first region Pillar; a gate structure located on the sidewall surface of the channel pillar.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims (18)

1. A semiconductor structure, comprising:

a substrate comprising a first region, a second region, and a third region, the second region being located between the first region and the third region, and the second region being adjacent to the first region and the third region, respectively;

a drift region located in the second region of the substrate, the drift region extending into the first and third regions of the substrate;

the leakage doping layers are positioned on the first region and the third region of the substrate, and first ions are doped in the leakage doping layers;

a channel pillar located on the drain doped layer of the first region;

a source doped layer positioned at the top of the channel pillar;

the grid structure is positioned on the surface of the side wall of the channel column;

the dielectric layer is positioned on the substrate and covers the grid structure, the channel column and the source doping layer;

a conductive structure within the dielectric layer, the conductive structure comprising: a first conductive plug connected to the source doped layer; a second conductive plug connected to the gate structure; and a third conductive plug connected with the drain doped layer of the third region.

2. The semiconductor structure of claim 1, further comprising: and the second ion is doped in the drift region, and the conductivity type of the second ion is the same as that of the first ion.

3. The semiconductor structure of claim 2, wherein the first ions comprise N-type ions or P-type ions.

4. The semiconductor structure of claim 3, wherein when said first ion is an N-type ion, said second ion comprises a phosphorus ion or an arsenic ion, saidThe implantation dose of the second ion is 1E18atm/cm ³ ～3E20atm/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the The implantation energy of the second ions is 10 keV-50 keV.

5. The semiconductor structure of claim 3, wherein when the first ion is a P-type ion, the second ion comprises a boron ion or an indium ion, and the implantation dose of the second ion is 2E18atm/cm ³ ～5E20atm/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the The implantation energy of the second ions is 5 keV-45 keV.

6. The semiconductor structure of claim 1, further comprising: and the isolation structure is positioned on the substrate, covers the drift region and part of the side wall surface of the channel column, and has a top surface lower than the top surface of the channel column.

7. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a first region, a second region and a third region, the second region is positioned between the first region and the third region, and the second region is adjacent to the first region and the third region respectively;

forming a drift region in the substrate of the second region, wherein the drift region extends into the first region and the third region of the substrate;

forming a drain doping layer on the first region and the third region, wherein first ions are doped in the drain doping layer;

forming a channel column on the drain doped layer of the first region;

forming a grid structure on the side wall surface of the channel column;

forming a dielectric layer on the substrate after forming a gate structure on the side wall surface of the channel column, wherein the dielectric layer covers the gate structure and the channel column;

after the dielectric layer is formed, forming a source doping layer on the top of the channel column;

after forming the source doped layer, forming a conductive structure within the dielectric layer, the conductive structure comprising: a first conductive plug connected to the source doped layer; a second conductive plug connected to the gate structure; and a third conductive plug connected with the drain doped layer of the third region.

8. The method of forming a semiconductor structure of claim 7, wherein forming a drain doped layer over the first region and the third region comprises: forming an initial drain doping layer on the substrate; forming a mask layer on the initial drain doping layer; forming a patterned layer on the mask layer, wherein the patterned layer exposes a part of the top surface of the mask layer; etching the mask layer and the initial drain doping layer on the second region substrate by taking the patterned layer as a mask until the top surface of the second region substrate is exposed, and forming the drain doping layers on the first region and the third region; and etching to remove the patterning layer and the mask layer after the drain doped layer is formed on the first region and the third region.

9. The method of forming a semiconductor structure of claim 8, further comprising, prior to forming the mask layer: and forming a protection side wall on the surface of the side wall of the channel column.

10. The method of claim 9, wherein said protective sidewall is removed after etching to remove said patterned layer and said mask layer.

11. The method for forming a semiconductor structure according to claim 9, wherein the method for forming a protective sidewall comprises: forming a protective side wall material layer on the side wall surface and the top surface of the channel column and the top surface of the initial drain doping layer; and etching the protective side wall material layer until the top surface of the channel column and the top surface of the initial drain doping layer are exposed, and forming the protective side wall on the side wall surface of the channel column.

12. The method of claim 9, wherein said sidewall-protecting material comprises silicon nitride.

13. The method of claim 11, wherein said forming of said protective sidewall material layer comprises an atomic layer deposition process.

14. The method of forming a semiconductor structure of claim 8, further comprising, prior to etching away the patterned layer and the mask layer: and carrying out ion implantation in the second region of the substrate, wherein second ions are doped in the drift region, and the conductivity type of the second ions is the same as that of the first ions.

15. The method of forming a semiconductor structure of claim 14, wherein the first ions comprise N-type ions or P-type ions.

16. The method of forming a semiconductor structure according to claim 15, wherein when the first ion is an N-type ion, the second ion includes a phosphorus ion or an arsenic ion, and an implantation dose of the second ion is 1E18atm/cm ³ ～3E20atm/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the The implantation energy of the second ions is 10 keV-50 keV.

17. The method of forming a semiconductor structure according to claim 15, wherein when the first ion is a P-type ion, the second ion includes boron ion or indium ion, and an implantation dose of the second ion is 2E18atm/cm ³ ～5E20atm/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the The implantation energy of the second ions is 5 keV-45 keV.

18. The method of forming a semiconductor structure of claim 7, further comprising, prior to forming a gate structure on a sidewall surface of the channel pillar: an isolation structure is formed on the substrate, the isolation structure covers the drift region and part of the side wall surface of the channel column, and the top surface of the isolation structure is lower than the top surface of the channel column.