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CN111725071B - Silicon-based junction accumulation layer and buffer layer lateral double-diffusion field effect transistor and manufacturing method thereof - Google Patents

Silicon-based junction accumulation layer and buffer layer lateral double-diffusion field effect transistor and manufacturing method thereof Download PDF

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CN111725071B
CN111725071B CN202010699370.4A CN202010699370A CN111725071B CN 111725071 B CN111725071 B CN 111725071B CN 202010699370 A CN202010699370 A CN 202010699370A CN 111725071 B CN111725071 B CN 111725071B
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CN111725071A (en
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段宝兴
王彦东
杨银堂
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Xidian University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure

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Abstract

本发明公开了一种硅基结型积累层和缓冲层横向双扩散场效应晶体管及其制作方法。该器件设置积累介质层，覆盖P型基区与N+漏区之间的区域；在积累介质层上形成外延层，在外延层的左侧端部、右侧端部分别通过离子注入形成两处P型区，并在所述外延层中邻接右端P型区通过离子注入形成N+区；在栅介质层表面形成栅极，栅极与左端P型区邻接；在N+漏区表面的右端区域形成漏极，漏极与右端P型区邻接。本发明通过结型积累层结构可产生电子，使得导通电阻不依赖于掺杂浓度，从而大幅度降低器件的导通电阻。通过缓冲层调制漂移区的电场，使电场分布更均匀，可大幅度提高器件的击穿电压。

Figure 202010699370

The invention discloses a lateral double diffusion field effect transistor of a silicon-based junction type accumulation layer and a buffer layer and a manufacturing method thereof. The device is provided with an accumulation dielectric layer, covering the area between the P-type base region and the N + drain region; an epitaxial layer is formed on the accumulation dielectric layer, and the left and right ends of the epitaxial layer are formed by ion implantation. A P-type region is formed at the epitaxial layer, and an N + region is formed by ion implantation adjacent to the right-end P-type region in the epitaxial layer; a gate is formed on the surface of the gate dielectric layer, and the gate is adjacent to the left-end P-type region; on the surface of the N + drain region The right end region forms a drain which is adjacent to the right end P-type region. The invention can generate electrons through the junction accumulation layer structure, so that the on-resistance does not depend on the doping concentration, thereby greatly reducing the on-resistance of the device. The electric field of the drift region is modulated by the buffer layer, so that the electric field distribution is more uniform, and the breakdown voltage of the device can be greatly improved.

Figure 202010699370

Description

Silicon-based junction accumulation layer and buffer layer lateral double-diffusion field effect transistor and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a transverse double-diffusion field effect transistor.
Background
Lateral Double-diffused metal oxide semiconductor field effect transistors (LDMOS) have the advantages of easy integration, good thermal stability, better frequency, low power consumption, high switching speed, and the like, and become the core of intelligent power circuits and high-voltage devices. With the increasing market demand for portable power management and automotive electronics, LDMOS has received increased attention.
In the design process of the lateral device, the condition of weakening the Surface electric Field (RESURF) technology is required to be satisfied, so that the breakdown point of the device is transferred from the Surface to the body. However, as the length of the drift region of the device increases, the breakdown voltage of the device is mainly limited by the internal longitudinal voltage endurance capability, i.e. the breakdown voltage of the device gradually tends to saturate as the length of the drift region increases due to the voltage saturation effect of the lateral power device. In addition, with the improvement of the withstand voltage level, the on-resistance is greatly increased, and the application of the LDMOS device in the high-voltage field is limited to a great extent.
Disclosure of Invention
The invention provides a silicon-based junction accumulation layer and buffer layer transverse double-diffusion field effect transistor, which can obtain better relation between breakdown voltage and specific on-resistance, greatly improve the breakdown voltage of a device and reduce the on-resistance.
The technical scheme of the invention is as follows:
a lateral double diffused field effect transistor with a silicon junction accumulation layer and a buffer layer, comprising:
the back surface of the P-type silicon substrate is provided with a substrate electrode;
a P-type base region formed at the left end region of the upper part of the P-type silicon substrate, a corresponding channel and an N are formed in the P-type base region+Source region and P+A source region;
an N-type buffer layer is formed on the right end region of the upper portion of the P-type silicon substrate, and an interval exists between the N-type buffer layer and the P-type base region; n is formed in the upper right end region of the N-type buffer layer+A drain region;
source electrode at P+Source region and N+A source region surface;
a gate dielectric layer covering N+A channel surface region on the right side of the source region;
an accumulation dielectric layer covering the P-type base region and N+A region between the drain regions;
the epitaxial layer covers the accumulation medium layer;
forming a first P-type region and a second P-type region at the left side end part and the right side end part of the epitaxial layer by ion implantation respectively, and forming N adjacent to the second P-type region in the epitaxial layer by ion implantation+A zone; said N is+The left end of the region does not exceed N+The boundary corresponding to the left end of the drain region;
forming a grid electrode on the surface of the grid dielectric layer, wherein the right side of the grid electrode is adjacent to the left side of the first P-type region;
in N+And a drain electrode is formed in the right end area of the surface of the drain region, and the left side of the drain electrode is adjacent to the second P-type region and the right side of the accumulation dielectric layer.
The epitaxial layer may beIs N-type, P-type, lightly doped or undoped, and has a concentration lower than that of N+The doping concentration of the region. The material of the epitaxial layer may be a silicon material or polysilicon.
Optionally, the doping concentration of the P-type silicon substrate is 1 × 1014cm-3～1×1015cm-3The doping concentration of the N-type buffer layer is 5 multiplied by 1014cm-3～5×1015cm-3。
Optionally, the length of the N-type buffer layer is 1/2-1/3 of the whole device, and the depth of the N-type buffer layer is 3-20 microns.
Optionally, the material of the accumulation dielectric layer is silicon dioxide or a high-K material.
Optionally, the thickness of the accumulation dielectric layer is 0.05-0.2 microns.
Optionally, the doping concentration of the epitaxial layer is 1 × 1014cm-3～1×1015cm-3。
Optionally, the thickness of the epitaxial layer is 1-3 microns.
Optionally, the doping concentration of the first P-type region and the second P-type region is 1 × 1017cm-3～1×1019cm-3。
Optionally, the N+The doping concentration of the region is 1 × 1017cm-3～1×1019cm-3。
The manufacturing method of the silicon-based junction accumulation layer and buffer layer lateral double-diffusion field effect transistor is characterized by comprising the following steps of:
1) taking a P-type silicon substrate and forming a substrate electrode;
2) formation of N by ion implantation and diffusion+Source region, P+Source region, P-type base region, N-type buffer layer and N+A drain region;
3) selecting an epitaxial layer material of 1-3 microns, growing an accumulated oxide layer on the bottom surface of the epitaxial layer material, and connecting the epitaxial layer material with the P-type silicon substrate and the N-type buffer layer through a bonding process; forming a first P-type region, a second P-type region and an N on the epitaxial layer by ion implantation+A zone;
4) forming a gate dielectric layer above the channel, and depositing metal to form a gate so that the metal is connected with the first P-type region in the epitaxial layer;
5) in N+Depositing metal above the drain region to form a drain electrode, so that the metal is connected with a second P-type region in the epitaxial layer;
6) and forming a passivation layer on the surface of the device.
The technical scheme of the invention has the following beneficial effects:
from the source of contradiction, the idea of separating the voltage-resistant region from the conducting region is provided, and by eliminating the dependence relationship of the conducting resistance on the doping concentration, a better relationship between the breakdown voltage and the specific conducting resistance can be obtained, so that the breakdown voltage of the device is greatly improved, and the conducting resistance is reduced.
The electric field of the drift region is modulated by the buffer layer, so that the electric field distribution is more uniform, and the breakdown voltage of the device can be greatly improved; meanwhile, electrons are generated through the junction accumulation layer structure, the conductivity of the substrate is modulated, the specific on-resistance of the device is greatly reduced, and the dependency of conduction on doping concentration is eliminated; the limitation of RESURF condition in a lateral device is broken through, so that the breakdown voltage can be greatly high by reducing the doping concentration between a grid electrode and a drain electrode.
In the invention, two P-type regions are arranged, so that metal and semiconductor form good ohmic contact.
Since electrons are formed below the oxide layer while an equal number of holes are formed above the oxide layer when the device is turned on, N is set+The region blocks hole current in the epitaxial layer (10) above the oxide layer.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of the present invention.
Fig. 2 is a schematic diagram of the working principle of the present invention.
FIG. 3 is a comparison of the breakdown voltage of an exemplary LDMOS device of the present invention.
FIG. 4 is a comparison of the on-resistance of an exemplary LDMOS device of the present invention with that of a conventional LDMOS device.
The reference numbers illustrate:
a 1-P type silicon substrate; 2-base region; 3-P+A source region; a 4-source electrode; 5-N+A source region; 6-a gate dielectric layer; 7-a grid; 8-a first P-type region; 9-accumulating a dielectric layer; 10-an epitaxial layer; 11-N+A zone; 12-a second P-type region; 13-a drain electrode; 14-a drain region; 15-N type buffer layer; 16-substrate electrode.
Detailed Description
The present invention will be further described in detail by way of examples with reference to the accompanying drawings.
As shown in fig. 1, a lateral double diffused field effect transistor of a silicon-based junction accumulation layer and a buffer layer comprises:
a P-type silicon substrate 1 having a substrate electrode 16 formed on the back surface thereof; typical values for the P-type silicon substrate doping concentration are 1 x 1014cm-3～1×1015cm-3；
A P-type base region 2 formed on the P-type silicon substrate, the concentration of the base region being determined by the threshold voltage, a corresponding channel being formed in the base region and an N+Source regions 5 and P+ A source region 3;
n-type buffer layer 15 formed on P-type silicon substrate and N+ A drain region 14, wherein the doping concentration and the depth of the N-type buffer layer are determined by the withstand voltage of the device; typical doping concentration of the N-type buffer layer is 5 × 1014cm-3～5×1015cm-3(ii) a The length of the N-type buffer layer is 1/2-1/3 of the whole device, and the typical value of the depth is 3-20 microns;
at P+Source region and N+ A source electrode 4 formed on the surface of the source region;
a gate dielectric layer 6 formed over the channel;
in the P-type base region and N+An accumulation dielectric layer 9 is formed on the surface of the device between the drain regions, the smaller the thickness of the dielectric layer is, the lower the on-resistance is, and the typical value of the thickness is 0.05-0.2 microns; the dielectric material is silicon dioxide or a high-K material;
an epitaxial layer 10 is formed above the accumulation medium layer, and the thickness of the epitaxial layer is 1-3 microns; typical doping concentration of the epitaxial layer 1 × 1014cm-3～1×1015cm-3The epitaxial layer is N type (or P type);
a first P-type region 8, a second P-type region 12 and N formed by implantation are formed on the epitaxial layer, respectively+A region 11; typical doping concentrations of the first and second P-type regions are 1 x 1017cm-3～1×1019cm-3，N+Typical doping concentration of the region is 1 x 1017cm-3～1×1019cm-3；
A grid 7 which covers the grid oxide layer and is connected with a first P-type region 8 in the epitaxial layer;
and the drain electrode 13 is positioned above the drain region and is connected with the second P type region 12 in the epitaxial layer.
Both breakdown voltage and specific on-resistance in conventional lateral double-diffused transistors exhibit a contradictory relationship, since a high breakdown voltage requires a low doping concentration, which leads to a high on-resistance. The invention starts from a contradiction source, proposes the idea of separating a breakdown region from a conduction region, and as shown in fig. 2, electrons can be generated through a junction accumulation layer structure, so that the conduction resistance does not depend on the doping concentration, and the conduction resistance of the device is greatly reduced; meanwhile, the electric field of the drift region is modulated by the buffer layer, so that the electric field distribution is more uniform, and the breakdown voltage of the device can be greatly improved.
The device can be prepared by the following steps:
1) taking a P-type silicon substrate and forming a substrate electrode;
2) formation of N by ion implantation and diffusion+Source region, P+Source region, P-type base region, N-type buffer layer and N+A drain region;
3) selecting an epitaxial layer material of 1-3 microns, growing an accumulated oxide layer on the bottom surface of the epitaxial layer material, and connecting the epitaxial layer material with the P-type silicon substrate and the N-type buffer layer through a bonding process; forming a first P-type region, a second P-type region and an N on the epitaxial layer by ion implantation+A zone;
4) forming a gate dielectric layer above the channel, and depositing metal to form a gate so that the metal is connected with the first P-type region in the epitaxial layer;
5) in N+Depositing a metal over the drain region to form a drain electrode, such that the metal is in contact withThe second P-type regions in the epitaxial layer are connected;
6) and forming a passivation layer on the surface of the device.
Through simulation tests, for the N-channel LDMOS, when the length of the drift region is 20 μm: as shown in fig. 3, the breakdown voltage of the common LDMOS is only about 230V, but with the structure of the present invention, the breakdown voltage of the device can be increased to about 460V, which is increased by 100%; as shown in FIG. 4, the specific on-resistance of a conventional LDMOS is 30m Ω. cm2On the other hand, the specific on-resistance of the device can be reduced to 6m omega cm by adopting the structure of the invention2The decrease is 80%.
Of course, the LDMOS of the present invention may also be a P-channel LDMOS, and the structure thereof is equivalent to that of an N-channel LDMOS, which is not described herein again.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions also fall into the protection scope of the present invention.

Claims (10)

1.一种硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于，包括：1. a silicon-based junction type accumulation layer and a buffer layer lateral double-diffusion field effect transistor, is characterized in that, comprising: P型硅衬底(1)，P型硅衬底的背面设置有衬底电极(16)；A P-type silicon substrate (1), the backside of the P-type silicon substrate is provided with a substrate electrode (16); 在P型硅衬底上部左端区域形成的P型基区(2)，在P型基区中形成相应的沟道以及N+源区(5)和P+源区(3)；A P-type base region (2) is formed in the upper left end region of the P-type silicon substrate, and a corresponding channel and an N + source region (5) and a P + source region (3) are formed in the P-type base region; 在P型硅衬底上部右端区域形成的N型缓冲层(15)，所述N型缓冲层(15)与P型基区(2)存在间隔；N型缓冲层(15)的上部右端区域形成N+漏区(14)；The N-type buffer layer (15) is formed in the upper right end region of the P-type silicon substrate, the N-type buffer layer (15) is spaced from the P-type base region (2); the upper right end region of the N-type buffer layer (15) forming an N + drain region (14); 源极(4 )，位于P+源区(3)和N+源区(5)表面；a source electrode (4), located on the surfaces of the P + source region (3) and the N + source region (5); 栅介质层(6)，覆盖N+源区(5)右侧的沟道表面区域；a gate dielectric layer (6) covering the channel surface region on the right side of the N + source region (5); 积累介质层(9)，覆盖P型基区(2)与N+漏区(14)之间的区域；an accumulation dielectric layer (9) covering the area between the P-type base region (2) and the N + drain region (14); 外延层(10)，覆盖所述积累介质层(9)；an epitaxial layer (10) covering the accumulation medium layer (9); 在所述外延层(10)的左侧端部、右侧端部分别通过离子注入形成第一P型区(8)和第二P型区(12)，并在所述外延层中邻接所述第二P型区(12)通过离子注入形成N+区(11)；所述N+区(11)的左端不超出N+漏区(14)左端对应的边界；A first P-type region (8) and a second P-type region (12) are formed on the left end portion and the right end portion of the epitaxial layer (10) by ion implantation, respectively, and are adjacent to the epitaxial layer. The second P-type region (12) forms an N + region (11) by ion implantation; the left end of the N + region (11) does not exceed the boundary corresponding to the left end of the N + drain region (14); 在栅介质层(6)表面形成栅极(7)，栅极(7)的右侧邻接第一P型区(8)的左侧；A gate electrode (7) is formed on the surface of the gate dielectric layer (6), and the right side of the gate electrode (7) is adjacent to the left side of the first P-type region (8); 在N+漏区(14)表面的右端区域形成漏极(13)，漏极(13)的左侧邻接第二P型区(12)以及积累介质层(9)的右侧。A drain electrode (13) is formed at the right end region of the surface of the N + drain region (14), and the left side of the drain electrode (13) is adjacent to the second P-type region (12) and the right side of the accumulation dielectric layer (9). 2.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述P型硅衬底(1)的掺杂浓度为1×1014cm-3～1×1015cm-3，所述N型缓冲层(15)的掺杂浓度为5×1014cm-3～5×1015cm-3。2. The silicon-based junction-type accumulation layer and buffer layer lateral double-diffusion field effect transistor according to claim 1, characterized in that: the doping concentration of the P-type silicon substrate (1) is 1×10 14 cm − 3 to 1×10 15 cm −3 , and the doping concentration of the N-type buffer layer (15) is 5×10 14 cm −3 to 5×10 15 cm −3 . 3.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述N型缓冲层(15)的长度为整个器件的1/2～1/3，深度为3-20微米。3. The silicon-based junction-type accumulation layer and buffer layer lateral double-diffused field effect transistor according to claim 1, characterized in that: the length of the N-type buffer layer (15) is 1/2-1/2 of the entire device 3. The depth is 3-20 microns. 4.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述积累介质层(9)的材料为二氧化硅或高K材料。4. The silicon-based junction type accumulation layer and buffer layer lateral double-diffusion field effect transistor according to claim 1, wherein the material of the accumulation medium layer (9) is silicon dioxide or high-K material. 5.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述积累介质层(9)的厚度为0.05-0.2微米。5. The silicon-based junction type accumulation layer and buffer layer lateral double diffusion field effect transistor according to claim 1, wherein the thickness of the accumulation medium layer (9) is 0.05-0.2 microns. 6.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述外延层(10)的掺杂浓度1×1014cm-3～1×1015cm-3。6. The silicon-based junction-type accumulation layer and buffer layer lateral double-diffusion field effect transistor according to claim 1, wherein the doping concentration of the epitaxial layer (10) is 1×10 14 cm −3 ˜1 × 10 15 cm -3 . 7.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述外延层(10)的厚度为1～3微米。7 . The lateral double diffusion field effect transistor of the silicon-based junction type accumulation layer and the buffer layer according to claim 1 , wherein the thickness of the epitaxial layer ( 10 ) is 1-3 μm. 8 . 8.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述第一P型区(8)和第二P型区(12)的掺杂浓度为1×1017cm-3～1×1019cm-3。8. The silicon-based junction-type accumulation layer and buffer layer lateral double-diffusion field effect transistor according to claim 1, characterized in that: the first P-type region (8) and the second P-type region (12) are doped with The impurity concentration is 1×10 17 cm -3 to 1×10 19 cm -3 . 9.根据权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述N+区(11)的掺杂浓度为1×1017cm-3～1×1019cm-3。9 . The silicon-based junction-type accumulation layer and buffer layer lateral double-diffusion field effect transistor according to claim 1 , wherein the doping concentration of the N + region ( 11 ) is 1×10 17 cm −3 ～ 1×10 19 cm -3 . 10.权利要求1所述的硅基结型积累层和缓冲层横向双扩散场效应晶体管的制作方法，其特征在于，包括以下步骤：10. The manufacturing method of the silicon-based junction type accumulation layer and the buffer layer lateral double-diffusion field effect transistor according to claim 1, characterized in that, comprising the following steps: 1)取P型硅衬底，并形成衬底电极；1) take a P-type silicon substrate, and form a substrate electrode; 2)通过离子注入和扩散形成N+源区、P+源区、P型基区、N型缓冲层和N+漏区；2) N + source region, P + source region, P-type base region, N-type buffer layer and N + drain region are formed by ion implantation and diffusion; 3)另选取1-3微米的外延层材料，在其底面生长积累氧化层，然后通过键合工艺与P型硅衬底以及N型缓冲层相连接；在外延层上通过离子注入形成第一P型区、第二P型区以及N+区；3) Another 1-3 micron epitaxial layer material is selected, and the accumulated oxide layer is grown on its bottom surface, and then connected to the P-type silicon substrate and the N-type buffer layer through a bonding process; the first epitaxial layer is formed by ion implantation. A P-type region, a second P-type region, and an N + region; 4)在沟道上方形成栅介质层，并淀积金属形成栅极，使得金属与外延层中的第一P型区相连接；4) forming a gate dielectric layer above the channel, and depositing metal to form a gate, so that the metal is connected to the first P-type region in the epitaxial layer; 5)在N+漏区上方淀积金属形成漏极，使得金属与外延层中的第二P型区相连接；5) depositing metal over the N + drain region to form a drain, so that the metal is connected to the second P-type region in the epitaxial layer; 6)在器件表面形成钝化层。6) A passivation layer is formed on the surface of the device.
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