CN113270476A - Lateral insulated gate bipolar transistor with electronic control gate region and Schottky anode and manufacturing method thereof - Google Patents
Lateral insulated gate bipolar transistor with electronic control gate region and Schottky anode and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a transverse insulated gate bipolar transistor with an electronic control gate region and a Schottky anode and a manufacturing method thereof. The device changes the design method of the polycrystalline silicon gate region and the drift region of the traditional LIGBT device, realizes the enhancement of the electron injection capability, keeps higher breakdown voltage and greatly shortens the conductance modulation region. The LIGBT device structurally uses a lightly doped P-type substrate region to replace a conventional N-type drift region, so that the limitation of the length of the drift region and the doping concentration on the withstand voltage of the device is weakened. Meanwhile, the electronic control gate region provides a main flow path for electrons from the cathode region to the anode region, and extremely low forward voltage drop and high saturation current are realized. In addition, the Schottky anode ensures hole injection in an on state and excessive electron extraction in an off state, can obviously inhibit the current tailing phenomenon in the turn-off of the device, reduces the turn-off loss of the device, and finally greatly relieves the contradiction between the forward characteristic and the switching characteristic of the device.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a transverse insulated gate bipolar transistor with an electronic control gate region and a Schottky anode.
Background
The power semiconductor device is a high-power electronic device mainly used for an electric energy conversion and control circuit of power equipment. With the rapid development of power electronic technology, power semiconductor devices have been widely used in modern industrial control and defense equipment. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is a power device that is very suitable for high voltage and high current applications because it combines the advantages of high input impedance and Bipolar current conduction, while the Lateral device is easy to integrate and its process is compatible with that of conventional complementary MOS devices. However, due to the large accumulation of non-equilibrium carriers caused by the bipolar conductivity, a severe current tailing phenomenon can be generated when the device is turned off, so that the turn-off loss is high, the working frequency is low, and the application range of the LIGBT device is limited.
Disclosure of Invention
In order to solve the problems that the existing LIGBT device generates serious current tailing phenomenon when being turned off, so that higher turn-off loss and lower working frequency are caused, the invention provides a transverse insulated gate bipolar transistor with an electronic control gate region and a Schottky anode and a manufacturing method thereof, aiming at reducing forward voltage drop and turn-off loss and finally greatly relieving the contradiction relation between the forward characteristic and the switching characteristic of the device.
The technical scheme of the invention is as follows:
the transverse insulated gate bipolar transistor comprises:
a P-type substrate of silicon material;
a lightly doped P-type well region formed in the upper left corner region of the P-type substrate, and an N-type buffer region formed in the upper right corner region;
a heavily doped P-type cathode region formed inside the P-type well region, and a heavily doped P-type anode region formed inside the N-type buffer region;
a heavily doped N-type cathode region formed inside the P-type cathode region;
forming a gate oxide layer of silicon dioxide material on the surface of the P-type substrate;
depositing a polysilicon material on the gate oxide layer, and doping to form an N-type gate region;
heavily doping the left side of the N-type grid region to form a left P-type contact region;
heavily doping the right side of the N-type gate region to form an N-type barrier region and a right P-type contact region, wherein a gap is formed between the right P-type contact region and the heavily doped N-type barrier region;
etching positions on the gate oxide layer, corresponding to the P-type cathode region and the N-type cathode region, to form a first electrode contact hole, and depositing a metal material in the first contact hole to form a cathode;
etching positions on the gate oxide layer and corresponding to the P-type anode region and the N-type buffer region to form a second electrode contact hole, depositing a metal material in the second contact hole to form an anode, and contacting the anode with the P-type contact region;
and a metal material is deposited on the surface of the left P-type contact region to form a grid electrode.
The LIGBT device provided by the invention is mainly characterized in that:
the lightly doped P-type substrate is used for replacing a conventional N-type drift region, so that the limitation of the length of the drift region and the doping concentration on the withstand voltage of the device is weakened;
the anode region structure utilizes an N-type buffer region with relatively low doping concentration to form Schottky anode contact, and the anode is still in ohmic contact with a P-type anode region with relatively high doping concentration and a P-type contact region on the right side;
the gate oxide layer on the surface of the P-type substrate extends from the surface of the P-type trap area to the surface of the N-type buffer area, and the polycrystalline silicon material completely covers the gate oxide layer and forms an N-type gate area through doping;
an N-type blocking region is provided to prevent the formation of high gate leakage current.
Furthermore, the doping concentration of the P-type substrate ranges from 1.0 to 5.0 multiplied by 1014cm-3The doping concentration of the N-type drift region is 1 order of magnitude lower than that of a conventional N-type drift region;
further, the N-type buffer regionForm Schottky contact with the anode, and the doping concentration ranges from 1.0 to 5.0 multiplied by 1017cm-3The P-type anode region and the right P-type contact region form ohmic contact with the anode, and the doping concentration is not lower than 1.0 × 1019cm-3；
Furthermore, the doping concentration of the N-type gate region is related to the voltage withstanding capability of the device, and the value range of the doping concentration is 1.0-5.0 multiplied by 1015cm-3；
Further, the N-type blocking region suppresses excessive gate leakage current and has a doping concentration of not less than 1.0 × 1018cm-3。
The method for manufacturing the transverse insulated gate bipolar transistor specifically comprises the following steps:
step 1: preparing a P-type silicon material as a P-type substrate;
step 2: forming a lightly doped P-type well region in the upper left corner region of the P-type substrate through an ion implantation process, then forming an N-type buffer region in the upper right corner region, and then performing a well pushing process at a high temperature of 900-1100 ℃, wherein the junction depth depends on the well pushing time finally, and the well pushing time is controlled to be 30-60 min;
and step 3: forming a heavily doped P-type cathode region inside the P-type well region by injecting boron ions, then forming a heavily doped P-type anode region inside the N-type buffer region, and performing rapid annealing treatment after the injection is finished;
and 4, step 4: forming a heavily doped N-type cathode region in the P-type cathode region by injecting phosphorus ions, and performing rapid annealing treatment after injection;
and 5: depositing a gate oxide layer made of silicon dioxide material on the upper surface of a P-type substrate, then depositing a polycrystalline silicon material to cover the gate oxide layer, and forming an N-type gate region by injecting and doping phosphorus ions;
step 6: forming a heavily doped left P-type contact region on the left side of the N-type gate region, forming a heavily doped N-type blocking region and a heavily doped right P-type contact region on the right side of the N-type gate region by an ion implantation process, wherein an interval is formed between the N-type blocking region and the right P-type contact region;
and 7: depositing a passivation layer on the surface of the gate oxide layer, etching to form a first electrode contact hole on the gate oxide layer at a position corresponding to the P-type cathode region and the N-type cathode region, and depositing a metal material in the first contact hole to form a cathode;
etching positions on the gate oxide layer, corresponding to the P-type anode region and the N-type buffer region, to form a second electrode contact hole, depositing a metal material in the second contact hole to form an anode, and ensuring that the anode is in contact with the right P-type contact region;
and 8: and depositing a metal material on the upper surface of the P-type contact region to form a grid electrode.
The technical scheme of the invention has the following beneficial effects:
the LIGBT device structure provided by the invention changes the design method of a polycrystalline silicon gate region and a drift region of the traditional LIGBT device, realizes the enhancement of electron injection capability, keeps higher breakdown voltage, and greatly shortens a conductance modulation region; meanwhile, an electronic control grid region structure is formed by a polycrystalline silicon doped region above the grid oxide layer, wherein the N-type grid region and the P-type ohmic contact regions on two sides maintain uniform grid voltage, a main flow path of electrons from a cathode region electrode to an anode region is provided, the function of adjusting an electric field in a P-type substrate is achieved, and finally extremely low forward voltage drop, high saturation current and high breakdown voltage are achieved, and the N-type blocking region avoids too high grid leakage. In addition, the N-type buffer region structure formed by the anode metal Schottky contact ensures hole injection in an on state and excessive electron extraction in an off state, can obviously inhibit the current trailing phenomenon when the device is turned off, and reduces the turn-off loss of the device. According to the numerical simulation result, under the same breakdown voltage condition, the forward voltage drop and turn-off loss of the LIGBT device provided by the invention are respectively 28.9% lower and 97.2% lower than those of the traditional LIGBT device, and the LIGBT device has shorter device length.
The device provided by the invention fully exerts the advantages of inversion layer electron accumulation and short-circuit anode structure below the grid, can obviously improve the conductivity modulation capability of the drift region, inhibits the current tailing phenomenon when the device is turned off, reduces the turn-off loss of the device, and finally greatly relieves the contradiction relation between the forward characteristic and the switching characteristic of the device.
Drawings
Fig. 1 is a schematic structural view of the present invention.
Wherein, the 1-P type well region; a 2-N type buffer region; a 3-P type cathode region; a 4-P type anode region; a 5-N type cathode region; 6-gate oxide layer; a 7-N type gate region; 8-left P-type contact region; 9-right P-type contact region; a 10-N type blocking region; 11-a cathode; 12-an anode; 13-a gate; 801-P type substrate.
Detailed Description
The present invention will now be described with reference to the drawings, in which an N-channel LIGBT is used as an example, and the described embodiments are only some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, the lateral insulated gate bipolar transistor with an electronic control gate region and a schottky anode provided in this embodiment specifically includes:
a P-type substrate 801 of silicon material; the LIGBT device uses the P-type substrate 801 to replace a conventional N-type drift region, wherein the doping concentration of the P-type substrate 801 is low and the value range is 1.0-5.0 multiplied by 1014cm-3The doping concentration of the N-type drift region is 1 order of magnitude lower than that of a conventional N-type drift region;
forming a lightly doped P-type well region 1 in the upper left corner region of the P-type substrate 801 and forming a lightly doped N-type buffer region 2 in the upper right corner region; the doping concentration of the N-type buffer region (2) ranges from 1.0 to 5.0 multiplied by 1017cm-3；
A heavily doped P-type cathode region 3 formed inside the P-type well region 1, and a heavily doped P-type anode region 4 formed inside the N-type buffer region 2;
a heavily doped N-type cathode region 5 formed inside the P-type cathode region 3;
forming a gate oxide layer 6 made of silicon dioxide material on the surface of a P-type substrate 801;
depositing a polysilicon material on the gate oxide layer 6, and doping to form an N-type gate region 7; specifically, the polycrystalline silicon material covers the area of the gate oxide layer 6 extending from the P-type well region 1 to part of the N-type buffer region 2, and forms an N-type gate region 7 through doping, wherein the doping concentration of the N-type gate region 7 is related to the voltage resistance of the device, and the value range is 1.0-5.0 multiplied by 1015cm-3；
Forming a heavily doped left P-type contact region 8 on the left side of the N-type gate region 7;
forming a heavily doped N-type barrier region 10 and a heavily doped right P-type contact region 9 on the right side of the N-type gate region 7, wherein an interval is formed between the right P-type contact region 9 and the heavily doped N-type barrier region 10;
the left side P type contact region 8 and the right side P type contact region 9 are heavily doped to form an ohmic contact region, and the doping concentration is not lower than 1.0 multiplied by 1019cm-3(ii) a The N-type blocking region 10 is used to prevent the formation of high gate leakage current, and its doping concentration is not less than 1.0 × 1018cm-3。
Etching positions on the gate oxide layer 6 and corresponding to the P-type cathode region 3 and the N-type cathode region 5 to form a first electrode contact hole, and depositing a metal material in the first contact hole to form a cathode 11;
etching to form a second electrode contact hole on the gate oxide layer 6 and corresponding to the positions of the P-type anode region 4 and the N-type buffer region 2, depositing a metal material in the second contact hole to form an anode 12, and contacting the anode 12 with the right P-type contact region 9 (because the right P-type contact region 9 is heavily doped, ohmic contact is formed between the anode 12 and the right P-type contact region 9); because the N-type buffer region 2 is lightly doped, Schottky contact is formed between the anode 12 and the N-type buffer region 2;
a metal material is deposited on the upper surface of the left P-type contact region 8 to form a gate 13.
Taking an N-channel LIGBT as an example, the method can be specifically prepared by the following steps:
1. preparing a P-type silicon material as a P-type substrate 801;
2. forming a lightly doped P-type well region 1 in the upper left corner region of a P-type substrate 801 through an ion implantation process, then forming an N-type buffer region 2 in the upper right corner region, and then performing a well pushing process under a high temperature condition of about 1000 ℃ (generally controlled at 900-1100 ℃), wherein the junction depth depends on the well pushing time which is generally controlled at 30-60 min;
3. forming a heavily doped P-type cathode region 3 inside the P-type well region 1 by injecting boron ions, then forming a heavily doped P-type anode region 4 inside the N-type buffer region 2, and performing rapid annealing treatment after the injection is finished;
4. forming a heavily doped N-type cathode region 5 in the P-type cathode region 3 by injecting phosphorus ions, and performing rapid annealing treatment after the injection is finished;
5. depositing a gate oxide layer 6 made of silicon dioxide on the upper surface of a P-type substrate 801, then depositing a polysilicon material to cover the gate oxide layer 6, and forming an N-type gate region 7 by phosphorus ion implantation doping;
6. through an ion implantation process, a heavily doped left P-type contact region 8 is formed on the left side of an N-type gate region 7, a heavily doped N-type blocking region 10 and a heavily doped right P-type contact region 9 are formed on the right side of the N-type gate region 7, and an interval is formed between the N-type blocking region 10 and the right P-type contact region 9;
7. depositing a passivation layer on the surface of the gate oxide layer 6, etching to form a first electrode contact hole on the gate oxide layer 6 at a position corresponding to the P-type cathode region 3 and the N-type cathode region 5, and depositing a metal material in the first contact hole to form a cathode 11;
etching positions on the gate oxide layer 6, corresponding to the P-type anode region 4 and the N-type buffer region 2 to form a second electrode contact hole, depositing a metal material in the second contact hole to form an anode 12, and ensuring that the anode 12 is in contact with the right P-type contact region 9;
8. and depositing a metal material on the upper surface of the left P-type contact region 8 to form a grid (13).
The LIGBT device in the present invention may also be a P-type channel, and its structure is equivalent to that of an N-channel LIGBT device, and it is also considered to belong to the protection scope of the claims of the present application, and is not described herein again.
The materials used in the present invention are mainly silicon semiconductor materials, and should be understood in a broad sense, that is, LIGBT devices formed by semiconductor materials of elements such as germanium, or wide band gap semiconductor materials such as silicon carbide, gallium nitride, etc. are equivalent to LIGBT devices described in the present invention, and should also be considered as belonging to the protection scope of the claims of the present application, and are not described herein again.
The LIGBT device in the present invention may also use SOI (silicon on insulator) substrate, and its structure is equivalent to that of the LIGBT device with bulk silicon substrate, and should also be considered as falling within the protection scope of the claims of the present application, and will not be described herein again.
Claims (7)
1. A lateral insulated gate bipolar transistor having an electronically controlled gate region and a Schottky anode, the structure comprising:
a P-type substrate (801) of silicon material;
forming a lightly doped P-type well region (1) in the upper left corner region of a P-type substrate (801), and forming a lightly doped N-type buffer region (2) in the upper right corner region;
a heavily doped P-type cathode region (3) formed inside the P-type well region (1), and a heavily doped P-type anode region (4) formed inside the N-type buffer region (2);
a heavily doped N-type cathode region (5) formed inside the P-type cathode region (3);
forming a gate oxide layer (6) made of silicon dioxide material on the surface of a P-type substrate (801);
depositing a polysilicon material on the gate oxide layer (6), and doping the formed N-type gate region (7);
forming a heavily doped left P-type contact region (8) on the left side of the N-type gate region (7);
forming a heavily doped N-type barrier region (10) and a heavily doped right P-type contact region (9) on the right side of the N-type gate region (7), wherein an interval is formed between the right P-type contact region (9) and the heavily doped N-type barrier region (10);
etching positions on the gate oxide layer (6) corresponding to the P-type cathode region (3) and the N-type cathode region (5) to form a first electrode contact hole, and depositing a metal material in the first contact hole to form a cathode (11);
etching positions on the gate oxide layer (6) corresponding to the P-type anode region (4) and the N-type buffer region (2) to form a second electrode contact hole, depositing a metal material in the second contact hole to form an anode (12), and contacting the anode (12) with the right P-type contact region (9);
and depositing a metal material on the upper surface of the left P-type contact region (8) to form a grid electrode (13).
2. The lateral insulated gate bipolar transistor of claim 1, wherein: the doping concentration of the P-type substrate (801) ranges from 1.0 to 5.0 multiplied by 1014cm-3。
3. The lateral insulated gate bipolar transistor of claim 1, wherein:
the doping concentration of the N-type buffer region (2) ranges from 1.0 to 5.0 multiplied by 1017cm-3。
4. The lateral insulated gate bipolar transistor of claim 1, wherein: the polycrystalline silicon material covers the area of the gate oxide layer (6) extending from the P-type well region (1) to part of the N-type buffer region (2), an N-type gate region (7) is formed by doping, the doping concentration of the N-type gate region (7) is related to the voltage resistance of the device, and the value range is 1.0-5.0 multiplied by 1015cm-3。
5. The lateral insulated gate bipolar transistor of claim 1, wherein:
the doping concentration of the left side P type contact region (8) and the right side P type contact region (9) is not less than 1.0 multiplied by 1019cm-3。
6. The lateral insulated gate bipolar transistor of claim 1, wherein: the doping concentration of the N-type blocking region (10) is not less than 1.0 multiplied by 1018cm-3。
7. A method of fabricating a lateral insulated gate bipolar transistor according to claim 1, comprising the steps of:
step 1: preparing a P-type silicon material as a P-type substrate (801);
step 2: forming a lightly doped P-type well region (1) in the upper left corner region of a P-type substrate (801) by an ion implantation process, then forming an N-type buffer region (2) in the upper right corner region, and then performing a well pushing process at a high temperature of 900-1100 ℃, wherein the junction depth finally depends on the well pushing time which is controlled within 30-60 min;
and step 3: forming a heavily doped P-type cathode region (3) inside the P-type well region (1) by injecting boron ions, then forming a heavily doped P-type anode region (4) inside the N-type buffer region (2), and performing rapid annealing treatment after the injection is finished;
and 4, step 4: forming a heavily doped N-type cathode region (5) in the P-type cathode region (3) by injecting phosphorus ions, and performing rapid annealing treatment after injection;
and 5: depositing a gate oxide layer (6) made of silicon dioxide material on the upper surface of a P-type substrate (801), then depositing polycrystalline silicon material to cover the gate oxide layer (6), and forming an N-type gate region (7) by phosphorus ion implantation doping;
step 6: through an ion implantation process, a heavily doped left P-type contact region (8) is formed on the left side of an N-type gate region (7), a heavily doped N-type blocking region (10) and a heavily doped right P-type contact region (9) are formed on the right side of the N-type gate region (7), and an interval is formed between the N-type blocking region (10) and the right P-type contact region (9);
and 7: depositing a passivation layer on the surface of the gate oxide layer (6), etching at positions corresponding to the P-type cathode region (3) and the N-type cathode region (5) on the gate oxide layer (6) to form a first electrode contact hole, and depositing a metal material in the first contact hole to form a cathode (11);
etching positions on the gate oxide layer (6) corresponding to the P-type anode region (4) and the N-type buffer region (2) to form a second electrode contact hole, depositing a metal material in the second contact hole to form an anode (12), and ensuring that the anode (12) is contacted with the right P-type contact region (9);
and 8: and depositing a metal material on the upper surface of the P-type contact region (8) to form a grid electrode (13).
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114709259A (en) * | 2022-03-28 | 2022-07-05 | 重庆大学 | Transverse insulated gate bipolar transistor with Schottky super barrier auxiliary gate integrated on anode |
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| CN111725071A (en) * | 2020-07-20 | 2020-09-29 | 西安电子科技大学 | A silicon-based junction-type accumulation layer and a buffer layer lateral double-diffusion field effect transistor and its manufacturing method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114709259A (en) * | 2022-03-28 | 2022-07-05 | 重庆大学 | Transverse insulated gate bipolar transistor with Schottky super barrier auxiliary gate integrated on anode |
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Application publication date: 20210817 |