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CN104183646A - SOI LDMOS device with extending gate structure - Google Patents

SOI LDMOS device with extending gate structure Download PDF

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Publication number
CN104183646A
CN104183646A CN201410439269.XA CN201410439269A CN104183646A CN 104183646 A CN104183646 A CN 104183646A CN 201410439269 A CN201410439269 A CN 201410439269A CN 104183646 A CN104183646 A CN 104183646A
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type semiconductor
region
conductivity type
gate
conductive type
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Inventor
罗小蓉
李鹏程
田瑞超
徐青
张彦辉
魏杰
石先龙
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/151—LDMOS having built-in components
    • H10D84/153—LDMOS having built-in components the built-in component being PN junction diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/657—Lateral DMOS [LDMOS] FETs having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/721—Insulated-gate field-effect transistors [IGFET] having a gate-to-body connection, i.e. bulk dynamic threshold voltage IGFET 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts

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Abstract

The invention discloses an SOI LDMOS device with an extending gate structure, and belongs to the technical field of semiconductor power devices. According to the SOI LDMOS device, the extending gate structure extending from a polysilicon gate to a drain electrode is introduced into the surface of a drift region of a conventional SOI LDMOS device. A PN junction which is reversely biased when the device is in the on state is introduced into the extending gate structure to reduce a leakage current. The extending gate structure is characterized in that on one hand, when the device is in the on state, a majority carrier accumulation layer is sensed on the portion, close to extending gate media, of the surface of the drift region, an ultralow resistance channel is provided for the on-state current, the specific on resistance of the device is accordingly and remarkably reduced, and the specific on resistance does not depend on the doping concentration of the drift region; on the other hand, when the device is in the off state, distribution of an electric field in the drift region is adjusted through the extending gate structure, and the voltage resistance of the device is accordingly improved. In addition, the vast majority of the on-state current flows through the low-resistance channel of the charge accumulation layer, temperature distribution of the SOI LDMOS device is accordingly even, and the SOI LDMOS device is stable.

Description

A kind of SOI LDMOS device with extension grid structure
Technical field
The invention belongs to semiconductor power device technology field, relate to transverse semiconductor power device, especially there is the high pressure, low-resistance lateral direction power SOI LDMOS (a Lateral Double-diffused Metal – Oxide – Semiconductor, the lateral double diffused metal-oxide-semiconductor) device that extend grid.
Background technology
The key parameter of power MOSFET is high pressure and low on-resistance.Because MOSFET belongs to monopole type device, the raising that it is withstand voltage is accompanied by the increase of drift region length and the reduction of drift region concentration; And for traditional high-voltage power MOSFET, its conducting resistance is mainly determined by its drift zone resistance.This just causes the conduction resistance R of device on, sp(conduction resistance=conducting resistance * device area) with respect to withstand voltage BV according to relational expression R on, sp∝ BV 2.5sharply increase, thereby cause power consumption sharply to increase, and the switching speed of device also decreases.
For conventional SOI LDMOS, the thickness of its drift region and size need meet RESURF principle and could under blocking state, exhaust completely, thereby reach the highest withstand voltage of device.If the drift region of device is thicker, the doping content of drift region is just lower, causes its conduction resistance larger, and RESURF effect a little less than, not remarkable for the electric field adjusting effect of drift region, therefore for the raising DeGrain of device withstand voltage.
Compare with conventional SOILDMOS, thin soi layer LDMOS is because active area longitudinal thickness is very little, so it is to ionize longitudinally path of integration just very short, thereby the longitudinal critical breakdown electric field in its body is significantly increased.In active area and dielectric buried layer interface, meet Gauss theorem, so the electric field strength of its dielectric buried layer can significantly improve, thereby improve the longitudinally withstand voltage of device.Thin soi layer LDMOS improves laterally withstand voltage for meeting RESURF principle, its drift region need to change doping, its doping content is from increasing gradually to close drain region near tagma, this can cause the distribution of resistance of its drift region inhomogeneous, thus wherein near near tagma because doping content exists larger resistance to produce focus and then affect stablizing of device work when the break-over of device compared with low.
S.Merchant in 1991, E.Arnold, H.Baumgart, S.Mukherjee, H.Pein, and R.Pinker confirms by drift region, (3a) linear doping can improve the puncture voltage (device architecture is as shown in Figure 1) of device with theoretical and experiment in article < < REALIZATION OF HIGH BREAKDOWN VOLTAGE (>700V) IN THIN SOI DEVICES > > (documents 1).Yet, drift region (3a) carried out to linear doping, and can to cause the distribution of resistance of drift region inhomogeneous (larger near channel region resistance, less near drain region resistance), therefore in the time of break-over of device can being caused, in the drift region near electronegative potential, form focus, thereby cause the temperature distributing disproportionation in device even, and then affect the stability of device.Theodore Letavic in 2000 and Mark Simpson utilize subregion change the drift region (3a) of doping and obtain high puncture voltage and low conducting resistance (device architecture as shown in Figure 2) at the upper grid field plate of introducing of top oxide layer (8) of stepped change in United States Patent (USP) < < LATERAL THIN-FILM SILICON-ON-INSULATOR (SOI) DEVICE HAVINGMULTIPLE ZONES IN THE DRIFT REGION > > (documents 2:US006023090A), but this structure is limited to the reduction of loss, and it is even effectively to alleviate drift region (3a) the inhomogeneous temperature distributing disproportionation causing that adulterates.Chinese patent < < middle proposition of power LDMOS device > > (documents 3:CN103268890A) with junction type field plate forms on surface, the drift region of device (3a) the junction type field plate (device architecture as shown in Figure 3) consisting of PN junction, utilize the PN junction Electric Field Distribution modulation device surface field in junction type field plate, make device surface Electric Field Distribution more evenly improve the withstand voltage of device, utilize junction type field plate to drift region (3a) simultaneously thus assisted depletion effect increase substantially drift region doped level and reduce conducting resistance.Yet what in this structure, the cold end of junction type field plate (9) connected is source S, what hot end (11) connected is drain D, so its conducting resistance still determines by drift region doping content, can not be reduced significantly.The conducting resistance of the above device all depends on drift region doping content strongly, but the doping content of drift region can not be too high, must meet RESURF principle could exhaust completely under blackout conditions, and the drift region of linear doping can cause drift region dead resistance skewness, thereby while causing device work, temperature distributing disproportionation is even.
Summary of the invention
Drift region dead resistance skewness can be caused in the drift region that the present invention is directed to the linear doping of existing horizontal SOI LDMOS device existence, thereby the even technical problem of temperature distributing disproportionation while causing device work, provides a kind of SOI LDMOS device that extends grid structure that has.Provided by the invention while thering is the SOI LDMOS device forward conduction that extends grid structure, thereby form electric charge accumulating layer in drift region, reduce conduction resistance; Meanwhile, because most electric currents are passed through by electric charge accumulating layer, and only have seldom the one part of current drift zone resistance of flowing through, so the Temperature Distribution of device is more even, device more stable work.
Technical solution of the present invention is as follows:
Have a SOI LDMOS device that extends grid structure, its structure cell, as shown in Fig. 4 a to Fig. 4 e, comprises longitudinal substrate layer 1, dielectric buried layer 2 and the first conductive type semiconductor active layer 3 from bottom to top.The first conductive type semiconductor active layer 3 one sides have the second conductive type semiconductor tagma 4, the second 4 surfaces, conductive type semiconductor tagma has the first adjacent conductive type semiconductor source region 6 and 5, the first conductive type semiconductor source regions 6, the second conductive type semiconductor body contact zone and 5 surfaces, the second conductive type semiconductor body contact zone and draws termination metallizing source S; The first conductive type semiconductor active layer 3 opposite sides have 7 surfaces, 7, the first conductive type semiconductor drain region, the first conductive type semiconductor drain region and draw termination metallization drain D; The first conductive type semiconductor active layer 3 between the second conductive type semiconductor tagma 4 and the first conductive type semiconductor drain region 7 forms the first conductive type semiconductor drift region 3a; The second 4 surfaces, conductive type semiconductor tagma, comprises that 6 surfaces, part the first conductive type semiconductor source region that are attached thereto have gate medium 8, and gate medium 8 surfaces have grid electric conducting material 13, and described grid electric conducting material 13 surfaces meet metallization gate electrode G.
Described gate medium 8 extends to the first conductive type semiconductor drain region 7 along device the first 3a surface, conductive type semiconductor drift region when covering 4 surface, the second conductive type semiconductor tagma, on the surface of gate medium 8 extensions, have the gate semiconductor of extension material, gate medium 8 extensions and extension gate semiconductor material form extension grid structure; Described extension gate semiconductor material is only followed successively by the second conductive type semiconductor gate contact zone 9, high resistance area 10, the first cut-off region, conductive type semiconductor field 11 and the second conductive type semiconductor that are linked in sequence and misses contact area 12 from playing near grid electric conducting material 13 near metallization drain D, wherein the second conductive type semiconductor gate contact zone 9 and metallization gate electrode G electrical connection, the second conductive type semiconductor is missed contact area 12 and metallization drain D is electric and joins.
In technique scheme, the preferred thickness of described the first conductive type semiconductor active layer (3) is less than 1 micron, and it is more effective to the Electric Field Modulated of drift region that device turn-offs withstand voltage state extension grid like this.
In technique scheme, described extension gate semiconductor material can adopt poly semiconductor or single-crystal semiconductor material.Wherein, adopt the device making technics of polycrystalline semiconductor material more simple.
The SOI LDMOS device with extension grid structure provided by the invention, compare with conventional SOI LDMOS device, thereby the voltage difference that when position of the present invention's close metallization drain D in extending grid structure is introduced in device ON state, back-biased PN junction bears between metallization grid G and metallization drain D reduces leakage current.This extends between grid structure and drift region and forms capacitance structure.Extend the cold end connection metal grid G of grid, hot end connection metal drain D.In the ON state of device, the voltage difference V between grid G and source S gSbe greater than the voltage difference V between drain D and source S dStime, in drift region, the surface of close gate medium extension can form the accumulation layer of majority carrier.The intensity of this majority carrier accumulation layer depends on alive size in grid G, irrelevant with drift region doping content with the thickness of gate medium extension.Along with alive raising in grid G, work as V gS>V tHafter (threshold voltage), the surface, tagma below polysilicon gate starts transoid, thereby forms the raceway groove of majority carrier.Therefore majority carrier will flow to drift region through raceway groove from source region, and flow into drain electrode by the accumulation layer on surface, drift region, thereby the passage of a super-low resistance is provided.Thereby so the electric current overwhelming majority in drift region by accumulation layer by significantly having reduced the conduction resistance of device; And, because the intensity of majority carrier accumulation layer depends on alive size in grid G, irrelevant with drift region doping content with the thickness of gate medium extension, majority carrier is almost uniformly distributed in the concentration of surface, drift region accumulation, therefore the resistance in this super-low resistance passage is uniformly distributed and causes the Temperature Distribution of device when work more even, and device operating state is more stable.
To sum up, the SOI LDMOS device with extension grid structure provided by the invention, when forward conduction, reduces conduction resistance thereby form electric charge accumulating layer in drift region.Because conduction resistance charge accumulated in drift region determines, the intensity of charge accumulated depends on alive size in grid G, irrelevant with drift region doping content with the thickness of gate medium extension, so just break the law that conventional power MOSFET conducting resistance depends on drift region doping content strongly, effectively alleviated the conduction resistance R of device on, spand the contradiction of 2.5 powers between withstand voltage BV.Meanwhile, because most electric currents are passed through by electric charge accumulating layer, and only have seldom the one part of current drift zone resistance of flowing through, so the Temperature Distribution of device is more even, device more stable work.In addition, extend the Electric Field Distribution of grid in can auxiliary adjustment drift region when device off state, thereby play a role to improving device withstand voltage.
Accompanying drawing explanation
Fig. 1 is the disclosed structural representation of documents 1.
Fig. 2 is the disclosed structural representation of documents 2.
Fig. 3 is the disclosed structural representation with the power LDMOS device of junction type field plate of documents 3.
Fig. 4 a is the structural representation of a kind of typical extension grid SOI LDMOS device that proposes of the present invention.
Fig. 4 b is the structural representation that a kind of drift region segmentation that the present invention proposes changes the extension grid SOI LDMOS device of doping.
Fig. 4 c is the structural representation that a kind of high resistance area that the present invention proposes becomes the extension grid SOI LDMOS device of conduction type doping.
Fig. 4 d is the structural representation that a kind of high resistance area segmentation that the present invention proposes changes the extension grid SOI LDMOS device of doping.
Fig. 4 e is that the present invention is applied to the body contact zone of thin active layer along the three-dimensional structure schematic diagram of the extension grid SOI LDMOS device of raceway groove arrangement.
Reference numeral:
1, substrate layer; 2, dielectric buried layer; 3, the first conductive type semiconductor active layer; 3a, the first conductive type semiconductor drift region; 4, the second conductive type semiconductor tagma; 5, the second conductive type semiconductor body contact zone; 6, the first conductive type semiconductor source region; 7, the first conductive type semiconductor drain region; 8, gate medium; 8a, gate medium extension; 9, the second conductive type semiconductor gate contact zone; 10, high resistance area; 10-1, the second conductive type semiconductor high resistance area; 10-2, the first conductive type semiconductor high resistance area; 11, the first cut-off region, conductive type semiconductor field; 12, the second conductive type semiconductor is missed contact area; 13, grid electric conducting material; S, metallizing source; G, metallization grid; D, metallization drain electrode.
Embodiment:
Below in conjunction with accompanying drawing and example, take and be applied to N raceway groove to extend grid SOI LDMOS device be example, state in detail technical scheme of the present invention.Unless otherwise noted, described technical scheme is equally applicable to P-channel device.
Embodiment 1
Fig. 4 a has provided a kind of structure cutaway view of typical extension grid SOI LDMOS device.Comprise longitudinal substrate layer 1, dielectric buried layer 2 and the first conductive type semiconductor active layer 3 from bottom to top.The first conductive type semiconductor active layer 3 one sides have the second conductive type semiconductor tagma 4, the second 4 surfaces, conductive type semiconductor tagma has the first adjacent conductive type semiconductor source region 6 and 5, the first conductive type semiconductor source regions 6, the second conductive type semiconductor body contact zone and 5 surfaces, the second conductive type semiconductor body contact zone and draws termination metallizing source S; The first conductive type semiconductor active layer 3 opposite sides have 7 surfaces, 7, the first conductive type semiconductor drain region, the first conductive type semiconductor drain region and draw termination metallization drain D; The first conductive type semiconductor active layer 3 between the second conductive type semiconductor tagma 4 and the first conductive type semiconductor drain region 7 forms the first conductive type semiconductor drift region 3a; The second 4 surfaces, conductive type semiconductor tagma, comprises that 6 surfaces, part the first conductive type semiconductor source region that are attached thereto have gate medium 8, and gate medium 8 surfaces have grid electric conducting material 13, and described grid electric conducting material 13 surfaces meet metallization gate electrode G.
Described gate medium 8 extends to the first conductive type semiconductor drain region 7 along device the first 3a surface, conductive type semiconductor drift region when covering 4 surface, the second conductive type semiconductor tagma, on the surface of gate medium 8 extensions, have the gate semiconductor of extension material, gate medium 8 extensions and extension gate semiconductor material form extension grid structure; Described extension gate semiconductor material is only followed successively by the second conductive type semiconductor gate contact zone 9, high resistance area 10, the first cut-off region, conductive type semiconductor field 11 and the second conductive type semiconductor that are linked in sequence and misses contact area 12 from playing near grid electric conducting material 13 near metallization drain D, wherein the second conductive type semiconductor gate contact zone 9 and metallization gate electrode G electrical connection, the second conductive type semiconductor is missed contact area 12 and metallization drain D is electric and joins.
Embodiment 2
Fig. 4 b has provided the structural representation that the segmentation of a kind of drift region changes the extension grid SOI LDMOS device of doping.Compare with embodiment 1, in this routine device, the doping content of drift region 3a is from increasing to 7 segmentations of close drain region near tagma 4.Sectional doped drift region can weaken the impact of RESURF effect on drift region Electric Field Distribution in SOI device.Therefore this routine device is compared withstand voltage meeting with the device in embodiment 1 and is significantly improved, but because drift region requires sectional doped, therefore higher to technological requirement.
Embodiment 3
Fig. 4 c has provided the structural representation that a kind of high resistance area becomes the extension grid SOI LDMOS device of conduction type doping.Compare with embodiment 2, this routine device adopts the doping of the second conduction type in the high resistance area 10 of extending grid near the part of gate contact zone 9, and in the part near a cut-off region 11, adopts the doping of the first conduction type.The part near cut-off region 11 adopt the doping of the first conduction type can avoid device turn-off in withstand voltage state high resistance area 10 doping near the second conduction type of a cut-off region 11 entirely exhaust after adverse effect to drift region longitudinal electric field intensity.Therefore, this routine device is compared withstand voltage meeting with the device in embodiment 2 and is improved, but because the doping type of high resistance area 10 is different, therefore more complicated for technological requirement.
Embodiment 4
Fig. 4 d has provided the structural representation that the segmentation of a kind of high resistance area changes the extension grid SOI LDMOS device of doping.Compare with embodiment 2-3, this routine device does not adopt the sectional doped form of drift region 3a in embodiment 2-3 and uses the form from changing to 11 segmentations of a close cut-off region near gate contact zone 9 in the high resistance area of described extension grid 10 doping contents instead.Because distribution of resistance in drift region Uniform Doped so its drift region is compared more even with embodiment 2-3.Therefore, when this routine device is compared work with the device in embodiment 2-3, its Temperature Distribution is more even, and device operating state is more stable.
Embodiment 5
Fig. 4 e has provided the three-dimensional structure schematic diagram of the extension grid SOI LDMOS device of arranging along raceway groove a kind of body contact zone 5 that is applied to thin active layer.Compare with embodiment 1-4, thereby this routine device do not adopt body contact zone 5 in embodiment 1-4 and source region 6 both directions X arrange and dielectric buried layer 2 between there is the structure in tagma 4, and use body contact zone 5 and source region 6 instead, both directly extend to dielectric buried layer 2, body contact zone 5 and source region 6 are arranged and made it in Z direction simultaneously to contact with tagma 4.Because contact zone 5 and source region 6 extend to dielectric buried layer 2, this structure more easily realizes when active layer 3 is thinner in technique, and body contact zone 5 and source region 6 have good contacting and also can effectively alleviate in active layer 3 dead resistance impact on device performance compared with the floater effect causing greatly in tagma 4 when thin in Z direction and tagma 4 simultaneously.But because body contact zone 5 and source region 6 are arranged and caused reducing of device channel area in Z direction, therefore, this routine device is compared its floater effect when active layer 3 is thinner with the device in embodiment 1-4 can access alleviation effectively, but conducting resistance can increase to some extent.
The described extension grid of above-mentioned several examples of the present invention SOI LDMOS device, its active layer 3 can adopt the semi-conducting materials such as Si, SiC, SiGe, SiGe, GaA or GaN, and the relative technology maturation of this different materials, is easy to draw materials.For the material in dielectric buried layer 2, the material that technical maturity is conventional is SiO 2, there is Gauss theorem to obtain, also can adopt dielectric coefficient lower than SiO 2low-K dielectric improve the longitudinally withstand voltage thickness that reduces dielectric buried layer 2.
The described extension grid of above-mentioned several examples of the present invention SOI LDMOS device, its gate medium 8 and extension gate medium 8a can adopt SiO 2, also can adopt dielectric coefficient higher than SiO 2high K dielectric.When the raising of dielectric coefficient can increase forward conduction, extend grid in the concentration of the majority carrier accumulation of drift region formation, thereby further reduce conduction resistance.

Claims (10)

1.一种具有延伸栅结构的SOI LDMOS器件，其元胞结构包括纵向自下而上的衬底层(1)，介质埋层(2)和第一导电类型半导体有源层(3)；第一导电类型半导体有源层(3)一侧具有第二导电类型半导体体区(4)，第二导电类型半导体体区(4)表面具有相邻的第一导电类型半导体源区(6)和第二导电类型半导体体接触区(5)，第一导电类型半导体源区(6)和第二导电类型半导体体接触区(5)表面引出端接金属化源极(S)；第一导电类型半导体有源层(3)另一侧具有第一导电类型半导体漏区(7)，第一导电类型半导体漏区(7)表面引出端接金属化漏极(D)；第二导电类型半导体体区(4)与第一导电类型半导体漏区(7)之间的第一导电类型半导体有源层(3)形成第一导电类型半导体漂移区(3a)；第二导电类型半导体体区(4)表面，包括与之相连的部分第一导电类型半导体源区(6)表面具有栅介质(8)，栅介质(8)表面具有栅导电材料(13)，所述栅导电材料(13)表面接金属化栅电极(G)；1. A SOI LDMOS device with an extended gate structure, its cell structure includes a vertical bottom-up substrate layer (1), a dielectric buried layer (2) and a first conductivity type semiconductor active layer (3); One conductive type semiconductor active layer (3) has a second conductive type semiconductor body region (4) on one side, and the surface of the second conductive type semiconductor body region (4) has an adjacent first conductive type semiconductor source region (6) and The second conductivity type semiconductor body contact region (5), the first conductivity type semiconductor source region (6) and the surface of the second conductivity type semiconductor body contact region (5) lead out the terminal metallization source (S); the first conductivity type The other side of the semiconductor active layer (3) has a first conductivity type semiconductor drain region (7), the surface of the first conductivity type semiconductor drain region (7) leads to a metallized drain (D); the second conductivity type semiconductor body The first conductivity type semiconductor active layer (3) between the region (4) and the first conductivity type semiconductor drain region (7) forms the first conductivity type semiconductor drift region (3a); the second conductivity type semiconductor body region (4 ) surface, including a part of the first conductive type semiconductor source region (6) connected thereto has a gate dielectric (8) on the surface, and the gate dielectric (8) has a gate conductive material (13) on the surface, and the gate conductive material (13) represents The metallized gate electrode (G) is connected to the surface; 其特征在于：It is characterized by: 所述栅介质(8)覆盖第二导电类型半导体体区(4)表面的同时沿器件第一导电类型半导体漂移区(3a)表面延伸至第一导电类型半导体漏区(7)，在栅介质(8)延伸部分的表面具有延伸栅半导体材料，栅介质(8)延伸部分和延伸栅半导体材料构成延伸栅结构；所述延伸栅半导体材料从靠近栅导电材料(13)起到靠近金属化漏极(D)止为顺序连接的第二导电类型半导体栅接触区(9)、高阻区(10)、第一导电类型半导体场截止区(11)和第二导电类型半导体漏接触区(12)，其中第二导电类型半导体栅接触区(9)与金属化栅电极(G)电气连接，第二导电类型半导体漏接触区(12)与金属化漏极(D)电气相接。The gate dielectric (8) covers the surface of the semiconductor body region (4) of the second conductivity type and extends along the surface of the semiconductor drift region (3a) of the first conductivity type of the device to the drain region (7) of the semiconductor of the first conductivity type. (8) The surface of the extended part has an extended gate semiconductor material, and the extended part of the gate dielectric (8) and the extended gate semiconductor material form an extended gate structure; the extended gate semiconductor material is from close to the gate conductive material (13) to close to the metallized drain The second conductive type semiconductor gate contact region (9), the high resistance region (10), the first conductive type semiconductor field stop region (11) and the second conductive type semiconductor drain contact region (12) are sequentially connected to the pole (D). ), wherein the second conductivity type semiconductor gate contact region (9) is electrically connected to the metallized gate electrode (G), and the second conductivity type semiconductor drain contact region (12) is electrically connected to the metallized drain (D). 2.根据权利要求1所述的具有延伸栅结构的SOI LDMOS器件，其特征在于，所述第一导电类型半导体有源层(3)的厚度小于1微米。2. The SOI LDMOS device with extended gate structure according to claim 1, characterized in that, the thickness of the first conductive type semiconductor active layer (3) is less than 1 micron. 3.根据权利要求1或2所述的具有延伸栅结构的SOI LDMOS器件，其特征在于，所述第一导电类型半导体漂移区(3a)采取变掺杂形式，其掺杂浓度从靠近第二导电类型半导体体区(4)起到第一导电类型半导体漏区(7)止逐渐增加。3. the SOI LDMOS device with extended gate structure according to claim 1 or 2, is characterized in that, described first conduction type semiconductor drift region (3a) adopts the variable doping form, and its doping concentration ranges from close to the second The conductivity type semiconductor body region (4) gradually increases until the first conductivity type semiconductor drain region (7). 4.根据权利要求1、2或3所述的具有延伸栅结构的SOI LDMOS器件，其特征在于，所述高阻区(10)材料为第二导电类型半导体，且掺杂浓度小于第二导电类型半导体栅接触区(9)和第二导电类型半导体漏接触区(12)的掺杂浓度。4. the SOI LDMOS device with extended gate structure according to claim 1, 2 or 3, is characterized in that, the material of the high resistance region (10) is a second conductivity type semiconductor, and the doping concentration is less than the second conductivity type semiconductor. The doping concentration of the semiconductor gate contact region (9) of the second conductivity type and the drain contact region (12) of the second conductivity type semiconductor. 5.根据权利要求4所述的具有延伸栅结构的SOI LDMOS器件，其特征在于，所述高阻区(10)采取变掺杂形式，其掺杂浓度从靠近第二导电类型半导体栅接触区(9)起到第一导电类型半导体场截止区(11)止逐渐减小。5. the SOI LDMOS device with extended gate structure according to claim 4, is characterized in that, described high-resistance region (10) adopts variable doping form, and its doping concentration is from close to second conductive type semiconductor gate contact region (9) gradually decrease until the field stop region (11) of the first conductivity type semiconductor. 6.根据权利要求1、2或3所述的具有延伸栅结构的SOI LDMOS器件，其特征在于，所述高阻区(10)材料为第一导电类型半导体，且掺杂浓度小于第一导电类型半导体场截止区(11)的掺杂浓度。6. the SOI LDMOS device with extended gate structure according to claim 1, 2 or 3, is characterized in that, the material of the high resistance region (10) is a first conductivity type semiconductor, and the doping concentration is less than the first conductivity type semiconductor. The doping concentration of the type semiconductor field stop region (11). 7.根据权利要求6所述的具有延伸栅结构的SOI LDMOS器件，其特征在于，所述高阻区(10)采取变掺杂形式，其掺杂浓度从靠近第二导电类型半导体栅接触区(9)起到第一导电类型半导体场截止区(11)止逐渐增加。7. the SOI LDMOS device with extended gate structure according to claim 6, is characterized in that, described high-resistance region (10) adopts variable doping form, and its doping concentration is from close to second conductive type semiconductor gate contact region (9) gradually increase until the field stop region (11) of the first conductivity type semiconductor. 8.根据权利要求1、2或3所述的具有延伸栅结构的SOI LDMOS器件，其特征在于，所述高阻区(10)由靠近第二导电类型半导体栅接触区(9)的第二导电类型半导体高阻区(10-1)和靠近第一导电类型半导体场截止区(11)的第一导电类型半导体高阻区(10-2)构成。8. according to claim 1,2 or 3 described SOI LDMOS devices with extended gate structure, it is characterized in that, described high-resistance region (10) is formed by the second close to second conductive type semiconductor gate contact region (9). The conductive type semiconductor high resistance region (10-1) is composed of the first conductive type semiconductor high resistance region (10-2) close to the first conductive type semiconductor field stop region (11). 9.根据权利要求1至8中任一项所述具有延伸栅结构的SOI LDMOS器件，其特征在于，所述栅介质(8)采用二氧化硅或者介电系数高于二氧化硅的介质材料。9. according to the described SOI LDMOS device with extended gate structure according to any one of claim 1 to 8, it is characterized in that, described gate medium (8) adopts silicon dioxide or the dielectric material with dielectric coefficient higher than silicon dioxide . 10.根据权利要求1至8中任一项所述具有延伸栅结构的SOI LDMOS器件，其特征在于，所述介质埋层(2)采用二氧化硅或者介电系数低于二氧化硅的介质材料。10. according to the SOI LDMOS device with extended gate structure described in any one in claim 1 to 8, it is characterized in that, described dielectric buried layer (2) adopts silicon dioxide or the dielectric coefficient lower than silicon dioxide Material.
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