CN111352280B - Display panel - Google Patents

Abstract

A display panel comprises a first substrate, a pixel array, a first output line, a second output line, a first sensing device and a second sensing device. The pixel array is located on the first substrate. The pixel array is driven in a row inversion mode and comprises a plurality of scanning lines, a plurality of data lines and a plurality of pixels. Each pixel comprises a plurality of sub-pixels, and each sub-pixel is electrically connected to a corresponding scanning line and a corresponding data line. The first output line and the second output line are substantially parallel to the data line. One of the data lines most adjacent to the first output line and the other of the data lines most adjacent to the second output line have the same polarity. The first sensing device and the second sensing device are electrically connected to the first output line and the second output line respectively.

Description

display panel

technical field

The present invention relates to a display panel, and more particularly, to a display panel including a sensing device.

Background technique

At present, in order to increase the convenience of use of the products, many manufacturers install sensing devices in the products. For example, a sensor device for fingerprint recognition is often attached to an existing mobile phone. In the existing fingerprint recognition technology, the sensing device detects the light reflected by the fingerprint of the finger, and the fluctuation of the fingerprint will have different intensities of reflected light, so the different fingerprint appearances will be distinguished by the sensing device.

However, when the light is insufficient or the fingerprint dent is not obvious, the sensing device is prone to false detection. As a result, the user needs to repeat the induction to successfully identify the fingerprint. Therefore, there is an urgent need for a method that can solve the aforementioned problems.

SUMMARY OF THE INVENTION

At least one embodiment of the present invention provides a display panel, which can reduce the influence of the polarity of a data line on a sensing device, thereby improving the ability of the sensing device to identify fingerprints.

At least one embodiment of the present invention provides a display panel. The display panel includes a first substrate, a pixel array, a first output line, a second output line, a first sensing device, and a second sensing device. The pixel array is located on the first substrate. The pixel array is driven in a row inversion manner, and includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels. The data lines are interleaved with the scan lines. Each pixel includes a plurality of sub-pixels, and each sub-pixel is electrically connected to a corresponding scan line and a corresponding data line. The first output line and the second output line are substantially parallel to the data lines. One of the data lines closest to the first output line and the other of the data lines closest to the second output line have the same polarity. The first sensing device and the second sensing device are electrically connected to the first output line and the second output line, respectively.

At least one embodiment of the present invention provides a display panel. The display panel includes a first substrate, a pixel array, a first output line, a second output line, a first sensing device, a second sensing device, a system voltage line, a first reference voltage line, and a second reference voltage line. The pixel array is located on the first substrate and includes a plurality of scan lines, a plurality of data lines and a plurality of pixels. The data lines are interleaved with the scan lines. Each pixel includes a plurality of sub-pixels, and each sub-pixel is electrically connected to a corresponding scan line and a corresponding data line. The first output line and the second output line are substantially parallel to the data lines. The first sensing device and the second sensing device are electrically connected to the first output line and the second output line, respectively, and the first sensing device and the second sensing device respectively include a first photosensitive element and a second photosensitive element. The system voltage line is located between the first sensing device and the second sensing device and between the first output line and the second output line, and is electrically connected to the first sensing device and the second sensing device. The first reference voltage line and the second reference voltage line are located on two sides of the first photosensitive element and the second photosensitive element, respectively. The first reference voltage line and the second reference voltage line are electrically connected to the first sensing device and the second sensing device, respectively.

The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention.

2A is a schematic top view of a pixel array substrate according to an embodiment of the present invention.

Fig. 2B is a schematic cross-sectional view taken along the section line aa' of Fig. 2A .

3A is a schematic bottom view of a sensing element substrate according to an embodiment of the present invention.

Fig. 3B is a schematic cross-sectional view along the section line bb' of Fig. 3A.

4A is a schematic top view of a pixel array substrate according to an embodiment of the present invention.

4B is a schematic bottom view of a sensing element substrate according to an embodiment of the present invention.

4C is a schematic perspective view of a display panel according to an embodiment of the present invention.

Among them, reference numerals:

1, 2: Display panel

10: Pixel array substrate

100: First substrate

110: Pixel array

20: Sensing element substrate

200: Second substrate

212: first output line

214: Second output line

216: The third output line

218: Fourth output line

222: First Sensing Device

224: Second Sensing Device

222a: third sensing device

224a: Fourth Sensing Device

222b: Fifth Sensing Device

224b: Sixth Sensing Device

222c: Seventh Sensing Device

224c: Eighth Sensing Device

232: First system voltage line

234: Second system voltage line

242: first reference voltage line

244: Second reference voltage line

246: Third reference voltage line

252: the first control signal line

254: The second control signal line

256: The third control signal line

258: Fourth control signal line

BL: Backlight Module

B1, B1', I1, I1', I2, I2', I3, I3', I4: insulating layer

B2: Passivation layer

CE: Common electrode

CL: Common electrode line

C1, C3: Conductive layer

C2, C4: electrode layer

D, D1, D2: Drain

CH, CH1, CH2: semiconductor channel layers

CR: Blackout area

DL: data line

F: finger

G, G1, G2: Grid

LC: Display medium layer

LR: light

LS: photosensitive element

LS1: The first photosensitive element

LS2: The first photosensitive element

LS1a: Third photosensitive element

LS2a: Fourth photosensitive element

LS1b: Fifth photosensitive element

LS2b: sixth photosensitive element

LS1c: seventh photosensitive element

LS2c: Eighth photosensitive element

OR: light transmission area

PE: pixel electrode

px: pixels

P1, P2, P3, P4: pitch

R1, R2: light sensing layer

H1, H2, H1a, H2a, H1b, H2b, H1c, H2c, H1d, H3a, H3b, O1, O2, OP, TH1, TH2: Open

S, S1, S2: source

SL: scan line

SM: Masking layer

SP: Subpixel

TE: transfer electrode

T: switching element

T1: The first switching element

T2: Second switching element

T3: Third switching element

T4: Fourth switching element

Detailed ways

Below in conjunction with accompanying drawing, structure principle and working principle of the present invention are described in detail:

FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention. For convenience of description, FIG. 1 omits to illustrate some components of the sensing element substrate and the pixel array substrate.

Please refer to FIG. 1 , the display panel 1 includes a sensing element substrate 20 , a pixel array substrate 10 and a display medium layer LC. The sensing element substrate 20 faces the pixel array substrate 10 . The display medium layer LC is located between the pixel array substrate 10 and the sensing element substrate 20 . In this embodiment, the display panel 1 further includes a backlight module BL. The backlight module BL is disposed below the pixel array substrate 10 . In other words, the pixel array substrate 10 is located between the backlight module BL and the sensing element substrate 20 .

In this embodiment, the pixel array substrate 10 includes a first substrate 100 and a pixel array 110 . The pixel array 110 is located on the first substrate 100 .

In this embodiment, the sensing element substrate 20 includes a second substrate 200 and a plurality of sensing devices (illustrated by the sensing device LS in the sensing device in FIG. 1 ). The sensing device is located on the second substrate 200 . In some embodiments, the sensing element substrate 20 further includes a system voltage line, a reference voltage line, and an output line. The arrangement of the system voltage line, the reference voltage line and the output line can be seen in the embodiment of FIG. 2A .

In this embodiment, the photosensitive element LS includes a conductive layer C1, a photosensitive layer R, and an electrode layer C2. The photo-sensing layer R is located between the conductive layer C1 and the electrode layer C2.

In this embodiment, when the finger F is close to the sensing element substrate 20 , the light LR emitted by the backlight module BL will be reflected to the light sensing layer R by the finger F.

2A is a schematic top view of a pixel array substrate according to an embodiment of the present invention. Fig. 2B is a schematic cross-sectional view taken along the section line aa' of Fig. 2A . 3A is a schematic bottom view of a sensing element substrate according to an embodiment of the present invention. Fig. 3B is a schematic cross-sectional view along the section line bb' of Fig. 3A. It should be noted that, in order to make the drawings clear, FIGS. 2A , 2B, 3A and 3B are not drawn in isometric scales.

It must be noted here that the embodiments of FIG. 2A to FIG. 3B use the element numbers and part of the content of the embodiment of FIG. 1 , wherein the same or similar reference numbers are used to represent the same or similar elements, and the same technical content is omitted. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

In this embodiment, the display panel has a light-transmitting region OR and a light-shielding region CR. In some embodiments, the light-shielding region CR overlaps the black matrix (not shown in FIG. 2B and FIG. 3B ). In some embodiments, the black matrix is located in the sensing element substrate 20 . In other embodiments, the black matrix is located in the pixel array substrate 10 .

Referring to FIGS. 2A and 2B , the pixel array 110 is located on the first substrate 100 and includes a plurality of scan lines SL, a plurality of data lines DL, and a plurality of pixels PX. The data lines DL may be zigzag, straight or other shapes.

The data lines DL are interlaced with the scan lines SL. Each pixel PX includes a plurality of sub-pixels SP, and each sub-pixel SP is electrically connected to a corresponding scan line SL and a corresponding data line DL.

In this embodiment, each sub-pixel SP includes a switching element T and a pixel electrode PE electrically connected to the switching element T. In this embodiment, the switching element T, the scan line SL and the data line DL are located in the light-shielding region CR, and at least part of the pixel electrode PE is located in the light-transmitting region OR.

The switching element T is located, for example, on the insulating layer I1. In some embodiments, the light shielding layer M is sandwiched between the switching element T and the first substrate 100 . The switching element T includes a gate G, a source S, a drain D, and a semiconductor channel layer CH. The semiconductor channel layer CH is on the insulating layer I1. The gate G and the semiconductor channel layer CH are overlapped, and the insulating layer I2 is sandwiched between the gate G and the semiconductor channel layer CH. The gate G is electrically connected to the scan line SL. In this embodiment, the gate G and the scan line SL belong to the same conductive film layer, but the invention is not limited to this. The insulating layer I3 is located on the insulating layer I2 and covers the gate G and the scan line SL. The source electrode S and the drain electrode D are located above the insulating layer I3, and the source electrode S is electrically connected to the data line DL. In this embodiment, the source electrode S and the data line DL belong to the same conductive film layer, but the invention is not limited to this. The source electrode S and the drain electrode D are electrically connected to the semiconductor channel layer CH through the openings H1 and H2, and the openings H1 and H2 are located in the insulating layer I3 and the insulating layer I2, for example. The insulating layer B1 is located above the source electrode S and the drain electrode D.

The above-mentioned switching element T is described by taking a top-gate thin film transistor as an example, but the present invention is not limited to this. According to other embodiments, the above-mentioned switching element T may also be a bottom gate type thin film transistor.

In this embodiment, the pixel array substrate 10 selectively includes a common electrode line CL.

In this embodiment, the extending directions of the common electrode line CL and the data line DL are the same, and the common electrode line CL and the data line DL belong to the same film layer, but the invention is not limited to this. In other embodiments, the common electrode line CL and the data line DL belong to different layers, and the common electrode line CL overlaps the data line DL in a direction perpendicular to the first substrate 100 , thereby increasing the aperture ratio of the display panel.

The common electrode CE is located on the insulating layer B1 and is electrically connected to the common electrode line CL through the opening in the insulating layer B1. In some embodiments, the common electrode CE includes a touch electrode.

The insulating layer I4 is located on the common electrode CE. The pixel electrode PE is located on the insulating layer I4, the pixel electrode PE overlaps with the common electrode CE, and the pixel electrode PE is separated from the common electrode CE. The pixel electrode PE is electrically connected to the drain D of the switching element T through the opening OP. In this embodiment, the opening OP passes through the insulating layer B1 , the insulating layer I4 and the common electrode CE, but the invention is not limited thereto. In some embodiments, the pixel array substrate 10 may use a fringe field switching (FFS) technology or a lateral electric field (In-Plane-Switching, IPS) technology to drive the liquid crystal.

In this embodiment, the pixel array 110 is driven in a column inversion manner. For example, adjacent data lines DL have different polarities. In this embodiment, the polarity of the data line DL is continuously reversed with the operation time.

3A and 3B, the first output line 212, the second output line 214, the first sensing device 222, the second sensing device 224, the first system voltage line 232, the first reference voltage line 242, the second The reference voltage line 244 , the first control signal line 252 and the second control signal line 254 are located on the second substrate 200 . In this embodiment, the first output line 212, the second output line 214, the first sensing device 222, the second sensing device 224, the first system voltage line 232, the first reference voltage line 242, the second reference voltage The line 244 , the first control signal line 252 and the second control signal line 254 are located in the light-shielding region CR.

In the present embodiment, the first output line 212 , the second output line 214 , the first system voltage line 232 , the first reference voltage line 242 and the second reference voltage line 244 overlap and are substantially parallel to the lines on the first substrate 100 . The data line DL can prevent the aperture ratio of the display panel from decreasing. In some embodiments, the first output line 212 , the second output line 214 , the first system voltage line 232 , the first reference voltage line 242 , and the second reference voltage line 244 may be zigzag, straight, or other shapes. shape.

In this embodiment, the first sensing device 222 is electrically connected to the first output line 212 , the first reference voltage line 242 , the first control signal line 252 and the first system voltage line 232 . The first sensing device 222 includes a first switching element T1, a second switching element T2, and a first light-sensing element LS1.

In this embodiment, the first switching element T1 includes a gate G1 , a source S1 , a drain D1 and a semiconductor channel layer CH1 . In this embodiment, a light shielding layer M1 is further included between the first switching element T1 and the second substrate 200 , but the invention is not limited to this.

The semiconductor channel layer CH1 is located on the insulating layer I1'. The gate G1 overlaps with the semiconductor channel layer CH1, and an insulating layer I2' is sandwiched between the gate G1 and the semiconductor channel layer CH1. The gate G1 is electrically connected to the first control signal line 252 . The insulating layer I3' is located on the insulating layer I2' and covers the gate G1, the first control signal line 252 and the second control signal line 254. The source electrode S1 and the drain electrode D1 are located above the insulating layer I3', and the source electrode S1 is electrically connected to the first reference voltage line 242, wherein, for example, the first reference voltage line 242 is electrically connected to the voltage VSS. The source electrode S1 and the drain electrode D1 are electrically connected to the semiconductor channel layer CH1 through openings H1a and H2a, respectively, and the openings H1a and H2a are located in the insulating layer I3' and the insulating layer I2', for example.

The second switching element T2 includes a gate electrode G2, a source electrode S2, a drain electrode D2 and a semiconductor channel layer CH2. In this embodiment, the light shielding layer M2 is further included between the second switching element T2 and the second substrate 200 , but the invention is not limited to this.

The semiconductor channel layer CH2 is located on the insulating layer I1'. The gate G2 overlaps with the semiconductor channel layer CH2, and an insulating layer I2' is sandwiched between the gate G2 and the semiconductor channel layer CH2. The insulating layer I3' covers the gate G2. The gate G2 is electrically connected to the first switching element T1. For example, the drain D1 of the first switching element T1 is electrically connected to the gate G2 through the opening H3a, for example, the opening H3a is located in the insulating layer I3'. The source electrode S2 and the drain electrode D2 are located above the insulating layer I3', and the source electrode S2 is electrically connected to the first system voltage line 232, wherein, for example, the first system voltage line 232 is electrically connected to the voltage VDD. The drain D2 is electrically connected to the first output line 212 . The source electrode S2 and the drain electrode D2 are electrically connected to the semiconductor channel layer CH2 through openings H2b, H1b, which are located in the insulating layer I3' and the insulating layer I2', for example. This design makes the signal better.

The first photosensitive element LS1 includes a conductive layer C1, a photosensitive layer R1, and an electrode layer C2. The photo-sensing layer R1 is located between the conductive layer C1 and the electrode layer C2.

The conductive layer C1 is located on the insulating layer B1'. The conductive layer C1 of the first photosensitive element LS1 is electrically connected to the second control signal line 254 .

The electrode layer C2 is located on the insulating layer B1'. The electrode layer C2 of the first photosensitive element LS1 is electrically connected to the drain D1 of the first switching element T1 and the gate G2 of the second switching element T2. For example, the electrode layer C2 is electrically connected to the drain D1 of the first switching element T1 through the opening TH1, and the opening TH1 is, for example, located in the insulating layer B1'. In some embodiments, a transfer electrode layer (not shown) is selectively sandwiched between the electrode layer C2 and the drain electrode D1, and the transfer electrode layer and the conductive layer C1 belong to the same film layer, for example.

In this embodiment, the second sensing device 224 is electrically connected to the second output line 214 , the second reference voltage line 244 , the first control signal line 252 and the first system voltage line 232 . In this embodiment, the first sensing device 222 and the second sensing device 224 share the same first system voltage line 232 . The second sensing device 224 includes a third switching element T3, a fourth switching element T4 and a second light-sensing element LS2.

In this embodiment, the third switching element T3 includes a gate electrode G3, a source electrode S3, a drain electrode D3 and a semiconductor channel layer CH3. In this embodiment, a light shielding layer M3 is further included between the third switching element T3 and the second substrate 200 , but the invention is not limited to this.

The semiconductor channel layer CH3 is located on the insulating layer I1'. The gate G3 overlaps with the semiconductor channel layer CH3, and an insulating layer I2' is sandwiched between the gate G3 and the semiconductor channel layer CH3. The gate G3 is electrically connected to the first control signal line 252 . The insulating layer I3' covers the gate G3. The source electrode S3 and the drain electrode D3 are located above the insulating layer I3', and the source electrode S3 is electrically connected to the second reference voltage line 244, wherein, for example, the second reference voltage line 244 is electrically connected to the voltage VSS. The source electrode S3 and the drain electrode D3 are electrically connected to the semiconductor channel layer CH3 through openings H1c and H2c, respectively. The openings H1c and H2c are located in the insulating layer I3' and the insulating layer I2', for example.

The fourth switching element T4 includes a gate electrode G4, a source electrode S4, a drain electrode D4 and a semiconductor channel layer CH4. In this embodiment, a light shielding layer M4 is further included between the fourth switching element T4 and the second substrate 200 , but the invention is not limited to this.

The semiconductor channel layer CH4 is located on the insulating layer I1'. The gate G4 overlaps with the semiconductor channel layer CH4, and an insulating layer I2' is sandwiched between the gate G4 and the semiconductor channel layer CH4. The insulating layer I3' covers the gate G4. The gate G4 is electrically connected to the third switching element T3. For example, the drain D3 of the third switching element T3 is electrically connected to the gate G4 through the opening H3b, for example, the opening H3b is located in the insulating layer I3'. The source electrode S4 and the drain electrode D4 are located above the insulating layer I3', and the source electrode S4 is electrically connected to the first system voltage line 232. The drain D4 is electrically connected to the second output line 214 . The source electrode S4 and the drain electrode D4 are electrically connected to the semiconductor channel layer CH4 through openings H2b and H1d, and the opening H1d is located in the insulating layer I3' and the insulating layer I2', for example. This design makes the signal better.

In this embodiment, the semiconductor channel layer CH4 and the semiconductor channel layer CH2 are integrated, and the source electrode S4 and the source electrode S2 are integrated, thereby reducing the size of the sensing device.

In some embodiments, the shapes of the gate G2 and the gate G4 are mirror-symmetrical to each other, and the shapes of the drain D1 and the drain D3 are mirror-symmetrical to each other.

In this embodiment, the gate G1 , the gate G2 , the gate G3 , the gate G4 , the first control signal line 252 and the second control signal line 254 belong to the same conductive film layer, but the invention is not limited thereto. In this embodiment, the source electrode S1, the drain electrode D1, the source electrode S2, the drain electrode D2, the source electrode S3, the drain electrode D3, the source electrode S4, the drain electrode D4, the first reference voltage line 242, the second reference voltage line 244 , the first output line 212 , the second output line 214 and the first system voltage line 232 belong to the same conductive film layer, but the invention is not limited to this.

In this embodiment, the first switching element T1 , the second switching element T2 , the third switching element T3 and the fourth switching element T4 are described by taking the top gate type thin film transistor as an example, but the invention is not limited thereto. In other embodiments, the first switching element T1 , the second switching element T2 , the third switching element T3 and the fourth switching element T4 may also be bottom gate type thin film transistors or other suitable thin film transistors.

The second light-sensing element LS2 includes a conductive layer C3, a light-sensing layer R2, and an electrode layer C4. The photo-sensing layer R2 is located between the conductive layer C3 and the electrode layer C4.

The conductive layer C3 is located on the insulating layer B1'. The conductive layer C3 is electrically connected to the second control signal line 254 . In this embodiment, the conductive layer C1 and the conductive layer C3 are integrated, and the conductive layer C1 and the conductive layer C3 are electrically connected to the transfer electrode TE through the opening O1, and the transfer electrode TE is electrically connected to the transfer electrode TE through the opening O2 The second control signal line 254 . The opening O1 is, for example, in the insulating layer B1'. The opening O2 is, for example, in the insulating layer I3'. In some embodiments, the transition electrode TE and the first system voltage line 232 belong to the same conductive film layer, but the invention is not limited to this.

The electrode layer C4 is located on the insulating layer B1'. The electrode layer C4 is electrically connected to the drain D3 of the third switching element T3 and the gate G4 of the fourth switching element T4. For example, the electrode layer C4 is electrically connected to the drain D3 of the third switching element T3 through the opening TH2, for example, the opening TH2 is located in the insulating layer B1'. In some embodiments, a transfer electrode layer (not shown) is selectively sandwiched between the electrode layer C4 and the drain electrode D3, and the transfer electrode layer and the conductive layer C3 belong to the same film layer, for example.

In this embodiment, the materials of the conductive layer C1 and the conductive layer C3 are preferably transparent conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide or Other suitable oxides or stacks of at least two of the above.

In this embodiment, the materials of the electrode layer C2 and the electrode layer C4 are, for example, molybdenum, aluminum, titanium, copper, gold, silver or other conductive materials or a stack of two or more of the above materials. In some embodiments, the electrode layer C2 and the electrode layer C4 can be used as a reflective layer, thereby increasing the light that the photo-sensing layer R1 and the photo-sensing layer R2 can receive.

In this embodiment, the materials of the photo-sensing layer R1 and the photo-sensing layer R2 are, for example, silicon-rich oxide (SRO) or other suitable materials.

In this embodiment, the sensing element substrate 20 further includes a shielding layer SM.

The shielding layer SM is located between the first output line 212 and the pixel array substrate 10 , between the second output line 214 and the pixel array substrate 10 , between the first system voltage line 232 and the pixel array substrate 10 , and between the first reference voltage line 242 and the pixel array substrate 10 , between the second reference voltage line 244 and the pixel array substrate 10 , between the first control signal line 252 and the pixel array substrate 10 , and between the second control signal line 254 and the pixel array substrate 10 .

In some embodiments, the shielding layer SM, the conductive layer C1 and the conductive layer C3 are the same conductive film layer. The shielding layer SM and the conductive layer C1 (or the conductive layer C3 ) are electrically connected to different signal sources. The problem that the electric field generated by the sensing element substrate 20 affects the liquid crystal molecules in the display medium layer is improved by the shielding layer SM, and the display quality of the display device can be improved.

In some embodiments, the common electrode CE and the shielding layer SM are electrically connected to the same signal source. It can also be said that the same signal is applied to the common electrode CE and the shielding layer SM, thereby further improving the problem that the electric field generated by the sensing element substrate 20 affects the display quality.

In this embodiment, the sensing element substrate 20 further includes a passivation layer B2. The passivation layer B2 covers the conductive layer C1, the electrode layer C2, the shielding layer SM and the insulating layer B1'.

In this embodiment, the first system voltage line 232 is located between the first sensing device 222 and the second sensing device 224 and between the first output line 212 and the second output line 214, and the first reference voltage line 242 and the second reference voltage line 244 are located on both sides of the first photosensitive element 222 and the second photosensitive element 224, respectively. Therefore, a data line DL closest to the first output line 212 and a data line DL closest to the second output line 214 The other data line DL has the same polarity (eg, the same positive pole or the same negative pole at the same time). For example, one data line DL overlapping the first output line 212 and another data line DL overlapping the second output line 214 have the same polarity, thereby reducing the polarity of the data line DL to the first inductance The influence caused by the sensing device 222 and the second sensing device 224 is improved, and the ability of the first sensing device 222 and the second sensing device 224 to identify fingerprints is improved.

4A is a schematic top view of a pixel array substrate according to an embodiment of the present invention. 4B is a schematic bottom view of a sensing element substrate according to an embodiment of the present invention. 4C is a schematic perspective view of a display panel according to an embodiment of the present invention.

It must be noted here that the embodiments of FIGS. 4A to 4C use the element numbers and part of the content of the embodiments of FIGS. 2A to 3B , wherein the same or similar reference numbers are used to represent the same or similar elements, and the same elements are omitted. Description of technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

Referring to FIGS. 4A , 4B and 4C , the display device 2 includes a sensing element substrate 20 and a pixel array substrate 10 .

The pixel array substrate 10 includes a first substrate 100 and a pixel array 110 . The pixel array 110 is located on the first substrate 100 . The pixel array 110 includes a plurality of scan lines SL, a plurality of data lines DL, and a plurality of pixels PX. Each pixel PX includes a plurality of sub-pixels SP, and each sub-pixel SP is electrically connected to a corresponding scan line SL and a corresponding data line DL. In this embodiment, each sub-pixel SP includes a switching element T and a pixel electrode PE electrically connected to the switching element T.

In this embodiment, the sensing element substrate 20 includes a second substrate 200, a first sensing device 222, a second sensing device 224, a third sensing device 222a, a fourth sensing device 224a, and a fifth sensing device 222b, sixth sensing device 224b, seventh sensing device 222c, eighth sensing device 224c, first system voltage line 232, second system voltage line 234, first output line 212, second output line 214, Three output lines 216, fourth output line 218, first reference voltage line 242, second reference voltage line 244, third reference voltage line 246, first control signal line 252, second control signal line 254, third control signal line 256 and fourth control signal line 258 .

The first sensing device 222 is electrically connected to the first system voltage line 232 , the first output line 212 , the first control signal line 252 , the second control signal line 254 and the first reference voltage line 242 . The second sensing device 224 is electrically connected to the first system voltage line 232 , the second output line 214 , the first control signal line 252 , the second control signal line 254 and the second reference voltage line 244 .

The structures of the third sensing device 222a and the fourth sensing device 224a are respectively similar to the first sensing device 222 and the second sensing device 224 in the foregoing embodiments. The third sensing device 222 a is electrically connected to the second system voltage line 234 , the third output line 216 , the first control signal line 252 , the second control signal line 254 and the second reference voltage line 244 . The fourth sensing device 224 a is electrically connected to the second system voltage line 234 , the fourth output line 218 , the first control signal line 252 , the second control signal line 254 and the third reference voltage line 246 .

The structures of the fifth sensing device 222b and the sixth sensing device 224b are respectively similar to the first sensing device 222 and the second sensing device 224 in the foregoing embodiments. The fifth sensing device 222b is electrically connected to the first system voltage line 232 , the first output line 212 , the third control signal line 256 , the fourth control signal line 258 and the first reference voltage line 242 . The sixth sensing device 224b is electrically connected to the first system voltage line 232 , the second output line 214 , the third control signal line 256 , the fourth control signal line 258 and the second reference voltage line 244 .

The structures of the seventh sensing device 222c and the eighth sensing device 224c are respectively similar to the first sensing device 222 and the second sensing device 224 in the foregoing embodiments. The seventh sensing device 222c is electrically connected to the second system voltage line 234 , the third output line 216 , the third control signal line 256 , the fourth control signal line 258 and the second reference voltage line 244 . The eighth sensing device 224c is electrically connected to the second system voltage line 234 , the fourth output line 218 , the third control signal line 256 , the fourth control signal line 258 and the third reference voltage line 246 .

In this embodiment, the data line DL closest to the first output line 212, the data line DL closest to the second output line 214, the data line DL closest to the third output line 216, and the The most adjacent data lines DL of the four output lines 218 have the same polarity. Therefore, the influence of the polarities of the data lines DL on the sensing device can be reduced, thereby improving the ability of the sensing device to identify fingerprints.

In this embodiment, the first sensing device 222, the second sensing device 224, the third sensing device 222a, the fourth sensing device 224a, the fifth sensing device 222b, the sixth sensing device 224b, the seventh The sensing device 222c and the eighth sensing device 224c respectively include a first photosensitive element LS1, a second photosensitive element LS2, a third photosensitive element LS1a, a fourth photosensitive element LS2a, a fifth photosensitive element LS1b, a sixth photosensitive element LS2b, a Seven photosensitive elements LS1c and eighth photosensitive elements LS2c.

In this embodiment, the pitch between the photosensitive elements is equal to the pitch between the pixels PX. For example, the pitch P1 between the first photosensitive element LS1 and the second photosensitive element LS2 is equal to the pitch P2 between the pixels PX, and the pitch P3 between the first photosensitive element LS1 and the fifth photosensitive element LS1b is approximately equal to Pitch P4 between pixels PX. In this embodiment, the pitch P1 is equal to the pitch P3, and the pitch P2 is equal to the pitch P4.

Although in this embodiment, the first sensing device 222, the second sensing device 224, the third sensing device 222a, the fourth sensing device 224a, the fifth sensing device 222b, the sixth sensing device 224b, the Seven sensing device 222c, eighth sensing device 224c, first system voltage line 232, second system voltage line 234, first output line 212, second output line 214, third output line 216, fourth output line 218 , the first reference voltage line 242, the second reference voltage line 244, the third reference voltage line 246, the first control signal line 252, the second control signal line 254, the third control signal line 256, and the fourth control signal line 258 are located at on the second substrate 200, but the present invention is not limited to this. In other embodiments, the first sensing apparatus 222, the second sensing apparatus 224, the third sensing apparatus 222a, the fourth sensing apparatus 224a, the fifth sensing apparatus 222b, the sixth sensing apparatus 224b, the seventh sensing apparatus The sensing device 222c, the eighth sensing device 224c, the first system voltage line 232, the second system voltage line 234, the first output line 212, the second output line 214, the third output line 216, the fourth output line 218, The first reference voltage line 242, the second reference voltage line 244, the third reference voltage line 246, the first control signal line 252, the second control signal line 254, the third control signal line 256, and the fourth control signal line 258 are located in the on a substrate 100 .

To sum up, since the first system voltage line is located between the first sensing device and the second sensing device and between the first output line and the second output line, and the first reference voltage line and the second reference voltage line Located on both sides of the first photosensitive element and the second photosensitive element, the data line closest to the first output line and the other data line closest to the second output line have the same polarity (for example, in the same time is the same positive or the same negative). For example, one data line overlapping the first output line and another data line overlapping the second output line have the same polarity, therefore, the polarity of the data line can be reduced for the first sensing device and the second The influence caused by the sensing device is improved, thereby enhancing the ability of the first sensing device and the second sensing device to identify fingerprints.

Of course, the present invention can also have other various embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding Changes and deformations should belong to the protection scope of the appended claims of the present invention.

Claims (11)

1. A display panel, comprising:

a pixel array on a first substrate, wherein the pixel array is driven in a row inversion manner and includes;

a plurality of scan lines;

a plurality of data lines interlaced with the scan lines; and

the pixel structure comprises a plurality of pixels, a plurality of pixel units and a plurality of control units, wherein each pixel comprises a plurality of sub-pixels, and each sub-pixel is electrically connected to a corresponding scanning line and a corresponding data line;

a first output line and a second output line substantially parallel to the data lines, wherein one of the data lines most adjacent to the first output line and the other of the data lines most adjacent to the second output line have the same polarity; and

a first sensing device and a second sensing device electrically connected to the first output line and the second output line, respectively.

2. The display panel of claim 1, further comprising:

a system voltage line between the first and second sensing devices and electrically connected to the first and second sensing devices.

3. The display panel of claim 1, further comprising:

a first reference voltage line and a second reference voltage line electrically connected to the first sensing device and the second sensing device, respectively;

a third sensing device electrically connected to the second reference voltage line, wherein the second reference voltage line is located between the second sensing device and the third sensing device; and

a third output line electrically connected to the third sensing device, wherein the one of the data lines most adjacent to the first output line and the other of the data lines most adjacent to the third output line have the same polarity.

4. The display panel of claim 1, wherein adjacent data lines have different polarities.

5. The display panel according to claim 1, wherein the first output line and the second output line overlap the data lines.

6. The display panel of claim 1, further comprising:

a second substrate, wherein the first output line, the second output line, the first sensing device and the second sensing device are located on the second substrate; and

and the display medium layer is positioned between the first substrate and the second substrate.

7. A display panel, comprising:

a pixel array on a first substrate and including;

a plurality of scan lines;

a plurality of data lines interlaced with the scan lines; and

the pixel structure comprises a plurality of pixels, a plurality of pixel units and a plurality of control units, wherein each pixel comprises a plurality of sub-pixels, and each sub-pixel is electrically connected to a corresponding scanning line and a corresponding data line;

a first output line and a second output line substantially parallel to the data lines;

a first sensing device and a second sensing device electrically connected to the first output line and the second output line, respectively, and including a first photosensitive element and a second photosensitive element, respectively;

a system voltage line between the first sensing device and the second sensing device and between the first output line and the second output line, and electrically connected to the first sensing device and the second sensing device; a first reference voltage line and a second reference voltage line respectively located at two sides of the first photosensitive element and the second photosensitive element and respectively electrically connected to the first sensing device and the second sensing device.

8. The display panel according to claim 7, wherein the first output line, the second output line, the system voltage line, the first reference voltage line, and the second reference voltage line overlap and are substantially parallel to the data lines.

9. The display panel of claim 7,

the first sensing device further includes:

a first switch element, wherein a gate of the first switch element, a source of the first switch element and a drain of the first switch element are electrically connected to a control signal line, the first reference voltage line and the first photosensitive element, respectively; and

a second switching element, wherein a gate of the second switching element, a source of the second switching element, and a drain of the second switching element are electrically connected to the first photosensitive element, the system voltage line, and the first output line, respectively; and is

The second sensing device includes:

a third switching element, wherein a gate of the third switching element, a source of the third switching element, and a drain of the third switching element are electrically connected to the control signal line, the second reference voltage line, and the second photosensitive element, respectively; and

and a fourth switching element, wherein a gate of the fourth switching element, a source of the fourth switching element, and a drain of the fourth switching element are electrically connected to the second photosensitive element, the system voltage line, and the second output line, respectively.

10. The display panel of claim 7, further comprising:

a second substrate, wherein the first output line, the second output line, the first sensing device and the second sensing device, the system voltage line, the first reference voltage line and the second reference voltage line are on the second substrate; and

and the display medium layer is positioned between the first substrate and the second substrate.

11. The display panel according to claim 7, wherein a pitch between the first photosensitive elements and the second photosensitive elements is equal to a pitch between the pixels.

Images