CN111129054A

CN111129054A - CMOS image sensor structure and manufacturing method

Info

Publication number: CN111129054A
Application number: CN201911334363.8A
Authority: CN
Inventors: 顾学强; 王玮; 李梦
Original assignee: Shanghai IC R&D Center Co Ltd; Chengdu Light Collector Technology Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd; Chengdu Light Collector Technology Co Ltd
Priority date: 2019-12-23
Filing date: 2019-12-23
Publication date: 2020-05-08
Anticipated expiration: 2039-12-23
Also published as: CN111129054B

Abstract

The invention discloses a CMOS image sensor structure and a manufacturing method. The CMOS image sensor structure includes a pixel unit array area located on a silicon substrate and a peripheral circuit area located around the pixel unit array area. In the silicon substrate of the pixel unit array area A first buried oxide layer is arranged, a second buried oxide layer is arranged in the silicon substrate of the peripheral circuit region, and the depth of the first buried oxide layer from the front surface of the silicon substrate is greater than the depth of the second buried oxide layer from the front surface of the silicon substrate, A silicon epitaxial layer is arranged in the silicon substrate between the first buried oxide layer and the front surface of the silicon substrate, a plurality of photosensitive parts of the pixel unit array are arranged in the silicon epitaxial layer, and the second buried oxide layer and the front surface of the silicon substrate are arranged Peripheral circuits are arranged on the silicon substrate between them. The invention can realize the manufacture of the pixel unit of the back-illuminated image sensor while using the low-power-consumption SOI device in the peripheral circuit, and can avoid the self-doping of impurities and the poor thickness uniformity after thinning easily caused by the conventional back-illuminated process. question.

Description

CMOS image sensor structure and manufacturing method

Technical Field

The invention relates to the technical field of semiconductor processing, in particular to a CMOS image sensor structure and a manufacturing method thereof.

Background

For half a century, the semiconductor industry has been in keeping with moore's law with shrinking transistor sizes, increasing transistor density, and increasing performance. However, as the size of bulk silicon transistor devices in planar structures is getting closer to the physical limit, moore's law is getting closer to its termination; therefore, new structures of semiconductor devices called "non-classical CMOS" have been proposed. These techniques include finfets, carbon nanotubes, Silicon On Insulator (SOI), silicon germanium on insulator (SiGe on insulator), germanium on insulator (GeOI), and the like.

With these new structures, the performance of the semiconductor device can be further improved. Among them, a semiconductor device manufactured on a silicon-on-insulator Substrate (SOI) material has attracted much attention because of its simple process and superior performance.

Semiconductor-on-insulator is a technique in which devices are fabricated in a silicon layer over an insulating layer rather than on a conventional silicon substrate, thereby achieving all-dielectric isolation between different transistors. Compared with the traditional planar bulk silicon process, the SOI technology has the advantages of high speed, low power consumption and high integration level. Compared with a bulk silicon device, the unique insulating buried oxide layer separates the device from the substrate, realizes the full-medium isolation of a single transistor, eliminates the influence (namely the bulk effect) of the substrate on the device, fundamentally eliminates the Latch-Up (Latch-Up) of the bulk silicon CMOS device, inhibits the parasitic effect of the bulk silicon device to a great extent, fully exerts the potential of the silicon integration technology, greatly improves the performance of a circuit, and has the working performance close to an ideal device.

Semiconductor on insulator has shown to be the dominant technology for future SOCs, whether in the size reduction of devices or in radio frequency or low voltage, low power applications. By using the semiconductor-on-insulator technology, a logic circuit, an analog circuit and an RF circuit can be integrated on one chip under the condition of small mutual interference, and the semiconductor-on-insulator technology has a very wide development prospect, so that the semiconductor-on-insulator technology becomes an important technology for researching and developing a large-scale integrated circuit with high speed, low power consumption, high integration degree and high reliability.

Meanwhile, the CMOS image sensor is an important application direction of the CMOS process. The image sensor refers to a device that converts an optical signal into an electrical signal, and a large-scale commercial image sensor chip includes two major types of Charge Coupled Device (CCD) and Complementary Metal Oxide Semiconductor (CMOS) image sensor chips. Compared with the traditional CCD sensor, the CMOS image sensor has the characteristics of low power consumption, low cost, compatibility with the CMOS process and the like, so that the CMOS image sensor is more and more widely applied. At present, CMOS image sensors are widely used in consumer electronics fields such as digital micro cameras (DSCs), cell phone cameras, video cameras, Digital Single Lens Reflex (DSLR), and in automotive electronics, surveillance, biotechnology, and medicine.

In order to achieve efficient photoelectric conversion, the silicon layer for sensitization of the CMOS image sensor is typically several micrometers to several tens of micrometers thick. SOI is used to fabricate devices with silicon layers typically between a few nanometers and hundreds of nanometers thick, well below the thickness required for CMOS image sensor sensing.

Referring to fig. 1, fig. 1 is a schematic diagram of a CMOS transistor fabricated in a conventional silicon-on-insulator substrate. As shown in fig. 1, a silicon-on-insulator (SOI) substrate includes a silicon base 10 at a bottom layer, a device silicon substrate 12 at an upper layer, and a buried oxide layer 11 for isolation between the silicon base 10 and the device silicon substrate 12. A transistor 13 is formed in the device silicon substrate 12 above the buried oxide layer 11. A buried oxide layer 11 between the device silicon substrate 12 and the silicon substrate 10 is usually a silicon dioxide layer, and the thickness of the device silicon substrate 12 is usually between several nanometers and several hundred nanometers. Since the thickness of the silicon substrate 12 for the device is too thin, a pixel cell structure of a CMOS image sensor cannot be fabricated therein. Therefore, SOI silicon wafers are not suitable for fabricating CMOS image sensors.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a conventional back-illuminated CMOS image sensor before thinning. As shown in fig. 2, a highly doped substrate 15 is bonded to the back side of the device silicon layer 14, and the thinning process requires that the highly doped substrate 15 be removed by grinding, wet etching, chemical mechanical polishing, and the like, and finally stop on the device silicon layer 14. Because the doping concentrations of the highly doped substrate 15 and the device silicon layer 14 are different, the corresponding etching rates are also different, so that the etching process is stopped mainly by the difference of the etching rates between the highly doped substrate and the device silicon layer, but the etching rate difference caused by the difference of the doping concentrations is smaller, so that the end point of the etching stop is not easy to control, and the over-etching phenomenon is often caused; meanwhile, the highly doped substrate 15 has a high impurity concentration and is easily separated out in a high-temperature process, so that the characteristics of the device are affected.

Therefore, there is a need to develop a new technology of a CMOS image sensor that can meet different manufacturing requirements of a pixel unit and a peripheral circuit; meanwhile, it is desirable to provide a CMOS image sensor manufacturing technique that does not require the use of a highly doped substrate to achieve backside illuminated process thinning.

Disclosure of Invention

The present invention aims to overcome the above-mentioned defects of the prior art, and provides a CMOS image sensor structure and a manufacturing method thereof, which realizes the manufacturing of a back-illuminated image sensor pixel unit while using a low-power SOI device as a peripheral circuit of the image sensor, thereby achieving the purpose of manufacturing a CMOS image sensor on a silicon-on-insulator substrate material; meanwhile, the problems of self doping and narrow process window formed when a highly doped substrate is used for manufacturing the back-illuminated CMOS image sensor are solved.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a CMOS image sensor structure comprising: the pixel unit array area is positioned on a silicon substrate, the peripheral circuit area is positioned around the pixel unit array area, a first buried oxide layer is arranged in the silicon substrate of the pixel unit array area, a second buried oxide layer is arranged in the silicon substrate of the peripheral circuit area, and the depth of the first buried oxide layer from the front surface of the silicon substrate is greater than the depth of the second buried oxide layer from the front surface of the silicon substrate; the silicon substrate is provided with a first buried oxide layer, a silicon substrate front surface and a second buried oxide layer, wherein a silicon epitaxial layer is arranged in the silicon substrate between the first buried oxide layer and the silicon substrate front surface, a plurality of light sensing parts of a pixel unit array are arranged in the silicon epitaxial layer, and a peripheral circuit is arranged on the silicon substrate between the second buried oxide layer and the silicon substrate front surface.

Furthermore, a groove is formed in the front surface of the silicon substrate of the pixel unit array region, the silicon epitaxial layer is arranged in the groove, and the peripheral circuit is located in the peripheral region outside the groove.

Further, the silicon epitaxial layer has a graded doping concentration towards the front surface of the silicon substrate.

Further, the bottom of the light sensing part penetrates out of the silicon epitaxial layer into the silicon substrate between the silicon epitaxial layer and the first buried oxide layer.

Furthermore, the device also comprises a pixel unit control transistor arranged on the front surface of the silicon epitaxial layer and a peripheral circuit transistor arranged on the silicon substrate between the second buried oxide layer and the front surface of the silicon substrate.

Furthermore, the silicon substrate further comprises a back dielectric layer arranged on the front surface of the silicon substrate and a metal interconnection layer arranged in the back dielectric layer.

Further, the light sensing portion is a photodiode.

A CMOS image sensor structure fabrication method, comprising:

providing a silicon substrate, and forming a groove in the front surface of the silicon substrate; the groove area is defined as a pixel unit array area of the CMOS image sensor, and the peripheral area outside the groove is a peripheral circuit area of the CMOS image sensor;

performing oxygen ion implantation on the whole front surface of the silicon substrate, and forming an oxygen ion layer below the bottom of the groove and in the silicon substrate around the groove;

forming a first buried oxide layer in the silicon substrate below the bottom of the trench and a second buried oxide layer in the silicon substrate around the trench by high temperature annealing;

growing a silicon epitaxial layer in the groove until the groove is filled;

forming a photodiode and a control transistor of a pixel unit on the front surface of the silicon epitaxial layer, and forming a peripheral circuit transistor on the front surface of the silicon substrate above the second buried oxide layer; wherein the bottom of the photodiode is located in the silicon substrate between the silicon epitaxial layer and the first buried oxide layer;

forming a back dielectric layer on the front surface of the whole silicon substrate, and forming a metal interconnection layer in the back dielectric layer;

inverting the front side of the silicon substrate to bond the next dielectric layer with a slide glass;

thinning the back of the whole silicon substrate, and stopping thinning above the first buried oxide layer;

continuously thinning the back of the whole silicon substrate, and removing the first buried oxide layer;

and continuously thinning the back surface of the whole silicon substrate, removing the residual silicon substrate material above the silicon epitaxial layer, and exposing the surfaces of the silicon epitaxial layer and the photodiode.

Further, after the high temperature annealing, the method specifically comprises the following steps:

forming an oxide layer on the whole front surface of the silicon substrate through high-temperature oxidation;

removing the oxide layer on the surface of the inner wall of the groove; and

and after the growth of the silicon epitaxial layer is carried out in the groove, removing the residual oxide layer on the front surface of the silicon substrate outside the groove.

Further, the growing of the silicon epitaxial layer further includes: and doping the silicon epitaxial layer, and enabling the silicon epitaxial layer to have the gradually changed doping concentration towards the surface of the front surface of the silicon substrate.

According to the technical scheme, the embedded oxygen layers (the first embedded oxygen layer and the second embedded oxygen layer) are formed in the pixel unit array region and the peripheral circuit region respectively through one-time oxygen ion implantation and high-temperature annealing, wherein the subsequent SOI transistor is manufactured by utilizing the second embedded oxygen layer of the peripheral circuit region, so that the advantages of low power consumption, high speed and high integration of the SOI transistor can be utilized, the first embedded oxygen layer of the pixel unit array region is utilized as a stop layer of the subsequent silicon substrate back thinning process, the process high selection ratio characteristic between the silicon substrate and the embedded oxygen layer is utilized, the stability and uniformity of the back thinning process are improved, and a back thinning process window is effectively expanded. Meanwhile, the pixel unit array is formed in the epitaxial layer, the doping concentration and the thickness of the epitaxial layer can be independently optimized according to the requirements of the pixel units, the epitaxial layer can be doped into an N type or a P type, the whole epitaxial layer can form a gradually changed potential by using the doping concentration which is gradually changed from top to bottom, so that the charge formed by photoelectric conversion can be transmitted, the image sticking phenomenon can be prevented when an image is formed, and the performance of the CMOS image sensor is improved.

Drawings

Fig. 1 is a schematic diagram of a CMOS transistor structure fabricated in a conventional silicon-on-insulator substrate.

Fig. 2 is a schematic structural diagram of a conventional back-illuminated CMOS image sensor before thinning.

Fig. 3 is a layout diagram of a CMOS image sensor chip.

Fig. 4 is a cross-sectional view of a CMOS image sensor at a location a-B in fig. 3 according to a preferred embodiment of the present invention.

Fig. 5-21 are schematic process steps of a method for manufacturing an image sensor structure according to a preferred embodiment of the invention.

Detailed Description

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.

In the following embodiments of the present invention, please refer to fig. 3-4, fig. 3 is a layout diagram of a CMOS image sensor chip, and fig. 4 is a cross-sectional structure diagram of a CMOS image sensor along a-B position in fig. 3 according to a preferred embodiment of the present invention. As shown in fig. 3, a typical CMOS image sensor chip includes a pixel cell area at the center of the chip and a peripheral circuit area surrounding the pixel cell area. The pixel unit area is provided with a pixel unit array formed by a plurality of densely arranged pixel units, and the pixel unit array is responsible for converting optical signals into electric signals; the peripheral circuit area is provided with various peripheral control and readout circuits including peripheral circuits such as a column-level readout circuit and a row selection control circuit.

Please refer to fig. 4, which shows a cross-sectional structure along the direction "a-B" in fig. 3. The device structure in fig. 4 is inverted compared to fig. 1. As shown in fig. 4, a CMOS image sensor structure of the present invention, built on a conventional silicon substrate 24, comprises: a pixel cell array region on the silicon substrate 24 and a peripheral circuit region around the pixel cell array region.

Please refer to fig. 4. A first buried oxide layer 27 is provided in the silicon substrate 24 of the pixel cell array region; meanwhile, a second buried oxide layer 23 is provided in the silicon substrate 24 of the peripheral circuit region. Wherein the first buried oxide layer 27 and the second buried oxide layer 23 are located at different depths in the silicon substrate 24; specifically, the depth of the first buried oxide layer 27 from the front surface of the silicon substrate 24 is greater than the depth of the second buried oxide layer 23 from the front surface of the silicon substrate 24. Thus, a thick silicon layer suitable for fabricating a photodiode of the pixel cell array for sensing light is formed on the first buried oxide layer 27, and a thin silicon layer 24' suitable for fabricating a peripheral circuit SOI transistor is formed on the second buried oxide layer 23.

A silicon epitaxial layer 28 is further arranged in the structure of the silicon substrate 24 between the first buried oxide layer 27 and the front surface of the silicon substrate 24; a plurality of photodiodes 26 of an array of pixel cells are provided in the silicon epitaxial layer 28. Wherein the bottom of the photodiode 26 is extended out of the bottom of the silicon epitaxial layer 28 to a position in the silicon substrate 24 "between the silicon epitaxial layer 28 and the first buried oxide layer 27.

A peripheral circuit is provided on the silicon substrate 24' between the second buried oxide layer 23 and the front surface of the silicon substrate 24.

Please refer to fig. 4. To form the pixel cell array in a thick silicon layer, a portion of the silicon substrate 24 material above the first buried oxide layer 27 may be removed to form a trench 25 into the silicon substrate 24 from the front surface of the silicon substrate 24 and to fill the trench 25 with a silicon epitaxial layer 28 such that the thickness of the silicon epitaxial layer 28 is equal to the depth of the trench 25. The photodiodes 26 of a plurality of pixel cells are then disposed in the silicon epitaxial layer 28 and form an array of pixel cells. Peripheral circuitry is provided on the silicon substrate 24' in a region surrounding the outer periphery of the trench 25.

Further, the doping concentration and thickness of the silicon epitaxial layer 28 (i.e., the depth of the trench 25) can be optimized according to the requirements of the pixel cell. For example, the epitaxial layer 28 may be doped to be N-type or P-type, and the entire epitaxial layer 28 forms a gradually changing potential by using doping concentration gradually changing from top to bottom, so as to facilitate transmission of charges formed by photoelectric conversion, prevent an image-sticking phenomenon, and improve the performance of the CMOS image sensor.

Please refer to fig. 4. The pixel cell control transistors 29 of the pixel cell array are disposed on the front surface of the silicon epitaxial layer 28; a peripheral circuit transistor 22 is provided on the silicon substrate 24' between the second buried oxide layer 23 and the front surface of the silicon substrate 24.

A conventional back-end dielectric layer 20 may also be provided on the front side of the silicon substrate 24, with a conventional metal interconnect layer 21 provided in the back-end dielectric layer 20.

The subsequent dielectric layer 20 may be bonded to the carrier sheet.

A method for fabricating a CMOS image sensor structure according to the present invention is described in detail with reference to the accompanying drawings.

Referring to fig. 5-21, fig. 5-21 are schematic process steps of a method for manufacturing an image sensor structure according to a preferred embodiment of the invention. As shown in fig. 5-21, a method for fabricating a CMOS image sensor chip structure according to the present invention can be used to fabricate the above-mentioned CMOS image sensor chip structure such as that shown in fig. 4. The invention relates to a manufacturing method of an image sensor structure, which comprises the following steps:

first, as shown in fig. 5, a conventional silicon substrate 24 is used, the thickness of the silicon substrate 24 is typically around 700 μm, and the doping type may be N-type or P-type.

Next, as shown in fig. 6, the photoresist in the pixel cell array region may be removed through a photolithography and development process, leaving the photoresist 30 in the peripheral circuit region.

Subsequently, as shown in fig. 7, a portion of the silicon substrate 24 material in the pixel cell area is removed by a dry etching process, and a trench 25 is formed in the front surface of the silicon substrate 24 in the area where the pixel cell array is located. The peripheral region outside the trench 25 becomes a peripheral circuit region of the CMOS image sensor, and the silicon substrate 24 of the peripheral circuit region is left protected by the photoresist.

The depth of the trench 25 may be between several micrometers and several tens of micrometers, and the specific depth thereof may vary according to different requirements of the pixel unit.

Next, as shown in fig. 8, oxygen ion implantation is performed on the entire front surface of the silicon substrate 24 using an ion implantation process, and the implantation depth may be several nanometers to several hundred nanometers. After the implantation is completed, oxygen ion layers 27 ', 23' are formed in the silicon substrate 24 under the bottom of the trench 25 in the region where the pixel cell array is located and in the peripheral circuit region around the trench 25.

Subsequently, as shown in fig. 9, by high temperature annealing, chemical reaction between oxygen ions and silicon atoms in the silicon layer is achieved, and silicon dioxide, i.e., buried

oxide layers

27, 23, are generated. Thereby forming a first buried oxide layer 27 in the silicon substrate 24 under the bottom of the trench 25 and a second buried oxide layer 23 in the silicon substrate 24 around the trench 25.

Then, as shown in fig. 10, an oxide layer 31 may be formed on the entire front surface of the silicon substrate 24 by high temperature oxidation to repair surface damage and defects caused by etching the trench 25 in the silicon layer, thereby ensuring the quality of the subsequent epitaxial layer 28 growth.

Next, as shown in fig. 11, the photoresist in the pixel unit region is removed by photolithography and development processes, the oxide layer 31 in the pixel unit region is exposed, and the photoresist 32 in the peripheral circuit region is remained.

Next, as shown in fig. 12, the oxide layer 31 on the inner wall surface of the trench 25 may be removed by wet etching, exposing the silicon layer under the sidewall and the bottom of the trench 25. The oxide layer 31 on the peripheral circuit region is retained due to masking with a photoresist.

Subsequently, as shown in fig. 13, growth of a silicon epitaxial layer 28 is performed within the trench 25 by a silicon epitaxial process until the trench 25 is filled. The doping type of the epitaxial layer 28 can be an N type or a P type, and the epitaxial layer 28 can be doped with gradually changing concentrations from the bottom to the surface through adjustment of a process menu, so that a built-in potential difference can be formed in a subsequent pixel unit, the transport of photo-generated charges can be realized, and image ghosting can be prevented.

Then, as shown in fig. 14, the remaining oxide layer 31 on the front surface of the silicon substrate 24 in the peripheral circuit region other than the trench 25 can be removed by using a wet etching process.

Next, as shown in fig. 15, by using a semiconductor manufacturing process, a photodiode 26 and a control transistor 29 such as a transfer transistor of a pixel cell are formed on the front surface of a silicon epitaxial layer 28 of a pixel cell region, and an SOI transistor (peripheral circuit transistor 22) is formed on the front surface of a silicon substrate 24' of a peripheral circuit region above the second buried oxide layer 23. The implantation depth of the photodiode 26 needs to be greater than the thickness of the epitaxial layer 28 and less than the depth of the first buried oxide layer 27, so that the bottom of the formed photodiode 26 is located in the silicon substrate 24 ″ between the silicon epitaxial layer 28 and the first buried oxide layer 27.

Next, as shown in fig. 16, a back-end dielectric layer 20 is formed on the entire front surface of the silicon substrate 24, and a metal interconnection layer 21 is formed in the back-end dielectric layer 20 by a back-end process.

Then, as shown in fig. 17, the silicon substrate 24 is turned upside down, and the subsequent dielectric layer 20 is bonded to a carrier.

Next, as shown in fig. 18, the entire back surface of the silicon substrate 24 can be thinned by grinding, wet etching, and chemical mechanical polishing, and the thinning process will automatically stop over the first buried oxide layer 27 due to the difference in removal rate between the silicon substrate 24 and the first buried oxide layer 27. Therefore, the first buried oxide layer 27 formed in the silicon substrate 24 can be used as a stop layer when the back surface of the silicon substrate 24 is thinned by utilizing the high selectivity characteristic of the process between the silicon substrate and the buried oxide layer, so that the stability and the uniformity of the back surface thinning process are improved, and the back surface thinning process window is effectively expanded.

Subsequently, as shown in fig. 19, the entire back surface of the silicon substrate 24 is thinned by wet etching or chemical mechanical polishing, and the first buried oxide layer 27 in the entire pixel unit region is removed. Due to the difference in removal rate between the first buried oxide layer 27 and the silicon substrate 24, the thinning process will automatically stop on the remaining silicon substrate 24 "between the first buried oxide layer 27 and the trench 25, exposing the photosensitive area of the photodiode 26.

Next, as shown in fig. 20, the remaining thin layer of silicon substrate 24 "above the epitaxial layer 28 is removed by wet etching or chemical mechanical polishing to thin the entire back surface of the silicon substrate 24. Since the thickness of the thin silicon substrate 24 "can be precisely controlled by the energy of the oxygen ion implantation, the process can be time controlled, i.e., the residual silicon substrate 24" between the first buried oxide layer 27 and the epitaxial layer 28 can be removed by wet etching or chemical mechanical polishing for a fixed time. Eventually exposing the surface of the epitaxial layer 28 and photodiode 26 throughout the pixel cell area.

Finally, as shown in fig. 21, a conventional backside illumination process may be further used to form other structures of the CMOS image sensor, such as an anti-reflection layer 33 and a metal light blocking layer 34, over the pixel unit.

The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.

Claims

1. A CMOS image sensor structure, characterized by comprising: a pixel unit array area located on a silicon substrate and a peripheral circuit area located around the pixel unit array area, the silicon substrate of the pixel unit array area A first buried oxide layer is arranged in the bottom, a second buried oxide layer is arranged in the silicon substrate of the peripheral circuit region, and the depth of the first buried oxide layer from the front surface of the silicon substrate is greater than that of the first buried oxide layer. The depth of the two buried oxide layers from the front surface of the silicon substrate; wherein, a silicon epitaxial layer is provided in the silicon substrate between the first buried oxide layer and the front surface of the silicon substrate, and the silicon epitaxial layer is A plurality of photosensitive parts of a pixel unit array are arranged in the layer, and peripheral circuits are arranged on the silicon substrate between the second buried oxide layer and the front surface of the silicon substrate.

2 . The CMOS image sensor structure according to claim 1 , wherein a trench is provided in the front surface of the silicon substrate in the pixel unit array region, and the silicon epitaxial layer is provided in the trench, 3 . The peripheral circuit is located in a peripheral area outside the trench.

3. The CMOS image sensor structure according to claim 1 or 2, wherein the silicon epitaxial layer has a graded doping concentration toward the front surface of the silicon substrate.

4 . The CMOS image sensor structure according to claim 1 , wherein the bottom of the photosensitive portion penetrates from the silicon epitaxial layer to between the silicon epitaxial layer and the first buried oxide layer. 5 . of the silicon substrate.

5. The CMOS image sensor structure according to claim 1 or 2, further comprising a pixel unit control transistor disposed on the front surface of the silicon epitaxial layer, and a pixel unit control transistor disposed on the second buried oxide layer and the second buried oxide layer. peripheral circuit transistors on the silicon substrate between the front surfaces of the silicon substrate.

6 . The CMOS image sensor structure according to claim 1 or 2 , further comprising a back-end dielectric layer provided on the front surface of the silicon substrate, and a metal interconnection layer provided in the back-end dielectric layer. 7 . Connect layers.

7. The CMOS image sensor structure according to claim 1, wherein the photosensitive part is a photodiode.

8. A method for fabricating a CMOS image sensor structure, comprising the following steps:

A silicon substrate is provided, and a trench is formed in the front surface of the silicon substrate; wherein, the trench area is defined as the pixel unit array area of the CMOS image sensor, and the surrounding area outside the trench is the periphery of the CMOS image sensor circuit area;

performing oxygen ion implantation on the entire front surface of the silicon substrate to form an oxygen ion layer in the silicon substrate under the trench bottom and around the trench;

By high temperature annealing, a first buried oxide layer is formed in the silicon substrate under the trench bottom, and a second buried oxide layer is formed in the silicon substrate around the trench;

growing a silicon epitaxial layer in the trench until the trench is filled;

Photodiodes and control transistors of pixel units are formed on the front side of the silicon epitaxial layer, and peripheral circuit transistors are formed on the front side of the silicon substrate above the second buried oxide layer; wherein the photodiodes formed are formed The bottom is located in the silicon substrate between the silicon epitaxial layer and the first buried oxide layer;

forming a back-end dielectric layer on the entire front side of the silicon substrate, and forming a metal interconnect layer in the back-end dielectric layer;

inverting the front side of the silicon substrate, so that the back-channel dielectric layer is bonded to a carrier;

thinning the entire backside of the silicon substrate, and stopping the thinning above the first buried oxide layer;

Continue to thin the entire backside of the silicon substrate to remove the first buried oxide layer;

Continue to thin the entire backside of the silicon substrate, remove the remaining silicon substrate material above the silicon epitaxial layer, and expose the silicon epitaxial layer and the surface of the photodiode.

9. The method for fabricating a CMOS image sensor structure according to claim 8, wherein after the high temperature annealing, the method further comprises:

forming an oxide layer on the entire front surface of the silicon substrate by high temperature oxidation;

removing the oxide layer on the surface of the inner wall of the trench; and

After the silicon epitaxial layer is grown in the trench, the remaining oxide layer on the front surface of the silicon substrate outside the trench is removed.

10. The method for fabricating a CMOS image sensor structure according to claim 8 or 9, wherein when the silicon epitaxial layer is grown, the method further comprises: doping the silicon epitaxial layer, and making the silicon epitaxial layer The epitaxial layer has a graded doping concentration towards the front surface of the silicon substrate.