CN111129054B - A kind of CMOS image sensor structure and manufacturing method - Google Patents

Abstract

The invention discloses a CMOS image sensor structure and a manufacturing method. The CMOS image sensor structure includes a pixel unit array area on a silicon substrate and a peripheral circuit area located around the pixel unit array area. The silicon substrate in the pixel unit array area A first buried oxide layer is provided, a second buried oxide layer is provided in the silicon substrate in the peripheral circuit area, the depth of the first buried oxide layer from the front side of the silicon substrate is greater than the depth of the second buried oxide layer from the front side of the silicon substrate, A silicon epitaxial layer is arranged in the silicon substrate between the first buried oxide layer and the front surface of the silicon substrate, and a plurality of photosensitive parts of the pixel unit array are arranged in the silicon epitaxial layer, and the second buried oxide layer is connected with the front surface of the silicon substrate. Peripheral circuits are provided on the silicon substrate between them. The present invention can realize the manufacture of back-illuminated image sensor pixel units while using low-power SOI devices in peripheral circuits, and can avoid the problems of impurity self-doping and poor thickness uniformity after thinning that are easily caused by conventional back-illuminated processes question.

Description

A kind of CMOS image sensor structure and manufacturing method

technical field

The invention relates to the technical field of semiconductor processing, in particular to a CMOS image sensor structure and a manufacturing method.

Background technique

For half a century, the semiconductor industry has been shrinking transistor size, increasing transistor density, and improving performance in accordance with Moore's Law. However, as the size of bulk silicon transistor devices with planar structure is getting closer and closer to the physical limit, Moore's law is getting closer and closer to its end; therefore, some new structures of semiconductor devices called "non-classical CMOS" have been proposed . These technologies include FinFET, carbon nanotubes, silicon on insulator (silicon on insulator, SOI), silicon germanium on insulator (SiGe on insulator, SiGeOI) and germanium on insulator (Ge on insulator, GeOI), etc.

Through these new structures, the performance of semiconductor devices can be further improved. Among them, semiconductor devices fabricated on silicon-on-insulator (SOI) materials have attracted widespread attention due to their simple process and superior performance.

Semiconductor-on-insulator is a technology that fabricates devices in a silicon layer above an insulating layer instead of on a traditional silicon substrate, thereby achieving full dielectric isolation between different transistors. Compared with the traditional planar bulk silicon process, SOI technology has the advantages of high speed, low power consumption and high integration. Compared with bulk silicon devices, its unique insulating buried oxide layer separates the device from the substrate, realizes full dielectric isolation of a single transistor, eliminates the influence of the substrate on the device (that is, the body effect), and fundamentally eliminates the bulk The latch-up of silicon CMOS devices suppresses the parasitic effects of bulk silicon devices to a large extent, fully exploits the potential of silicon integration technology, greatly improves the performance of the circuit, and the working performance is close to that of ideal devices.

Semiconductor-on-insulator, whether in terms of device size reduction, radio frequency, or low-voltage, low-power applications, shows that it will be the main technology of future SOCs. Using semiconductor-on-insulator technology, logic circuits, analog circuits, and RF circuits can be integrated on one chip with little mutual interference, which has very broad development prospects. An important technology for integrated and high-reliability large-scale integrated circuits.

At the same time, the CMOS image sensor is an important application direction of the CMOS process. An image sensor refers to a device that converts optical signals into electrical signals. Large-scale commercial image sensor chips include charge-coupled device (CCD) and complementary metal-oxide semiconductor (CMOS) image sensor chips. Compared with traditional CCD sensors, CMOS image sensors have the characteristics of low power consumption, low cost and compatibility with CMOS technology, so they are more and more widely used. Now, CMOS image sensors are not only used in consumer electronics fields such as miniature digital cameras (DSCs), mobile phone cameras, video cameras, and digital single-lens reflex cameras (DSLRs), but also in automotive electronics, monitoring, biotechnology, and medicine.

In order to realize effective photoelectric conversion, the photosensitive silicon layer thickness of the CMOS image sensor is usually several microns to tens of microns. However, the thickness of the silicon layer used in SOI to manufacture devices is usually between a few nanometers and hundreds of nanometers, which is much lower than the thickness required for CMOS image sensors to sense light.

Please refer to FIG. 1 , which is a schematic structural diagram of a CMOS transistor manufactured in a conventional silicon-on-insulator substrate. As shown in FIG. 1 , a silicon-on-insulator substrate (SOI) includes a silicon substrate 10 at the bottom layer, a silicon substrate 12 for devices on the upper layer, and an isolation layer between the silicon substrate 10 and the silicon substrate 12 for devices. Buried oxide layer 11. The transistor 13 is formed in the device silicon substrate 12 above the buried oxide layer 11 . The buried oxide layer 11 between the silicon substrate 12 for the device and the silicon substrate 10 is usually a silicon dioxide layer, and the thickness of the silicon substrate 12 for the device is usually between several nanometers and hundreds of nanometers. Since the device silicon substrate 12 is too thin, the pixel unit structure of the CMOS image sensor cannot be fabricated therein. Therefore, SOI silicon wafers are not suitable for manufacturing CMOS image sensors.

Please refer to FIG. 2 , which is a schematic structural diagram of a conventional back-illuminated CMOS image sensor before thinning. As shown in FIG. 2, a highly doped substrate 15 is bonded to the back of the device silicon layer 14. The thinning process requires the use of grinding, wet etching and chemical mechanical polishing to remove the highly doped substrate 15. Finally, it stops on the silicon layer 14 for devices. Since the doping concentrations of the highly doped substrate 15 and the device silicon layer 14 are different, their corresponding etching rates are also different, so the etching process is mainly stopped by the different etching rates between the two, but the difference in doping concentration The resulting corrosion rate difference is small, so the end point of the corrosion stop is not easy to control, often causing over-corrosion phenomenon; at the same time, the impurity concentration in the highly doped substrate 15 is relatively high, and it is easy to precipitate during the high-temperature process, thereby affecting device characteristics.

Therefore, it is necessary to develop a new technology for CMOS image sensors that can take into account the different manufacturing requirements of pixel units and peripheral circuits; at the same time, it is necessary to provide a CMOS image sensor manufacturing technology that does not need to use highly doped substrates to achieve back-illuminated process thinning .

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned defects that exist in the prior art, provide a kind of CMOS image sensor structure and manufacturing method, realize the manufacture of back-illuminated image sensor pixel unit while using low power consumption SOI device in the peripheral circuit of image sensor, The purpose of manufacturing a CMOS image sensor on a silicon-on-insulator substrate material is achieved; at the same time, the problems of self-doping and narrow process window formed when a back-illuminated CMOS image sensor is manufactured using a highly doped substrate are avoided.

To achieve the above object, the technical scheme of the present invention is as follows:

A CMOS image sensor structure, comprising: a pixel unit array area located on a silicon substrate and a peripheral circuit area located around the pixel unit array area, the silicon substrate of the pixel unit array area is provided with a first A buried oxide layer, the silicon substrate in the peripheral circuit area is provided with a second buried oxide layer, and the depth of the first buried oxide layer from the front side of the silicon substrate is greater than the distance from the second buried oxide layer. The depth of the front side of the silicon substrate; wherein, a silicon epitaxial layer is arranged in the silicon substrate between the first buried oxide layer and the front surface of the silicon substrate, and a pixel unit is arranged in the silicon epitaxial layer For multiple photosensitive parts of the array, peripheral circuits are provided on the silicon substrate between the second buried oxide layer and the front surface of the silicon substrate.

Further, a trench is provided in the front surface of the silicon substrate in the region of the pixel unit array, the silicon epitaxial layer is disposed in the trench, and the peripheral circuit is located in a surrounding area outside the trench.

Further, the silicon epitaxial layer has a gradually changing doping concentration toward the front surface of the silicon substrate.

Further, the bottom of the photosensitive part passes through the silicon epitaxial layer into the silicon substrate between the silicon epitaxial layer and the first buried oxide layer.

Further, it also includes a pixel unit control transistor disposed on the front surface of the silicon epitaxial layer, and a peripheral transistor disposed on the silicon substrate between the second buried oxide layer and the front surface of the silicon substrate. circuit transistors.

Further, it also includes a back-end dielectric layer arranged on the front surface of the silicon substrate, and a metal interconnection layer arranged in the back-end dielectric layer.

Further, the photosensitive part is a photodiode.

A method for manufacturing a CMOS image sensor structure, comprising the following steps:

A silicon substrate is provided, and a groove is formed in the front surface of the silicon substrate; wherein, the groove area is defined as the pixel unit array area of the CMOS image sensor, and the surrounding area outside the groove is the periphery of the CMOS image sensor circuit area;

Performing oxygen ion implantation on the entire front side of the silicon substrate to form an oxygen ion layer in the silicon substrate below the bottom of the trench and around the trench;

forming a first buried oxide layer in the silicon substrate below the bottom of the trench by high temperature annealing, and forming a second buried oxide layer in the silicon substrate around the trench;

growing a silicon epitaxial layer in the trench until the trench is filled;

A photodiode and a control transistor of a pixel unit are formed on the front surface of the silicon epitaxial layer, and a peripheral circuit transistor is formed on the front surface of the silicon substrate above the second buried oxide layer; wherein the formed photodiode The bottom of is located in the silicon substrate between the silicon epitaxial layer and the first buried oxide layer;

forming a back-end dielectric layer on the entire front side of the silicon substrate, and forming a metal interconnection layer in the back-end dielectric layer;

Turning the silicon substrate upside down so that the subsequent dielectric layer is bonded to a carrier;

Thinning the entire backside of the silicon substrate, and stopping the thinning above the first buried oxide layer;

Continue to thin the entire backside of the silicon substrate to remove the first buried oxide layer;

Continue to thin the entire backside of the silicon substrate, remove the remaining silicon substrate material above the silicon epitaxial layer, and expose the silicon epitaxial layer and the surface of the photodiode.

Further, after high temperature annealing, it specifically includes:

forming an oxide layer on the entire front surface of the silicon substrate by high temperature oxidation;

removing the oxide layer on the inner wall surface of the trench; and

After the silicon epitaxial layer is grown in the trench, the remaining oxide layer on the front surface of the silicon substrate outside the trench is removed.

Further, when growing the silicon epitaxial layer, it also includes: doping the silicon epitaxial layer, and making the silicon epitaxial layer have a gradually changing doping concentration toward the front surface of the silicon substrate.

It can be seen from the above technical scheme that the present invention forms buried oxide layers (first buried oxide layer and second buried oxide layer) in the pixel unit array region and the peripheral circuit region and respectively through one oxygen ion implantation and high temperature annealing, wherein , using the second buried oxide layer in the peripheral circuit area to manufacture subsequent SOI transistors, so that the advantages of low power consumption, high speed and high integration of SOI transistors can be used, and the first buried oxide layer in the pixel unit array area is used as a subsequent silicon substrate The stop layer of the bottom and back thinning process utilizes the high process selectivity between the silicon substrate and the buried oxide layer to improve the stability and uniformity of the back thinning process and effectively expand the back thinning process window. At the same time, the pixel unit array of the present invention is formed in the epitaxial layer, and the doping concentration and thickness of the epitaxial layer can be independently optimized according to the requirements of the pixel unit, and the epitaxial layer can be doped into N-type or P-type, and the entire epitaxial layer uses The gradually changing doping concentration from top to bottom can form a gradually changing potential, which is conducive to the transmission of charges formed by photoelectric conversion, and can prevent image sticking when forming an image, thus improving the performance of the CMOS image sensor.

Description of drawings

FIG. 1 is a schematic diagram of the structure of a CMOS transistor fabricated in a conventional silicon-on-insulator substrate.

FIG. 2 is a schematic structural diagram of a conventional back-illuminated CMOS image sensor before thinning.

FIG. 3 is a schematic layout diagram of a CMOS image sensor chip.

FIG. 4 is a schematic cross-sectional structure diagram of a CMOS image sensor according to a preferred embodiment of the present invention along the position A-B in FIG. 3 .

5-21 are schematic diagrams of process steps of a method for manufacturing an image sensor structure according to a preferred embodiment of the present invention.

Detailed ways

The specific embodiment of the present invention will be further described in detail below in conjunction with the accompanying drawings.

It should be noted that, in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly show the structure of the present invention for the convenience of description, the structures in the drawings are not drawn according to the general scale, and are drawn Partial magnification, deformation and simplification are included, therefore, it should be avoided to be interpreted as a limitation of the present invention.

In the following specific embodiments of the present invention, please refer to Fig. 3-Fig. 4, Fig. 3 is a schematic layout diagram of a CMOS image sensor chip, and Fig. 4 is a diagram of a preferred embodiment of the present invention along the position A-B in Fig. 3 Schematic diagram of a cross-sectional structure of a CMOS image sensor. As shown in FIG. 3 , a CMOS image sensor chip generally includes a pixel unit area located in the center of the chip and peripheral circuit areas surrounding the pixel unit area. Among them, the pixel unit area is provided with a pixel unit array composed of densely arranged multiple pixel units, and the pixel unit array is responsible for converting optical signals into electrical signals; the peripheral circuit area is provided with various peripheral control and readout circuits, including columns Peripheral circuits such as level readout circuit and row selection control circuit.

Please refer to FIG. 4 , which shows a cross-sectional structure along the direction "A-B" in FIG. 3 . Compared with Fig. 1, the device structure in Fig. 4 is inverted. As shown in FIG. 4, a CMOS image sensor structure of the present invention is built on a conventional silicon substrate 24, including: a pixel unit array area on the silicon substrate 24 and a peripheral circuit area around the pixel unit array area .

Please refer to Figure 4. A first buried oxide layer 27 is provided in the silicon substrate 24 in the pixel unit array area; meanwhile, a second buried oxide layer 23 is provided in the silicon substrate 24 in the peripheral circuit area. Wherein, the first buried oxide layer 27 and the second buried oxide layer 23 are located at different depths in the silicon substrate 24; specifically, the depth of the first buried oxide layer 27 from the front side of the silicon substrate 24 is greater than that of the second buried oxide layer 23 The depth from the front side of the silicon substrate 24 . In this way, on the first buried oxide layer 27, a thick silicon layer suitable for manufacturing a pixel unit array for photosensitive photodiodes is formed, and on the second buried oxide layer 23, a silicon layer suitable for manufacturing peripheral circuit SOI transistors is formed. Thin silicon layer 24'.

A silicon epitaxial layer 28 is further provided in the structure of the silicon substrate 24 between the first buried oxide layer 27 and the front surface of the silicon substrate 24 ; a plurality of photodiodes 26 of a pixel unit array are provided in the silicon epitaxial layer 28 . Wherein, the bottom of the photodiode 26 penetrates from the bottom of the silicon epitaxial layer 28 until extending to a position in the silicon substrate 24 ″ between the silicon epitaxial layer 28 and the first buried oxide layer 27 .

Peripheral circuits are provided on the silicon substrate 24' between the second buried oxide layer 23 and the front surface of the silicon substrate 24.

Please refer to Figure 4. In order to form a pixel unit array in a thick silicon layer, part of the material of the silicon substrate 24 above the first buried oxide layer 27 can be removed, thereby forming a trench 25 from the front surface of the silicon substrate 24 into the silicon substrate 24, And the silicon epitaxial layer 28 is filled in the trench 25 so that the thickness of the silicon epitaxial layer 28 is equal to the depth of the trench 25 . Then, a plurality of photodiodes 26 of pixel units are arranged in the silicon epitaxial layer 28 to form a pixel unit array. The peripheral circuits are arranged on the silicon substrate 24' in the peripheral area outside the trench 25.

Further, the doping concentration and thickness of the silicon epitaxial layer 28 (ie, the depth of the trench 25 ) can be optimized according to the requirements of the pixel unit. For example, the epitaxial layer 28 can be doped into N-type or P-type, and the entire epitaxial layer 28 uses a gradually changing doping concentration from top to bottom to form a gradually changing potential, thereby facilitating the transmission of charges formed by photoelectric conversion and preventing the formation of The afterimage phenomenon of the image improves the performance of the CMOS image sensor.

Please refer to Figure 4. The pixel unit control transistor 29 of the pixel unit array is arranged on the front surface of the silicon epitaxial layer 28; the peripheral circuit transistor 22 is arranged on the silicon substrate 24' between the second buried oxide layer 23 and the front surface of the silicon substrate 24.

A conventional back-end dielectric layer 20 may also be provided on the front side of the silicon substrate 24 , and a conventional metal interconnection layer 21 is provided in the back-end dielectric layer 20 .

The subsequent dielectric layer 20 can be bonded to the carrier.

A method for manufacturing a CMOS image sensor structure of the present invention will be described in detail below with reference to specific embodiments and accompanying drawings.

Please refer to FIG. 5-FIG. 21. FIG. 5-FIG. 21 are schematic diagrams of process steps of a method for manufacturing an image sensor structure according to a preferred embodiment of the present invention. As shown in FIGS. 5-21 , a method for manufacturing a CMOS image sensor chip structure according to the present invention can be used to manufacture the above-mentioned CMOS image sensor chip structure such as in FIG. 4 . A method for manufacturing an image sensor structure of the present invention may include the following steps:

First, as shown in FIG. 5 , a conventional silicon substrate 24 is used, the thickness of the silicon substrate 24 is usually about 700 microns, and the doping type can be N-type or P-type.

Next, as shown in FIG. 6 , the photoresist in the pixel unit array area can be removed by photolithography and developing processes, and the photoresist 30 in the peripheral circuit area remains.

Subsequently, as shown in FIG. 7 , a part of the material of the silicon substrate 24 in the pixel unit area is removed through a dry etching process, and a groove 25 is formed in the front surface of the silicon substrate 24 in the area where the pixel unit array is located. The surrounding area outside the trench 25 becomes the peripheral circuit area of the CMOS image sensor, and the silicon substrate 24 in the peripheral circuit area is reserved due to the photoresist protection.

The depth of the groove 25 can be between several micrometers and tens of micrometers, and the specific depth can be changed according to different requirements of the pixel unit.

Next, as shown in FIG. 8 , the entire front surface of the silicon substrate 24 is implanted with oxygen ions using an ion implantation process, and the implantation depth can be several nanometers to hundreds of nanometers. After the implantation is completed, oxygen ion layers 27', 23' are formed in the silicon substrate 24 under the bottom of the trench 25 in the region where the pixel unit array is located and in the peripheral circuit region around the trench 25.

Subsequently, as shown in FIG. 9 , through high-temperature annealing, a chemical reaction between oxygen ions in the silicon layer and silicon atoms is realized to form silicon dioxide, that is, buried oxide layers 27 and 23 . Thus, a first buried oxide layer 27 is formed in the silicon substrate 24 below the bottom of the trench 25 , and a second buried oxide layer 23 is formed in the silicon substrate 24 around the trench 25 .

Then, as shown in FIG. 10 , an oxide layer 31 can be formed on the front surface of the entire silicon substrate 24 by high-temperature oxidation to repair the surface damage and defects caused when the silicon layer is etched with the trench 25, ensuring that the subsequent epitaxial layer 28 The quality of growth.

Next, as shown in FIG. 11 , the photoresist in the pixel unit area is removed through photolithography and development processes, exposing the oxide layer 31 in the pixel unit area, and the photoresist 32 in the peripheral circuit area remains.

Again, as shown in FIG. 12 , the oxide layer 31 on the inner wall surface of the trench 25 can be removed by wet etching, exposing the silicon layer below the sidewall and bottom of the trench 25 . The oxide layer 31 on the peripheral circuit area remains due to the masking of the photoresist.

Subsequently, as shown in FIG. 13 , a silicon epitaxial layer 28 is grown in the trench 25 through a silicon epitaxial process until the trench 25 is filled. Wherein, the doping type of the epitaxial layer 28 can be N-type or P-type, which can be adjusted through the process menu, and the concentration of the epitaxial layer 28 is gradually doped from the bottom to the surface, so as to facilitate the formation of a built-in potential difference in subsequent pixel units. Realize the transport of photogenerated charges and prevent image sticking.

Then, as shown in FIG. 14 , the remaining oxide layer 31 on the front surface of the silicon substrate 24 in the peripheral circuit area outside the trench 25 can be removed by using a wet etching process.

Next, as shown in FIG. 15 , by using a semiconductor manufacturing process, a control transistor 29 such as a photodiode 26 and a transfer transistor of the pixel unit is formed on the front surface of the silicon epitaxial layer 28 in the pixel unit region, and a peripheral area above the second buried oxide layer 23 is formed. SOI transistors (peripheral circuit transistors 22) are formed on the front side of the silicon substrate 24' in the circuit region. Wherein, the implantation depth of the photodiode 26 needs to be greater than the thickness of the epitaxial layer 28 and less than the depth of the first buried oxide layer 27, so that the bottom of the formed photodiode 26 is located in the silicon between the silicon epitaxial layer 28 and the first buried oxide layer 27. Substrate 24".

Again, as shown in FIG. 16 , the back-end dielectric layer 20 is formed on the entire front surface of the silicon substrate 24 by the back-end process, and the metal interconnection layer 21 is formed in the back-end dielectric layer 20 .

Then, as shown in FIG. 17 , the silicon substrate 24 is turned upside down, so that the subsequent dielectric layer 20 is bonded to a carrier.

Next, as shown in FIG. 18 , the back surface of the entire silicon substrate 24 can be thinned by grinding, wet etching and chemical mechanical polishing. Due to the difference in removal rate between the silicon substrate 24 and the first buried oxide layer 27 difference, the thinning process will automatically stop above the first buried oxide layer 27 . Therefore, the high selectivity of the process between the silicon substrate and the buried oxide layer can be utilized, and the first buried oxide layer 27 formed in the silicon substrate 24 can be used as a stop layer when the back side of the silicon substrate 24 is thinned, thereby improving The stability and uniformity of the back thinning process are improved, and the window of the back thinning process is effectively expanded.

Subsequently, as shown in FIG. 19 , the back surface of the entire silicon substrate 24 is continuously thinned by wet etching or chemical mechanical polishing, and the first buried oxide layer 27 in the entire pixel unit area is removed. Due to the difference in removal rate between the first buried oxide layer 27 and the silicon substrate 24, the thinning process will automatically stop on the remaining silicon substrate 24" between the first buried oxide layer 27 and the trench 25, exposing the photoelectric The photosensitive area of diode 26.

Next, as shown in FIG. 20 , the backside of the entire silicon substrate 24 is continuously thinned by processes such as wet etching or chemical mechanical polishing, and the remaining thin silicon substrate 24 ″ above the epitaxial layer 28 is removed. Due to this The thickness of the thin-layer silicon substrate 24" can be precisely controlled by the energy during oxygen ion implantation, so the process can be controlled by time, that is, through wet etching or chemical mechanical polishing for a fixed time, the first buried oxide layer 27 can be The residual silicon substrate 24" between the epitaxial layer 28 and the epitaxial layer 28 is removed. Finally, the epitaxial layer 28 and the surface of the photodiode 26 in the entire pixel unit area can be exposed.

Finally, as shown in FIG. 21 , other structures of the CMOS image sensor such as the anti-reflection layer 33 and the metal light-blocking layer 34 can be formed on the pixel unit by further using a conventional back-illumination process.

The above are only preferred embodiments of the present invention, and the embodiments are not intended to limit the protection scope of the present invention. Therefore, all equivalent structural changes made by using the description and accompanying drawings of the present invention should be included in the protection of the present invention in the same way. within range.

Claims (10)

1. A CMOS image sensor structure, comprising: a pixel unit array region positioned on a silicon substrate and a peripheral circuit region positioned around the pixel unit array region, wherein a first oxygen-buried layer is arranged in the silicon substrate of the pixel unit array region to serve as a stop layer of a subsequent silicon substrate back thinning process, a second oxygen-buried layer is arranged in the silicon substrate of the peripheral circuit region to manufacture a subsequent SOI transistor, and the depth of the first oxygen-buried layer from the front surface of the silicon substrate is larger than that of the second oxygen-buried layer from the front surface of the silicon substrate; the silicon substrate between the first oxygen-buried layer and the front surface of the silicon substrate is internally provided with a silicon epitaxial layer, the silicon epitaxial layer is internally provided with a plurality of photosensitive parts of a pixel unit array, and a peripheral circuit is arranged on the silicon substrate between the second oxygen-buried layer and the front surface of the silicon substrate.

2. The CMOS image sensor structure according to claim 1, wherein a trench is provided in the front surface of the silicon substrate of the pixel cell array region, the silicon epitaxial layer is provided in the trench, and the peripheral circuit is located in a peripheral region outside the trench.

3. The CMOS image sensor structure of claim 1 or 2, wherein the silicon epitaxial layer has a graded doping concentration toward the front surface of the silicon substrate.

4. The CMOS image sensor structure according to claim 1 or 2, wherein the bottom of the light-sensing portion protrudes from the silicon epitaxial layer into the silicon substrate between the silicon epitaxial layer and the first buried oxide layer.

5. The CMOS image sensor structure according to claim 1 or 2, further comprising a pixel cell control transistor provided on a front surface of the silicon epitaxial layer, and a peripheral circuit transistor provided on the silicon substrate between the second buried oxide layer and the front surface of the silicon substrate.

6. The CMOS image sensor structure of claim 1 or 2, further comprising a back-end dielectric layer disposed on the front-end of the silicon substrate, and a metal interconnect layer disposed in the back-end dielectric layer.

7. The CMOS image sensor structure of claim 1, wherein the photosensitive portion is a photodiode.

8. A method of fabricating a CMOS image sensor structure, comprising the steps of:

providing a silicon substrate, and forming a groove in the front surface of the silicon substrate; defining the groove area as a pixel unit array area of the CMOS image sensor, wherein the peripheral area outside the groove is a peripheral circuit area of the CMOS image sensor;

oxygen ion implantation is carried out on the whole front surface of the silicon substrate, and an oxygen ion layer is formed in the silicon substrate below the bottom of the groove and around the groove;

forming a first buried oxide layer in the silicon substrate below the bottom of the trench and forming a second buried oxide layer in the silicon substrate around the trench by high temperature annealing;

growing a silicon epitaxial layer in the groove until the groove is filled;

forming a photodiode and a control transistor of a pixel unit on the front surface of the silicon epitaxial layer, and forming a peripheral circuit transistor on the front surface of the silicon substrate above the second buried oxide layer; wherein a bottom of the formed photodiode is located in the silicon substrate between the silicon epitaxial layer and the first buried oxide layer;

forming a back medium layer on the whole front surface of the silicon substrate, and forming a metal interconnection layer in the back medium layer;

inverting the front side of the silicon substrate to bond the back dielectric layer with a slide glass;

thinning the back surface of the whole silicon substrate, and stopping thinning above the first oxygen-buried layer;

continuously thinning the back surface of the whole silicon substrate and removing the first buried oxide layer;

and continuing to thin the back surface of the whole silicon substrate, and removing the residual silicon substrate material above the silicon epitaxial layer to expose the surfaces of the silicon epitaxial layer and the photodiode.

9. The method for manufacturing a CMOS image sensor structure according to claim 8, further comprising, after the high-temperature annealing:

forming an oxide layer on the whole front surface of the silicon substrate through high-temperature oxidation;

removing the oxide layer on the inner wall surface of the groove; and

and after the growth of the silicon epitaxial layer is carried out in the groove, removing the rest oxide layer on the front surface of the silicon substrate outside the groove.

10. The method according to claim 8 or 9, characterized in that the growing of the silicon epitaxial layer is performed further comprising: the silicon epitaxial layer is doped and has a graded doping concentration toward the front surface of the silicon substrate.