CN110880508B - Transistor combination structure of integrated circuit memory and forming method thereof - Google Patents

Abstract

The present invention provides a transistor combination structure of an integrated circuit memory and a method for forming the same. A first notch that is recessed relative to a first top surface of the channel region is formed in a substrate of the channel region to increase the effective area of the interface between the channel region and the word line. Therefore, when a memory transistor composed of an active region and a word line is turned on, the formed conductive channel can be inverted along the interface morphology of the channel region and the word line, thereby increasing the length and/or width of the conductive channel, thereby effectively improving the short channel effect of the memory transistor and increasing the on-current of the memory transistor.

Description

Transistor combination structure of integrated circuit memory and forming method thereof

Technical Field

The present invention relates to the field of semiconductor integrated circuit technology, and in particular to a transistor combination structure of an integrated circuit memory and a forming method thereof, and a semiconductor integrated circuit device.

Background Art

In the current semiconductor industry, integrated circuit products can be divided into three main types: logic devices, memory devices and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products. A memory usually includes a plurality of memory cells, and the memory cell usually includes an active area, and the active area can be used to form a memory transistor, for example.

FIG1 is a schematic diagram of the structure of an active region of a memory cell. As shown in FIG1 , the active region 10 can be used to form a memory transistor, so an active region 10S and a drain region 10D are defined on the active region 10, and a portion between the source region 10S and the drain region 10D forms a channel region 10C. When the memory transistor is turned on, a conductive channel can be inverted and formed in the channel region 10C, so that the source region 10S and the drain region 10D can realize current flow through the conductive channel.

As the integration of semiconductor devices continues to increase, it has become a trend to improve the integration density of memory. However, under the requirement of reducing the size of components, the size of the conductive channel of the memory transistor will also be reduced, which will lead to the short channel effect of the memory transistor and reduce the on-current and saturation current of the memory transistor.

Summary of the invention

The object of the present invention is to provide a transistor combination structure of an integrated circuit memory to solve the problem that the short channel effect of the storage transistor and the decrease of the on-current are easy to occur in the existing integrated circuit memory as the device size continues to decrease.

In order to solve the above technical problems, the present invention provides a transistor combination structure of an integrated circuit memory, comprising:

a substrate having a plurality of active regions therein; and,

A plurality of word lines are formed in the substrate, wherein the word lines intersect with the corresponding active regions in their extending directions, and the active regions and part of the word lines together constitute storage transistors of an integrated circuit memory;

The portion of the active area corresponding to the word line constitutes a channel area, the substrate corresponding to the channel area has a first top surface, and at least one first notch recessed relative to the first top surface is formed in the substrate of the channel area, and the word line covers the first top surface of the channel area and fills the first notch.

Optionally, the active region extends along an active length direction, and the bottom surface of the first notch and the first top surface form a first step structure, and the first step structure is arranged step by step in a direction perpendicular to the extension direction of the active region.

Optionally, the first notch extends along an extension direction of the active region, and has the same length dimension as the channel region in the extension direction.

Optionally, a plurality of word line grooves are formed in the substrate, the word lines are filled in the word line grooves, and the word line grooves pass through the channel region of the corresponding active region in their extension direction; wherein the portion of the word line groove corresponding to the channel region constitutes a gate groove, the bottom surface of the gate groove corresponds to the first top surface of the channel region, and the first notch is recessed relative to the bottom surface of the gate groove.

Optionally, the word line trench further has a plurality of connection trenches in its extension direction, and the connection trenches are located between the gate trenches adjacent to each other in the word line extension direction, so that the gate trenches adjacent to each other in the word line extension direction are interconnected.

Optionally, in the word line trench, the bottom surface of the gate trench protrudes relative to the bottom surface of the connection trench and has a protruding sidewall, and the word line fills the gate trench and the connection trench and covers the protruding sidewall to form a gate of the fin field effect transistor.

Optionally, the first notch is arranged on a side of the gate groove close to the connecting groove, and the bottom surface of the first notch protrudes relative to the bottom surface of the connecting groove, so that the bottom surface of the connecting groove, the bottom surface of the first notch and the bottom surface of the gate groove constitute a multi-step structure, and the multi-step structure is arranged step by step in an extension direction perpendicular to the active area.

Optionally, the substrate further has a trench isolation structure, and the trench isolation structure surrounds the periphery of the active area to isolate adjacent active areas.

Optionally, the portion of the active region located on both sides of the word line constitutes the source and drain regions of the storage transistor, the substrate corresponding to the source and drain regions has a second top surface, and at least one second notch recessed relative to the second top surface is formed in the substrate corresponding to the source and drain regions.

Optionally, the active region extends along an active length direction, and the bottom surface of the second notch and the second top surface form a second step structure, and the second step structure is arranged step by step in a direction perpendicular to the extension direction of the active region.

Optionally, the second notch extends along an extension direction of the active region, and has the same length dimension as a corresponding source region or drain region in the extension direction of the active region.

Optionally, the first notch in the channel region and the second notch in the source/drain region both extend along an extension direction of the active region, and in the same active region, a height projection area of the first notch and a height projection area of the second notch are connected to each other on the same straight line.

Optionally, the plurality of active areas extend along the same direction and are aligned and arranged in the extending direction to form a plurality of active rows, and two adjacent active rows in the plurality of active rows are combined to form an active row group; wherein, in the two active rows of each active row group, the active areas located in different rows are formed with the first notch and the second notch on the side close to each other or on the side away from each other.

Optionally, the plurality of active regions are aligned and arranged in the extension direction of the word line to form a plurality of active columns, and in two adjacent active columns, the plurality of active regions in one active column all extend along the first direction, and the plurality of active regions in the other active column all extend along the second direction, so that the two adjacent active columns are mirror-symmetric with respect to a center line, and two adjacent active regions in different columns virtually intersect on the center line along the extension directions of the two active regions to have a virtual connection point;

The plurality of active regions are connected in series based on the virtual connection points to form a plurality of active strings, and two adjacent active strings in the plurality of active strings are combined to form an active string group (110B). In the two active strings in each of the active string groups, the active regions located on different active strings are formed with the first gap and the second gap on the side close to each other or on the side away from each other.

Another object of the present invention is to provide a method for forming a transistor combination structure of an integrated circuit memory, comprising:

A substrate is provided, wherein the substrate has a plurality of active regions, and a channel region is defined in the active region, and portions of the active region located on both sides of the channel region are used to form source and drain regions of transistors of an integrated circuit memory;

At least one first notch is formed in the substrate of the channel region, the substrate corresponding to the channel region having a first top surface, the first notch being recessed relative to the first top surface of the channel region, so that after forming a plurality of word lines, the word lines intersect with corresponding active regions in their extension directions to cover the channel regions of the active regions, and portions of the word lines corresponding to the channel regions cover the first top surface of the channel regions and fill the first notch.

Optionally, the word line forming method includes:

Forming a word line mask layer on the substrate, wherein a plurality of first openings are formed in the word line mask layer, wherein an extension direction of the first openings intersects with an extension direction of the active region and exposes the channel region of the active region;

The substrate is etched using the word line mask layer as a mask to form a plurality of word line grooves in the substrate, wherein the word line grooves pass through the channel region of the corresponding active region in the extending direction thereof, and the portions of the word line grooves corresponding to the channel region constitute gate grooves, and the first notches are further formed in the gate grooves, and the first notches are recessed relative to the bottom surface of the gate grooves;

A word line material is filled in the word line trench to form the word line.

Optionally, a portion of the word line trench corresponding to the gate trenches adjacent to each other in the word line extension direction constitutes a connecting trench, and a bottom surface of the connecting trench is lower than a bottom surface of the gate trench.

Optionally, the step of forming the first gap includes:

forming a shielding mask layer on the substrate, wherein a plurality of second openings are formed in the shielding mask layer, and the second openings expose a portion of the channel region; and,

The substrate is etched using the shielding mask layer as a mask to form a plurality of initial grooves in the substrate in the channel region, wherein the initial grooves are used to form the first notches.

Optionally, after forming the initial groove, the word line groove is formed and the first notch is formed at the same time, and the forming steps include:

forming the word line mask layer on the substrate, wherein the first opening of the word line mask layer exposes the channel region of the active region in its extension direction and exposes the initial groove corresponding to the channel region; and,

The substrate is etched using the word line mask layer as a mask to form a plurality of word line grooves in the substrate, wherein the initial grooves corresponding to the channel region form the first gaps after etching.

Optionally, the plurality of active regions extend along the same direction and are aligned in the extending direction to form a plurality of active rows, and two adjacent active rows in the plurality of active rows are combined to form an active row group.

Optionally, the second opening of the shielding mask layer extends along the extension direction of the active area, and each of the second openings exposes a portion of the active area in each of the active row groups where two active rows are close to each other, so as to expose a portion of the channel region; and the initial groove extends along the extension direction of the active area and has the same length dimension as the active area.

Optionally, the plurality of active areas are aligned and arranged in the extension direction of the word line to form a plurality of active columns, and in two adjacent active columns, the plurality of active areas in one active column all extend along a first direction, and the plurality of active areas in the other active column all extend along a second direction, so that the two adjacent active columns are mirror-symmetric with respect to a center line, and two adjacent active areas in different columns virtually intersect on the center line along the extension directions of the two active areas to have a virtual connection point; wherein the plurality of active areas are connected in series based on the virtual connection point to form a plurality of waveform-extended active strings, and two adjacent active strings in the plurality of active strings are combined to form an active string group.

Optionally, the second opening of the shielding mask layer extends corresponding to the active string waveform, and each of the second openings exposes a portion of the active area in each of the active string groups where two active strings are close to each other, so as to expose a portion of the channel area; and the initial groove extends along the active area in the corresponding active area and has the same length dimension as the corresponding active area.

Optionally, the first opening of the word line mask layer exposes part of the initial groove, and the part of the initial groove corresponding to the part in the channel region is used to form the first gap, and the parts of the initial groove located on both sides of the channel region are used to form a second gap, and the second gap corresponds to the source and drain region.

Another object of the present invention is to provide a semiconductor integrated circuit device, comprising:

a substrate having a plurality of active regions therein; and,

A plurality of conductive lines are formed in the substrate, wherein the conductive lines intersect with the corresponding active regions in their extending directions, and the active regions and a portion of the conductive lines together constitute a transistor;

The portion of the active area corresponding to the conductive line constitutes a channel area, the substrate corresponding to the channel area has a first top surface, and at least one notch recessed relative to the first top surface is formed in the substrate of the channel area, and the conductive line covers the first top surface of the channel area and fills the notch.

In the transistor combination structure of the integrated circuit provided by the present invention, a first notch is formed in the substrate of the channel region corresponding to the active region, and the first notch is recessed relative to the first top surface of the channel region. That is, it is equivalent to that the channel region has an uneven surface, which not only has a first surface, but also has a bottom surface and sidewall of the first notch recessed relative to the first surface, thereby greatly increasing the effective area of the junction between the channel region and the word line. When the storage transistor composed of the active region and the word line is turned on, the conductive channel formed in the channel region, that is, the corresponding interface morphology along the channel region and the word line is inverted, so that the cross-sectional shape of the formed conductive channel in a predetermined direction is bent, which is conducive to increasing the length dimension and/or width dimension of the conductive channel, thereby improving the short channel effect of the constituted storage transistor, and increasing the conduction current of the storage transistor. Based on this, it is also conducive to reducing the memory size of the integrated circuit memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of an active area of a memory cell;

FIG2 is a top view of an integrated circuit memory in the first embodiment of the present invention;

3 is a schematic structural diagram of an active area of an integrated circuit memory in Embodiment 1 of the present invention;

FIG4a is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in FIG2 along the direction a1-a1′;

FIG4b is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in FIG2 along the direction a2-a2';

FIG4c is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in FIG2 along the direction b1-b1′;

FIG4d is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in FIG2 along the direction b2-b2';

FIG5 is a schematic diagram of the structure of the integrated circuit memory in the first embodiment of the present invention shown in FIG4a after the word lines are omitted;

FIG6 is a top view of an integrated circuit memory in a second embodiment of the present invention;

FIG7a is a schematic cross-sectional view of the integrated circuit memory in the second embodiment of the present invention shown in FIG6 along the aa′ direction;

FIG7b is a schematic cross-sectional view of the integrated circuit memory in the second embodiment of the present invention shown in FIG6 along the bb' direction;

8 is a schematic flow chart of a method for forming an integrated circuit memory in Embodiment 3 of the present invention;

9a to 12a are top views of the method for forming an integrated circuit memory in the third embodiment of the present invention during its preparation process;

9b, 10b to 10c, 11b to 11c and 12b are cross-sectional schematic diagrams of the method for forming an integrated circuit memory in the third embodiment of the present invention during its preparation process.

The reference numerals are as follows:

10-active region; 10C-channel region;

10S-source region; 10D-drain region;

100-substrate;

110-active region; 110C-channel region;

110S-source region; 110D-drain region;

111C-conductive channel; 111SD-second notch;

110A-active row group; 110B-active string group;

110P-virtual connection point;

120- trench isolation structure; 121- isolation structure;

200-word line;

200G-gate portion; 200L-connecting portion;

300-word line groove;

300G-gate trench; 300L-connection trench;

310G-first gap;

400-isolation layer;

500- shielding mask layer;

510 - second opening; 511 - initial groove;

600-word line mask layer; 610-first opening;

T11 - first top surface; T12 - bottom surface of the first notch;

T13 - bottom surface of the connecting groove;

T21 - second top surface; T22 - bottom surface of the second notch;

H1-first height position; H2-second height position;

H3-third height position; H4-fourth height position;

H5 - fifth height position.

DETAILED DESCRIPTION

The integrated circuit memory and its formation method and semiconductor device proposed by the present invention are further described in detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

Embodiment 1

FIG2 is a top view of the integrated circuit memory in the first embodiment of the present invention, FIG3 is a schematic diagram of the structure of the active area of the integrated circuit memory in the first embodiment of the present invention, FIG4a is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in FIG2 along the a1-a1' direction, FIG4b is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in FIG2 along the a2-a2' direction, FIG4c is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in FIG2 along the b1-b1' direction, and FIG4d is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in FIG2 along the b2-b2' direction. In combination with FIG2, FIG3 and FIG4a to FIG4d, the transistor combination structure of the integrated circuit memory includes: a substrate 100 and a plurality of word lines 200 formed on the substrate 100.

The substrate 100 has a plurality of active regions 110 . Furthermore, the substrate also has a trench isolation structure 120 . The trench isolation structure 120 surrounds the periphery of the active region 110 to isolate adjacent active regions 110 .

Referring to FIG. 2 , the active area 110 extends along the active length direction. In this embodiment, all active areas 110 extend along the first direction (Z1 direction), and a plurality of active areas 110 are arranged in an array. In this embodiment, a plurality of active areas 110 are aligned and arranged in the active length direction to form a plurality of active rows, wherein two adjacent active rows in the plurality of active rows can be combined to form an active row group 110A.

2, 3 and 4a to 4d, a plurality of word lines 200 are formed in the substrate 100 and extend obliquely relative to the extension direction of the active area (in this embodiment, the word lines extend along the Y direction), the word lines 200 intersect with the corresponding active areas 100 in the word line extension direction, and the active areas 110 and part of the word lines 200 together constitute a transistor combination structure of an integrated circuit memory.

With particular reference to FIG. 3 and in combination with FIG. 4 a , the portions of the active region 110 located on both sides of the word line 200 constitute the source region 110S and the drain region 110D of the storage transistor. Also, the portion of the active region 110 corresponding to the word line 200 constitutes the channel region 110C, the substrate 100 has a first top surface T11 corresponding to the channel region 110C, and at least one first notch 310G is formed in the substrate 100 of the channel region 110C, which is recessed relative to the first top surface T11, that is, the bottom surface T12 of the first notch 310G is further sunken relative to the first top surface T11 of the channel region 110C. The word line 200 covers the first top surface T11 and fills the first notch 310G.

It should be noted that, when the memory transistor composed of the word line 200 and the active area 110 is turned on, a conductive channel 111C can be invertedly formed in the substrate corresponding to the channel area 110C and close to the word line 200. In particular, since a first notch 310G is recessed on the first top surface T11 of the channel area 110C, the substrate surface corresponding to the channel area 110C is an uneven surface (that is, the cross-sectional shape of the substrate surface corresponding to the channel area 110C in a predetermined direction is a bent structure), and the word line 200 covers the substrate surface of the channel area along the uneven surface of the channel area 110C. In this way, when the storage transistor is turned on, the inversion-formed conductive channel 111C, that is, the corresponding interface morphology along the word line 200 and the substrate surface of the channel region 110C, is formed in the substrate, so that the cross-sectional shape of the formed conductive channel 111C in a predetermined direction can be a bent structure, which is beneficial to increase the size of the conductive channel 111C of the storage transistor in the predetermined direction.

For example, the cross-sectional shape of the conductive channel 111C in the direction from the source region to the drain region (i.e., in the length direction of the conductive channel 111C) is bent, which is equivalent to increasing the length of the conductive channel 111C, thereby improving the short channel effect of the storage transistor; or, the cross-sectional shape of the conductive channel 111C in the direction perpendicular to the source region to the drain region (i.e., in the width direction of the conductive channel 111C) is bent, which is equivalent to increasing the width of the conductive channel 110C, thereby effectively increasing the on-current of the storage transistor, which is beneficial to improving the on-performance of the storage transistor.

Continuing to refer to FIG. 4a to FIG. 4d, in this embodiment, the cross-sectional shape of the conductive channel 111C in its width direction is bent. FIG. 4a is a schematic cross-sectional view of the conductive channel 111C in the width direction, so the conductive particles in the conductive channel 111C shown in FIG. 4a flow in a direction perpendicular to the paper surface; FIG. 4d and FIG. 4c are schematic cross-sectional views of the conductive channel 111C in the length direction, so the conductive particles in the conductive channel 111C shown in FIG. 4d and FIG. 4c flow in a direction from the source region 110S to the drain region 110D or from the drain region 110D to the source region 110S. Therefore, in this embodiment, by forming the first notch 310G, the total width of the conductive channel 111C is increased in the width direction of the conductive channel 111C, so that the width of the conductive channel 111C formed in inversion can be further widened, which is beneficial to improving the on-current of the storage transistor.

As shown in FIG. 2 , FIG. 3 and FIG. 4 a , the bottom surface T12 of the first notch 310G and the first top surface T11 in this embodiment constitute a first step structure, and the first step structure is arranged step by step in a direction perpendicular to the extension direction of the active region. Further, the first notch 310G can also extend along the extension direction of the active region, and have the same length dimension as the channel region 110C in the extension direction. That is, the first notch 310G extends in a direction parallel to the active region, and can extend to the entire channel region 110C in its extension direction, so the entire channel region 110C can constitute a step structure.

Fig. 5 is a schematic diagram of the structure of the integrated circuit memory in the first embodiment of the present invention shown in Fig. 4a after omitting the word line. Combining Fig. 4a and Fig. 5, the word line 200 in this embodiment is a buried word line and is buried in the substrate 100.

Specifically, a plurality of word line grooves 300 are formed in the substrate 100, and the word lines 200 are filled in the word line grooves 300, so that the word line grooves 300 extend in the extension direction of the word lines 200; and the word line grooves 300 pass through the corresponding active areas 110 in the word line extension direction, so that the word lines 200 can intersect with the corresponding active areas 110 in the word line extension direction.

Furthermore, the portion of the word line trench 300 corresponding to the active area 110 constitutes a gate trench 300G, and the portion of the word line 200 filling the gate trench 300G is used to constitute the gate portion 200G of the storage transistor. The bottom surface of the gate trench 300G is the first top surface T11 of the channel region 110C, and the first notch 310G is a corresponding depression relative to the bottom surface of the gate trench.

Specifically, the top surface of the non-corresponding word line of the substrate has a first height position H1, the bottom surface T11 of the gate trench 300G has a second height position H2, and the bottom surface T12 of the first notch 310G has a third height position H3, wherein the first height position H1 is higher than the second height position H2, and the second height position H2 is higher than the third height position H3.

Continuing with reference to FIG. 4a and FIG. 5, the word line groove 300 further has a plurality of connection grooves 300L in its extension direction, and the connection grooves 300L are located between the gate grooves 300G adjacent to each other in the word line extension direction, so that the gate grooves 300G adjacent to each other in the word line extension direction are interconnected; the word line 200 fills the connection grooves 300L to form a connection portion 200L, and the connection portion 200L is interconnected with the gate portion 200G.

It can be considered that the connection trench 300L corresponds to the trench isolation structure 120, and the connection portion 200L of the word line is correspondingly formed in the trench isolation structure 120. Wherein, an isolation structure 121 is formed in the trench isolation structure 120, and the connection portion 200L is formed on the isolation structure 121.

With particular reference to FIG. 5 , in the word line trench 300 of this embodiment, the bottom surface T11 of the gate trench 300G protrudes relative to the bottom surface T13 of the connection trench 300L and has a protruding sidewall, and the word line 200 fills the gate trench 300G and the connection trench 300L and covers the protruding sidewall to form the gate of the fin field effect transistor. Alternatively, it can be understood that the bottom surface T13 of the connection structure 300L is recessed relative to the bottom surface T11 of the gate trench 300G, and in this embodiment, the top surface of the isolation structure 121 in the trench isolation structure 120 is lower than the first top surface T11 of the channel region 110C.

That is, the substrate corresponding to the channel region 110C protrudes relative to the isolation structures 121 on both sides thereof, so that the word line 200 can not only cover the top surface of the channel region 110C, but also cover the protruding sidewalls on both sides of the channel region 110C. When the fin field effect transistor is turned on, a conductive channel can be formed not only in the substrate near the top surface of the channel region, but also in the substrate near the protruding sidewalls of the gate region, further increasing the width of the conductive channel of the storage transistor.

Furthermore, the first notch 310G is arranged on a side of the gate groove 300G close to the connecting groove 300L, and the bottom surface T12 of the first notch 310G protrudes relative to the bottom surface T13 of the connecting groove 300L, so that the bottom surface T13 of the connecting groove, the bottom surface T12 of the first notch and the bottom surface T11 of the gate groove constitute a multi-step structure, and the multi-step structure is arranged step by step in a direction perpendicular to the extension direction of the active area (perpendicular to the Z1 direction).

In this embodiment, the bottom surface T13 of the connecting groove 300L has a fourth height position H4. The fourth height position H4 of the bottom surface T13 of the connecting groove 300L, the third height position H3 of the bottom surface T12 of the first notch 310G, the second height position H2 of the bottom surface T11 of the gate groove 300G and the first height position H1 of the top surface of the non-corresponding word line of the substrate present a multi-step structure from low to high.

It should be noted that, since the first notch 310G is interconnected with the connecting groove 300L, the side wall of the first notch 310G close to the connecting structure 300L is removed, so that the bottom surface T12 of the first notch 310G conforms to the side wall of the connecting groove 300L to form the multi-step step structure.

Accordingly, when the storage transistor is turned on and a conductive channel 111C is invertedly formed along the surface morphology of the substrate in the substrate near the gate portion 300G, the cross-sectional shape of the conductive channel 111C in its width direction correspondingly presents a multi-step structure.

Next, focusing on Figures 3 and 4b, the portions of the active region 110 located on both sides of the word line 200 respectively constitute the source region 110S and the drain region 110D of the storage transistor, and the substrate has a second top surface T21 corresponding to the source region 110S and the drain region 110D; and at least one second notch 111SD recessed relative to the second top surface T21 is formed in the substrate corresponding to the source region 110S and the drain region 110D.

In this embodiment, the substrate surface corresponding to the source region 110S and the drain region 110D also presents an uneven surface, which correspondingly increases the surface area of the source region 110S and the drain region 110D. Therefore, based on the fact that the projection size of the source region 110S and the drain region 110D in the height direction is not changed, the contact area between the source region 110S and the drain region 110D and other components subsequently formed thereon is effectively increased, thereby correspondingly reducing the contact resistance; or, while keeping the surface area of the source region 110S and the drain region 110D unchanged, the projection size of the source region 110S and the drain region 110D in the height direction is reduced (that is, the size that the source region 110S and the drain region 110D need to occupy on the substrate is reduced), so that the overall size of the formed storage transistor can be further reduced, which is conducive to realizing a high-density arrangement of integrated circuit memory.

Continuing to refer to FIGS. 2 and 4 b , in the source region 110S and the drain region 110D, the bottom surface T22 and the second top surface T21 of the second notch 111SD may further constitute a second step structure, and the second step structure is arranged step by step in a direction perpendicular to the extension direction of the active region. Furthermore, the second notch 111SD may also extend along the extension direction (Z1 direction) of the active region, and have the same length dimension as the corresponding source region or drain region in the extension direction of the active region. That is, in this embodiment, the second notch 111SD in the source region 110S and the drain region 110D is similar to the setting of the first notch 310G in the channel region 110C, and both extend along the extension direction of the active region.

In an optional solution, in the same active region, the ends of the height projection area of the first notch 310G of the channel region 110C and the height projection area of the second notch 111SD of the source region 110S/drain region 110D are connected to each other. That is, in this embodiment, the first notch 310G is more sunken than the second notch 111SD, but in the height projection area, the first notch 310G and the second notch 111SD can extend on the same straight line.

Specifically, the height position of the second top surface T21 of the source region 110S and the drain region 110D corresponds to the first height position H1 of the top surface of the substrate not corresponding to the word line as described above, that is, the second top surface T21 has the first height position H1, and the bottom surface T22 of the second notch has a fifth height position H5, and the fifth height position H5 is lower than the first height position H1. In this embodiment, the height difference between the first height position H1 and the fifth height position H5 of the corresponding source region 110S and the drain region 110D is equal to or close to the height difference between the second height position H2 and the third height position H3 of the corresponding gate trench 300G.

Continuing to refer to FIG. 2 , in this embodiment, a plurality of active regions 110 are aligned and arranged in the extension direction (Z1 direction) to form a plurality of active rows, and two adjacent active rows in the plurality of active rows can be combined to form an active row group 110A. Among them, in the two active rows of each active row group 110A, the active regions 110 located in different rows are formed with the first notch 310G and the second notch 111SD on the side close to each other or the side away from each other. That is, the first notches 310G located in different rows are close to each other or away from each other, and the second notches 111SD located in different rows are close to each other or away from each other.

Since the two active rows in the active row group 110A are aligned along their extension direction (i.e., the arrangement direction is parallel to the extension direction of the active area), the first notch 310G and the second notch 111SD can be arranged at the same straight line position of each active row in its arrangement direction. In this way, when preparing the first notch and the second notch, the difficulty of preparing the first notch and the second notch can be reduced.

In addition, the transistor combination structure of the integrated circuit memory further includes an isolation layer 400 , which is formed on the substrate 100 and fills a portion of the word line trench 300 located above the word line 200 to cover the word line 200 .

Embodiment 2

The difference from the first embodiment is that in the integrated circuit memory in this embodiment, some of the multiple active regions extend along the first direction, and another part of the active regions extend along the second direction.

Figure 6 is a top view of the integrated circuit memory in the second embodiment of the present invention, Figure 7a is a cross-sectional schematic diagram of the integrated circuit memory in the second embodiment of the present invention shown in Figure 6 in the aa’ direction, and Figure 7b is a cross-sectional schematic diagram of the integrated circuit memory in the second embodiment of the present invention shown in Figure 6 in the bb’ direction.

As shown in FIG. 6 and FIG. 7a to FIG. 7b, in this embodiment, a plurality of active regions 110 are aligned and arranged along the extension direction of the word line 200 to form a plurality of active columns, and in two adjacent active columns, a plurality of active regions 110 in one active column are extended along the first direction (Z1 direction), and a plurality of active regions 110 in the other active column are extended along the second direction (Z2 direction), so that the two adjacent active columns are mirror-symmetric with respect to a center line. In addition, two adjacent active regions 110 in different columns virtually intersect on the center line along the extension direction of the two active regions and have a virtual connection point 110P.

Further, a plurality of the active regions 110 are connected in series based on the virtual connection point 110P to form a plurality of active strings, and the active strings are correspondingly extended in a wave structure. In the present embodiment, the active string extends in a wave shape in a direction perpendicular to the extension direction of the word line, that is, the active string extends in the X direction. Among them, two active strings adjacent to each other in the plurality of active strings are combined to form an active string group 110B. In an optional scheme, in the two active strings of each of the active string groups 110B, the active regions 110 located on different active strings are formed with the first notch 310G and the second notch 111SD on the side close to each other or on the side away from each other.

Continuing to refer to FIG. 6 and FIG. 7 b , a plurality of trench isolation structures 120 are provided in the substrate 100, and a plurality of isolation structures 121 are formed in the trench isolation structures 120 to isolate adjacent active regions 110 from each other. In this embodiment, since the plurality of active regions 110 are aligned and arranged in a column direction, and the trench isolation structures 120 are correspondingly provided between adjacent active columns, the isolation structures 121 formed between adjacent active columns extend along the extension direction of the word lines 200 accordingly.

Embodiment 3

FIG8 is a schematic flow chart of the method for forming an integrated circuit memory in the third embodiment of the present invention, FIG9a to FIG12a are top views of the method for forming an integrated circuit memory in the third embodiment of the present invention during its preparation process; FIG9b, FIG10b to FIG10c, FIG11b to FIG11c and FIG12b are schematic cross-sectional views of the method for forming an integrated circuit memory in the third embodiment of the present invention during its preparation process. The steps of the method for forming an integrated circuit memory in this embodiment are described in detail below in conjunction with the accompanying drawings.

In step S100, specifically referring to Figures 9a and 9b, a substrate 100 is provided, wherein the substrate 100 has a plurality of active regions 110, and a channel region 110C is defined in the active region 110, and portions of the active region 110 located on both sides of the channel region 110C are used to constitute source and drain regions of a transistor combination structure of an integrated circuit memory.

In this embodiment, the plurality of active regions 110 extend along the same direction (Z1 direction) and are aligned in the extending direction to form a plurality of active rows. Two adjacent active rows in the plurality of active rows are combined to form an active row group 110A.

In step S200, specifically referring to Figures 10a to 12a and Figures 10b to 10c, Figures 11b to 11c and Figure 12b, at least one first notch 310G is formed in the substrate of the channel region 110C, the substrate corresponding to the channel region 110C has a first top surface T11, and the first notch 310G is recessed relative to the first top surface T11 of the channel region 110C, so that after forming a plurality of word lines 200, the word lines 200 intersect with the corresponding active regions 110 in their extension directions, and the portion of the word lines 200 corresponding to the active regions covers the first top surface T11 of the channel region 110C and fills the first notch 310G.

Since a first notch 310G recessed relative to the first top surface T11 is formed in a partial area of the channel region 110C, and another partial area of the channel region 110C still has the first top surface T11, the channel region 110C has an uneven surface. Therefore, when the word line 200 is formed to constitute a storage transistor, the size of the conductive channel of the storage transistor can be increased.

In this embodiment, the word line 200 formed is a buried word line, that is, the word line 200 is formed in the substrate. Specifically referring to FIG. 11a and FIG. 12a, the method for forming the word line 200 includes: first, forming a word line groove 300 in the substrate 100, the word line groove 300 passes through the channel region 110C of the active region, and the part of the word line groove 300 corresponding to the channel region constitutes a gate groove 300G, and the first notch 310G is also formed in the gate groove 300G; then, filling the word line material in the word line groove 300 to form the word line 200, the word line 200 fills the gate groove 300G and further fills the first notch 310G.

Further, the first notch 310G and the word line groove 300 are formed in the same step, that is, the first notch 310G is formed on the bottom of the word line groove 300 while the word line groove 300 is formed. The following is a detailed description of the method for forming the first notch 310G, the word line groove 300 and the word line 200 in this embodiment in conjunction with the accompanying drawings.

In the first step, specifically referring to FIG. 10a and FIG. 10b, a shielding mask layer 500 is formed on the substrate 100, and a plurality of second openings 510 are opened in the shielding mask layer 500. The second openings 510 expose a portion of the channel region 110C and correspondingly cover another portion of the channel region 110C. In this step, the top surface of the substrate 100 has a first height position H1.

As shown in FIG. 10a, the multiple active regions 110 in this embodiment constitute multiple active rows, and the multiple active rows are aligned and arranged in the extension direction of the active regions, and further combined to form multiple active row groups 110A. At this time, the second openings 510 of the shielding mask layer 500 can be extended along the extension direction of the active regions, and each of the second openings 510 can expose the portion of the active regions 110 in each of the active row groups 110A where the two active rows are close to each other, so as to expose part of the channel region 110C. That is, one opening can be used to simultaneously expose part of the channel region 110C of multiple active regions 110, so that the opening size of the second opening 510 can be increased, and then when defining the second opening, it is beneficial to increase the photolithography process window corresponding to the second opening.

In the second step, as described in detail with reference to FIG. 10a and FIG. 10c, the substrate 100 is etched using the shielding mask layer 500 as a mask to form a plurality of initial grooves 511 in the substrate 100 in the channel region 110C. Then, the shielding mask layer 500 can be removed. In this step, the bottom surface of the formed initial groove 511 can have a fifth height position H5, and the fifth height position H5 is lower than the first height position H1.

In this embodiment, the second opening 510 exposes the active area 110 along the extension direction of the active area, so that the formed initial groove 511 extends accordingly along the extension direction of the active area, and the initial groove 511 has the same length dimension as the active area 110, that is, the initial groove 511 extends in the entire active area 110 in the extension direction of the active area.

In the third step, specifically referring to FIG. 11a and FIG. 11b , a word line mask layer 600 is formed on the substrate 100, and a plurality of first openings 610 are opened in the word line mask layer 600. The extension direction of the first openings 610 intersects with the extension direction of the active area, and exposes the channel area 110C of the active area, and correspondingly exposes the portion of the initial groove 511 located in the channel area 110C in its extension direction.

In this embodiment, the initial groove 511 is formed in the channel region 110C, and further extends to the active region 110 outside the channel region. Based on this, the first opening 610 of the word line mask layer 600 only exposes a portion of the initial groove 511, wherein the portion of the initial groove 511 corresponding to the channel region is used to form the first notch, and the portions of the initial groove 511 located on both sides of the channel region are used to form a second notch 111SD, and the second notch 111SD corresponds to the source region 110S and the drain region 110D.

In the fourth step, with specific reference to FIG. 11a and FIG. 11c, the substrate 100 is etched with the word line mask layer 600 as a mask to form a plurality of word line grooves 300 in the substrate 100. The word line grooves 300 pass through the channel region 110C of the corresponding active region in the extension direction thereof, and the portion of the word line grooves 300 corresponding to the channel region 110C constitutes a gate groove 300G. In addition, the initial groove 511 corresponding to the channel region constitutes the first notch 310G after etching, and the first notch 310G is formed in the gate groove 300G, that is, the portion of the gate groove 300G corresponding to the initial groove 511 is recessed relative to the bottom surface T11 of the gate groove to constitute the first notch 310G. In this way, the first notch 310G can be formed in the gate groove 300G while the gate groove 300G is formed.

The bottom surface T11 of the gate channel of the word line trench 300 has a second height position H2, and the bottom surface T12 of the first notch has a third height position H3, and the third height position H3 is lower than the second height position H2.

Furthermore, the word line trench 300 further includes a connecting trench 300L. The connecting trench 300L is located between the gate trenches 300G adjacent to each other in the word line extension direction, and is used to connect the gate trenches 300G adjacent to each other in the word line extension direction.

In a preferred embodiment, the bottom surface T13 of the connecting trench 300L is further sunken than the bottom surface T11 of the gate trench 300G, that is, the bottom surface T11 of the gate trench protrudes relative to the bottom surface T13 of the connecting trench and has a protruding sidewall. The bottom surface T13 of the connecting trench has a fourth height position H4, and the fourth height position H4 is lower than the second height position H2 of the bottom surface of the gate trench.

Optionally, the first notch 310G is close to the connecting trench 300L and communicates with the connecting trench 300L, and the bottom surface T13 of the connecting trench is more sunken than the bottom surface T12 of the first notch. Therefore, the bottom surface T11 of the gate trench, the bottom surface T12 of the first notch 310G and the bottom surface T13 of the connecting trench can form a multi-step structure.

In the fifth step, as shown in FIG12a and FIG12b, word line material is filled in the word line trench to form the word line 200. The word line 200 fills the gate trench, the first notch and the connection trench.

The portion of the word line 200 filled with the gate trench and the first notch constitutes a gate portion 200G, and the portion of the word line 200 filled with the connection trench constitutes a connection portion 200L. Also, the portion of the active region 110 located on both sides of the word line 200 is used to constitute the source region 110S and the drain region 110D of the storage transistor.

At this point, a plurality of buried word lines 200 are formed in the substrate 100 , and the word lines 200 not only fill the gate trenches but also further fill the first gaps in the portions corresponding to the channel regions 110C.

Furthermore, after forming the word line 200, the method further includes:

Step S300 , referring to FIG. 12 b , an isolation layer 400 is formed on the substrate 100 to cover the word line 200 .

Furthermore, the top of the word line 200 is lower than the top of the word line trench. At this time, the isolation layer 400 further fills the portion of the word line trench located above the word line to improve the isolation effect on the word line.

It should be noted that in this embodiment, a plurality of active regions extending in the same direction and arranged in an aligned manner are used as an example to explain the formation method of the integrated circuit memory. However, in other embodiments, when the plurality of active regions are arranged in the manner shown in FIG. 6 , the morphology of the second opening of the shielding mask layer can be adjusted accordingly.

Specifically, in other embodiments, the plurality of active regions are aligned and arranged in the extension direction of the word line to form a plurality of active columns, and in two adjacent active columns, the plurality of active regions in one active column all extend along the first direction, and the plurality of active regions in the other active column all extend along the second direction, so that the two adjacent active columns are mirror-symmetric with respect to a center line, and two adjacent active regions in different columns virtually intersect on the center line along the extension direction of the two active regions and have a virtual connection point. The plurality of active regions are connected in series based on the virtual connection point to form a plurality of active strings extending in waveforms, and two active strings adjacent to each other in the plurality of active strings are combined to form an active string group.

Based on this, when forming the initial groove, the second opening of the shielding mask layer can be extended corresponding to the waveform of the active string, and each of the second openings exposes the portion of the active region in each of the active string groups where the two active strings are close to each other, so as to expose part of the channel region. At this time, the second opening is also extended in a waveform to correspond to the morphology of the active string, and the initial groove formed can also be extended along the active region in the corresponding active region and have the same length size as the corresponding active region.

In addition, in the field of semiconductor integrated circuits, the transistor combination structure of the integrated circuit memory described above can also be modified accordingly to be applicable to other semiconductor integrated circuit devices. Specifically, the semiconductor integrated circuit device includes:

a substrate having a plurality of active regions therein; and,

A plurality of conductive lines are formed in the substrate, wherein the conductive lines intersect with the corresponding active regions in their extending directions, and the active regions and a portion of the conductive lines together constitute a transistor;

The portion of the active area corresponding to the conductive line constitutes a channel area, the substrate corresponding to the channel area has a first top surface, and at least one notch recessed relative to the first top surface is formed in the substrate of the channel area, and the conductive line covers the first top surface of the channel area and fills the notch.

In the semiconductor integrated circuit device as described above, the length and/or width of the conductive channel of the transistor of the semiconductor integrated circuit device can also be effectively increased, thereby effectively improving the conduction performance of the transistor and the short channel effect of the transistor. In other words, the semiconductor integrated circuit device can effectively reduce the problem of short channel effect of the transistor while achieving device size reduction, and avoid the conduction current of the transistor being too small, so as to ensure the conduction performance of the transistor.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims (19)

1. A transistor combination structure of an integrated circuit memory, comprising:

a substrate having a plurality of active regions therein; and

A plurality of word lines formed in the substrate, the word lines intersecting the respective active regions in a word line extending direction, memory transistors of an integrated circuit memory being collectively constituted by the active regions and portions of the word lines within the active regions;

Wherein a groove portion of the active region corresponding to the word line constitutes a channel region, the substrate corresponding to the channel region has a first top surface, and at least one first notch recessed with respect to the first top surface is formed in the substrate of the channel region, the word line covers the first top surface of the channel region and fills the first notch;

the active region extends along the active length direction, the bottom surface of the first notch and the first top surface form a first step structure, and the first step structure is arranged step by step in the extending direction perpendicular to the active region;

the first notch extends along the extending direction of the active region and has the same length dimension as the channel region in the extending direction;

A plurality of word line trenches are formed in the substrate, the word lines are filled in the word line trenches, and the word line trenches cross the channel regions of the corresponding active regions in the extending direction of the word lines;

wherein a portion of the wordline trench corresponding to the channel region constitutes a gate trench, a bottom surface of the gate trench corresponds to the first top surface of the channel region, and the first notch is recessed relative to the bottom surface of the gate trench.

2. The transistor combination structure of an integrated circuit memory according to claim 1, wherein the word line trench further has a plurality of connection trenches in a word line extending direction, the connection trenches being located between the gate trenches adjacent in the word line extending direction so that the gate trenches adjacent in the word line extending direction communicate with each other.

3. The transistor combination structure of integrated circuit memory of claim 2, wherein in the word line trench, a bottom surface of the gate trench protrudes with respect to a bottom surface of the connection trench and has protruding sidewalls, the word line filling the gate trench and the connection trench and covering the protruding sidewalls to constitute a gate of a fin field effect transistor.

4. The transistor combination structure of the integrated circuit memory according to claim 3, wherein the first notch is provided on a side of the gate trench close to the connection trench, and a bottom surface of the first notch protrudes with respect to a bottom surface of the connection trench so that the bottom surface of the connection trench, the bottom surface of the first notch, and the bottom surface of the gate trench constitute a multi-step structure arranged stepwise in an extending direction perpendicular to the active region.

5. The transistor combination structure of claim 1, wherein a trench isolation structure is further formed in said substrate, said trench isolation structure surrounding a periphery of said active region to isolate adjacent said active region.

6. The transistor combination structure of any of claims 1-5, wherein portions of the active region on both sides of the word line form source and drain regions of the memory transistor, the substrate corresponding to the source and drain regions has a second top surface, and at least one second notch recessed relative to the second top surface is formed in the substrate corresponding to the source and drain regions.

7. The transistor combination structure of claim 6, wherein the active region extends along an active length direction, and wherein a bottom surface of the second notch and the second top surface form a second step structure, the second step structure being arranged stepwise in a direction perpendicular to the extension direction of the active region.

8. The transistor combination structure of claim 7, wherein the second notch extends along an extension direction of the active region and has a same length dimension as a corresponding source or drain region in the extension direction of the active region.

9. The transistor combination structure of claim 6, wherein the first notch of the channel region and the second notch of the source drain region each extend along an active length direction, and a height projection area of the first notch and a height projection area of the second notch are connected to each other on a same straight line in the same active region.

10. The transistor combination structure of claim 6, wherein a plurality of said active regions extend along a same direction and are aligned in an active length direction to form a plurality of active rows, and two adjacent active rows of said plurality of active rows are combined to form an active row group; in the two active rows of each active row group, the active regions located on different rows are respectively formed with the first notch and the second notch on the sides close to each other or the sides far away from each other.

11. The transistor combination structure of an integrated circuit memory according to claim 6, wherein a plurality of the active regions are aligned in a word line extending direction to constitute a plurality of active columns, and in adjacent two active columns, a plurality of active regions in one active column each extend along a first direction, a plurality of active regions in the other active column each extend along a second direction, such that the adjacent two active columns are mirror-symmetrical with respect to a center line, and two active regions located between adjacent two active regions in different columns virtually intersect on the center line along an extending direction of the two active regions to have virtual connection points;

The active areas are connected in series based on the virtual connection points to form a plurality of active strings, two adjacent active strings in the active strings are combined to form an active string group, and the first notch and the second notch are formed on one side, close to each other or away from each other, of the active areas on different active strings in the two active strings of each active string group.

12. A method of forming a transistor combination structure for an integrated circuit memory, comprising:

providing a substrate, wherein the substrate is provided with a plurality of active areas, channel areas are defined in the active areas, and the parts of the active areas, which are positioned at two sides of the channel areas, are used for forming source and drain areas of a transistor combination structure of an integrated circuit memory; and

Forming at least one first notch in the substrate of the channel region, the forming step of the first notch comprising: forming a shielding mask layer on the substrate, wherein a plurality of second openings are formed in the shielding mask layer, and the second openings expose part of the channel region; etching the substrate by taking the shielding mask layer as a mask to form a plurality of initial grooves in the substrate of the channel region, wherein the initial grooves are used for forming the first notch; wherein a substrate corresponding to the channel region has a first top surface, the first notch being recessed relative to the first top surface of the channel region;

Forming a word line mask layer on the substrate, wherein a plurality of first openings are formed in the word line mask layer, and the extending direction of the first openings is intersected with the extending direction of the active region and exposes the channel region of the active region;

Etching the substrate by taking the word line mask layer as a mask to form a plurality of word line grooves in the substrate, wherein the word line grooves penetrate through a channel region of a corresponding active region in the extending direction of the word line grooves, a part of the word line grooves corresponding to the channel region forms a gate groove, the gate groove is further provided with the first notch, and the first notch is sunken relative to the bottom surface of the gate groove; and

Filling a word line material in the word line trench to form a word line;

After forming the plurality of word lines, the word lines intersect the respective active regions in a word line extending direction to cover the channel regions of the active regions, and portions of the word lines corresponding to the channel regions cover the first top surfaces of the channel regions and fill the first gaps.

13. The forming method according to claim 12, wherein a portion of the word line trenches corresponding to between the gate trenches adjacent in the word line extending direction constitutes a connection trench, a bottom surface of the connection trench being lower than a bottom surface of the gate trench.

14. The method of forming of claim 12, wherein after forming the initial recess, forming the word line trench and simultaneously forming the first notch comprises:

Forming the word line mask layer on the substrate, wherein the first opening of the word line mask layer exposes the channel region of the active region in the extending direction of the word line and exposes the initial groove corresponding to the channel region; and

And etching the substrate by taking the word line mask layer as a mask to form a plurality of word line grooves in the substrate, wherein the initial grooves corresponding to the channel regions form the first notch after etching.

15. The method of claim 14, wherein the plurality of active regions extend along the same direction and are aligned in the active extending direction to form a plurality of active rows, and two adjacent active rows of the plurality of active rows are combined to form an active row group.

16. The method of claim 15, wherein the second openings of the shadow mask layer extend along an extension direction of the active regions, and each of the second openings exposes a portion of the active regions in each of the active row groups that are adjacent to each other in two active rows to expose a portion of the channel region; and the initial groove extends along the extending direction of the active region and has the same length dimension as the active region.

17. The method of forming of claim 14, wherein a plurality of the active regions are aligned in an extending direction of the word line to constitute a plurality of active columns, and in two adjacent active columns, a plurality of active regions in one active column each extend along a first direction, a plurality of active regions in the other active column each extend along a second direction, such that the two adjacent active columns are mirror-symmetrical with respect to a center line, and two adjacent active regions in different columns virtually intersect each other along the extending direction of the two active regions on the center line to have virtual connection points; the active areas are connected in series based on the virtual connection points to form a plurality of active strings extending in a wave shape, and two adjacent active strings in the active strings are combined to form an active string group.

18. The method of claim 17, wherein the second openings of the shadow mask layer extend in correspondence with the active string waveforms, and each of the second openings exposes a portion of an active region in each of the active string groups where two active strings are adjacent to each other to expose a portion of the channel region; and the initial grooves extend along the active regions in the corresponding active regions and have the same length dimension as the corresponding active regions.

19. The method of claim 16 or 18, wherein the first opening of the word line mask layer exposes a portion of the initial recess, the portion of the initial recess corresponding to the channel region is used to form the first notch, and the portions of the initial recess located on both sides of the channel region are used to form a second notch, the second notch corresponding to the source drain region.