CN114883335A - Flash memory and layout structure thereof - Google Patents

Abstract

The invention provides a flash memory and a layout structure thereof, wherein a redundant grid graph of the layout structure of the flash memory comprises a redundant selection grid graph and a redundant control grid graph which are connected into a whole, namely the redundant selection grid graph and the redundant control grid graph are integrated. Therefore, the overall size of the redundant grid formed by the redundant control grid and the redundant selection grid is larger, and the contact area of the redundant grid and the bottom film layer is increased. Therefore, in the manufacturing process of the flash memory, the redundant grid is not easy to strip, and particularly, the redundant grid can be prevented from stripping in a cleaning process, so that the problem of stripping of the redundant grid can be solved.

Description

Flash memory and its layout

technical field

The present invention relates to the technical field of semiconductor manufacturing, in particular to a flash memory and a layout structure thereof.

Background technique

As a safe and fast storage body, flash memory has become the most important carrier of data and programs in embedded systems with a series of advantages such as small size, large capacity, low cost, and no loss of data after power failure. In the manufacturing process of forming the flash memory, the redundant gate is easily peeled off in the cleaning process, which will cause pollution to the device and affect the yield of the device.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a flash memory and its layout structure to solve the problem of redundant gate peeling.

In order to solve the above technical problems, the present invention provides a layout structure of a flash memory, including a gate pattern and redundant gate patterns located on both sides of the gate pattern, and the redundant gate pattern includes redundant gate patterns connected as a whole. A selection gate pattern and a redundant control gate pattern, the redundant control gate pattern being closer to the gate pattern than the redundant selection gate pattern.

Optionally, in the layout structure of the flash memory, the redundant gate pattern and the gate pattern are arranged along a first direction, the redundant gate pattern extends along a second direction, and the redundant gate pattern extends along a second direction. The residual gate pattern and the gate pattern are parallel to each other, wherein the second direction and the first direction are perpendicular to each other.

Optionally, in the layout structure of the flash memory, the shape of the redundant gate pattern is a straight strip, and in the second direction, the size of the redundant control gate pattern and the redundant The selection grid shapes are the same size.

Optionally, in the layout structure of the flash memory, the gate pattern includes a selection gate pattern and a control gate pattern arranged along the first direction, and the control gate pattern in the second direction The size is larger than the size of the select gate pattern, and one end of the select gate pattern is aligned with one end of the control gate pattern.

Optionally, in the layout structure of the flash memory, the shape of the selection gate pattern is a straight bar, and the selection gate pattern extends along the second direction; the shape of the control gate pattern is an inverted L. wherein the control gate pattern includes a first partial pattern extending along the first direction and a second partial pattern extending along the second direction, and an end of the second partial pattern away from the first partial pattern is One end of the control gate pattern is aligned.

Optionally, in the layout structure of the flash memory, the layout of the flash memory further includes an active area pattern extending along the first direction and a redundant active area pattern extending along the first direction. Redundant active area patterns at both ends of the active area pattern, the projection of the active area pattern corresponds to the projection of the gate pattern, and the projection of the redundant active area pattern corresponds to the redundant active area pattern The projection of the remaining grid pattern corresponds.

Optionally, in the flash memory layout structure, the flash memory layout further includes a connection pattern extending along the second direction, and the connection pattern is located in the active area pattern and the redundant active area. between area graphics.

Based on the same inventive concept, the present invention also provides a flash memory, comprising: a gate formed on a semiconductor substrate and redundant gates located on both sides of the gate, the redundant gates including redundant selection gates and a redundant control gate in contact with the redundant select gate, the redundant control gate being closer to the gate than the redundant select gate.

Optionally, in the flash memory, the redundant gate and the gate are arranged along a first direction, the redundant gate extends along a second direction, and the redundant gate and all The gates are parallel to each other, wherein the second direction and the first direction are perpendicular to each other.

Optionally, in the flash memory, the shape of the redundant gate is a straight strip, and the size of the redundant control gate and the size of the redundant select gate in the second direction same.

In the layout structure of the flash memory provided by the present invention, the redundant gate pattern includes a redundant selection gate pattern and a redundant control gate pattern that are connected as a whole, that is, the redundant selection gate pattern and the redundant control gate pattern are integrated. During the manufacturing process of the flash memory, the redundant select gates defined by the redundant select gate pattern are in contact with the redundant control gates defined by the redundant control gate pattern, and there is no gap between them. In this way, the overall size of the redundant gate composed of the redundant control gate and the redundant select gate is relatively large, which increases the contact area between the redundant gate and its bottom film layer. Therefore, in the manufacturing process of the flash memory, the redundant gate is not easily peeled off, and in particular, the redundant gate can be prevented from peeling off in the cleaning process, thereby solving the problem of the redundant gate peeling off.

Description of drawings

FIG. 1 is a schematic structural diagram of a layout structure of a flash memory according to an embodiment of the present invention.

FIG. 2 is a schematic structural diagram of a redundant gate pattern and a gate pattern of a layout structure of a flash memory according to an embodiment of the present invention.

3 is a schematic structural diagram of an active area pattern and a redundant active area pattern of a layout structure of a flash memory according to an embodiment of the present invention.

FIG. 4 is a top view of a flash memory according to an embodiment of the present invention.

Fig. 5 is a schematic sectional view taken along the direction A-A' of Fig. 4 .

Fig. 6 is a schematic sectional view taken along the direction B-B' of Fig. 4 .

110-redundant gate pattern; 111-redundant select gate pattern; 112-redundant control gate pattern; 120-gate pattern; 121-control gate pattern; 1211-first partial pattern; 1212-second part pattern; 122-select gate pattern; 130-redundant active area pattern; 140-active area pattern; 150-connection pattern; 160-contact pattern; 200-semiconductor substrate; 201-shallow trench 210-redundant gate; 211-redundant select gate; 212-redundant control gate; 220-gate; 221-control gate; 2211-first part; 2212-second part; 222-select gate; 230-redundant active area; 240-active area; 250-connection; 251-contact; 261-redundant gate oxide; 262-redundant dummy gate; 263-redundant isolation layer; 271-redundant Tunneling oxide layer; 272 - redundant floating gate; 273 - redundant inter-gate dielectric layer.

Detailed ways

The flash memory and its layout structure proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

1 is a schematic structural diagram of a layout structure of a flash memory according to an embodiment of the present invention; FIG. 2 is a schematic structural diagram of redundant gate patterns and gate patterns of the layout structure of a flash memory according to an embodiment of the present invention.

Referring to FIG. 1 in conjunction with FIG. 2, the layout structure of the flash memory includes a gate pattern 120 and redundant gate patterns 110 located on both sides of the gate pattern 120. The redundant gate pattern 110 includes a A redundant selection gate pattern 111 and a redundant control gate pattern 112 are provided. The redundant control gate pattern 112 is closer to the gate pattern 120 than the redundant selection gate pattern 111 .

Specifically, the redundant gate pattern 110 is used to define redundant gates in the flash memory. The redundant selection gate pattern 111 is used for defining redundant selection gates, and the redundant control gate pattern 112 is used for defining redundant control gates. Since the redundant selection gate pattern 111 and the redundant control gate pattern 112 are connected as a whole, the overall size of the redundant gate formed by the redundant control gate and the redundant selection gate can be made larger, and the redundant gate and the redundant gate can be increased. The contact area of the bottom film layer, thus, during the manufacturing process of the flash memory, the redundant gate is not easy to peel off. In particular, the redundant gate can be prevented from peeling off in a cleaning process (eg, an ultrasonic cleaning process), so that the problem of redundant gate peeling can be solved.

As shown in FIG. 2 , the redundant gate patterns 110 and the gate patterns 120 are arranged along the first direction Y. The redundant gate pattern 110 extends along a second direction X, the redundant gate pattern 110 and the gate pattern 120 are parallel to each other, wherein the second direction X and the first direction Y are perpendicular to each other .

In this embodiment, the shape of the redundant gate pattern 110 is a straight strip, and the size of the redundant control gate pattern 112 and the size of the redundant selection gate pattern 111 in the second direction X are The same, that is, the length of the redundant control gate pattern 112 is the same as the length of the redundant selection gate pattern 111 . In this way, the ends of the redundant control gate patterns 112 are aligned with the ends of the redundant select gate patterns 111 . During the manufacturing process of the flash memory, the redundant control gates defined by the redundant control gate patterns 112 And the redundant select gates defined by the redundant select gate patterns 111 are not easy to peel off, and in particular, peeling off during the cleaning process can be avoided, thereby solving the problem of redundant gate peeling off.

As shown in FIG. 2 , the gate pattern 120 includes a control gate pattern 121 and a selection gate pattern 122 arranged along the first direction Y. As shown in FIG. The selection gate pattern 122 is used to define a selection gate, and the control gate pattern 121 is used to define a control gate. In the second direction X, the size of the control gate pattern 121 is larger than that of the selection gate pattern 122 , and one end of the selection gate pattern 122 is aligned with one end of the control gate pattern 121 . With this arrangement, the difficulty of preparing the selection gate and the control gate can be reduced.

In this embodiment, the shape of the selection gate pattern 122 is a straight bar, and the selection gate pattern 122 extends along the second direction X. As shown in FIG.

As shown in FIG. 2 , the shape of the control gate pattern 121 is an inverted L shape, wherein the control gate pattern 121 includes a first partial pattern 1211 extending along the first direction Y and a first partial pattern 1211 extending along the second direction X Two-part pattern 1212 , one end of the second partial pattern 1212 away from the first partial pattern 1211 is aligned with one end of the select gate pattern 122 . The second part 1212 is used to define the main body part of the control gate, and the first part 1211 is used to define the part of the control gate electrically connected to the outside (ie, the part used to electrically connect with the contact plug).

In this embodiment, the size of the redundant gate pattern 110 in the second direction X may be the same as the size of the control gate pattern 121 , that is, the length of the redundant gate pattern 110 may be the same as that of the control gate pattern 121 of the same length. In this way, the uniformity of the select gates and the control gates in the flash memory can be improved, the variance of the size of the control gates in the flash memory can be improved, and the variance of the sizes of the select gates in the flash memory can be improved.

FIG. 3 is a schematic structural diagram of an active area pattern 140 and a redundant active area pattern 130 of a layout structure of a flash memory according to an embodiment of the present invention. As shown in FIG. 3 , the layout structure of the flash memory further includes redundant active area patterns 130 extending along the first direction Y and active area patterns 140 extending along the first direction Y, the redundant active area patterns 140 extending along the first direction Y. The area pattern 130 is connected to both ends of the active area pattern 140, the projection of the active area pattern 140 corresponds to the projection of the gate pattern 120, and the projection of the redundant active area pattern 130 is the same as the projection of the gate pattern 120. The projection of the redundant gate pattern 110 corresponds to.

Specifically, the gate pattern 120 is located on the active region pattern 140 , and the redundant gate pattern 110 is located on the redundant active region pattern 130 . In this embodiment, the active area pattern 140 is used to define the active area, and the redundant active area pattern 130 is used to define the redundant active area. The existence of the redundant active area pattern 130 can improve the The uniformity of the active area, such as improving the uniformity of the surface of the active area after chemical mechanical polishing.

In this embodiment, the layout structure of the flash memory further includes a connection pattern 150 extending along the second direction X, and the connection pattern 150 is located between the active area pattern 140 and the redundant active area pattern 130 , And the connection pattern 150 is connected with the active area pattern 140 and the redundant active area pattern 130 . The connection pattern 150 may be used to define an electrical connection structure between the active regions to electrically connect the active regions.

As shown in FIG. 3 , the layout structure of the flash memory further includes a contact pattern 160 connected to the active area pattern 140 for defining contact holes.

In this embodiment, the layout structure of the flash memory can be used to form the non-volatile flash memory.

FIG. 4 is a top view of a flash memory according to an embodiment of the present invention. Fig. 5 is a schematic sectional view taken along the direction A-A' of Fig. 4 . Fig. 6 is a schematic sectional view taken along the direction B-B' of Fig. 4 . Based on the same inventive concept, an embodiment of the present invention provides a flash memory. As shown in FIG. 4 , the flash memory includes a gate 220 formed on a semiconductor substrate 200 and redundant electrodes located on both sides of the gate 220 . Gate 210, the redundant gate 210 includes a redundant selection gate 211 and a redundant control gate 212, the redundant control gate 212 is in contact with the redundant selection gate 211, and the redundant control gate 212 is relatively The redundant select gate 211 is close to the gate 220 .

Since the redundant control gate 212 is in contact with the redundant select gate 211, there is no gap therebetween. In this way, the overall size of the redundant gate 210 formed by the redundant control gate 212 and the redundant select gate 211 is relatively large, which increases the contact area between the redundant gate 210 and its bottom film layer, thus, in the flash memory During the manufacturing process, the redundant gate 210 is not easily peeled off. In particular, peeling off of the redundant gate 210 during the cleaning process can be avoided, so that the problem of peeling off of the redundant gate 210 can be solved.

As shown in FIG. 5 and FIG. 6 , the semiconductor substrate 200 may be a silicon substrate, and a shallow trench isolation structure 201 is formed in the semiconductor substrate 200 , and the shallow trench isolation structure 201 is used to define the semiconductor substrate 200 active area.

As shown in FIG. 4 , the redundant gates 210 and the gates 220 are arranged along a first direction Y; the redundant gates 210 extend along a second direction X, and the second direction X and the The first directions Y are perpendicular to each other.

In this embodiment, the cross-sectional shape (cross-sectional shape in the horizontal direction) of the redundant gate 210 is a straight strip, and the size of the redundant control gate 212 in the second direction X is the same as the size of the redundant control gate 212 in the second direction X. The redundant select gates 211 have the same size, that is, the redundant control gates 212 have the same length as the redundant select gates 211 . In this way, the ends of the redundant control gates 212 are aligned with the ends of the redundant selection gates 211 , which can reduce the area occupied by the redundant control gates 212 and the redundant selection gates 211 .

In this embodiment, the flash memory further includes a gate 220, and the gate 220 includes a control gate 221 and a selection gate 222 arranged along the first direction Y, wherein the selection gate 222 can be used to form a selection transistor, and the control gate 221 can be used to form a control transistor. The size of the control gate 221 in the second direction X may be larger than that of the selection gate 222 . In other embodiments, the size of the control gate 221 may be the same as the size of the select gate 222 .

In this embodiment, one end of the select gate 222 is aligned with one end of the control gate 221 . In this way, the fabrication difficulty of the selection gate 222 and the control gate 221 can be reduced.

In this embodiment, the cross-sectional shape of the selection gate 222 is a straight strip, and the selection gate 222 extends along the second direction X. As shown in FIG. The shape of the control gate 221 is an inverted L shape, wherein the control gate 221 includes a first portion 2211 extending along the first direction Y and a second portion 2212 extending along the second direction X, the second portion One end of 2212 away from the first portion 2211 is aligned with one end of the select gate 222 . The second part 2212 is used to form the main body of the control gate 221 , and the first part 2211 is used to form the part for the control gate 221 to be electrically connected to the outside (ie, the part to be electrically connected to the contact plug).

In this embodiment, the size of the redundant gate 210 in the second direction X may be the same as the size of the control gate 221 , that is, the length of the redundant gate 210 may be the same as the length of the control gate 221 . In this way, the uniformity of the redundant gate 210 and the control gate 221 in the flash memory can be improved, and the size difference between the control gate 221 and the redundant gate 210 in the flash memory can be improved.

As shown in FIG. 5 , the flash memory further includes a redundant gate oxide layer 261 and a redundant dummy gate 262 located between the semiconductor substrate 200 and the redundant select gate 211, and the redundant dummy gate 262 covers the redundant gate. Residual gate oxide layer 261. Further, there are trenches between the redundant dummy gates 262 , and the redundant select gate 211 fills the trenches between the redundant dummy gates 262 and covers the redundant dummy gates 262 . And, the flash memory further includes a redundant isolation layer 263, the redundant isolation layer 263 covers the bottom wall and sidewall of the trench between the redundant dummy gates 262 for isolation.

As shown in FIG. 6 , the flash memory further includes a redundant tunnel oxide layer 271 and a redundant floating gate 272 located between the semiconductor substrate 200 and the redundant control gate 212, and the redundant floating gate 272 covers the Redundant tunnel oxide layer 271 . The material of the redundant floating gate 272 may be doped polysilicon. There are trenches between the redundant floating gates 272 , and the redundant control gate 212 fills the trenches between the redundant floating gates 272 and extends to cover the redundant floating gates 272 . Further, a redundant inter-gate dielectric layer 273 is also formed between the redundant floating gate 272 and the redundant control gate 212 , and the redundant inter-gate dielectric layer 273 is used for the connection between the redundant floating gate 272 and the redundant control gate 212 . isolation between.

In this embodiment, the flash memory further includes a tunnel oxide layer and a floating gate (not shown) located between the semiconductor substrate 200 and the control gate 221 , and the floating gate covers the tunnel oxide layer. The material of the floating gate may be doped polysilicon, and the floating gate is used for storing electrons. Electrons in the floating gate can tunnel through the tunnel oxide layer to the semiconductor substrate. The material of the tunnel oxide layer may be silicon oxide. A trench is formed between the floating gates, and the control gate 221 fills the trench between the floating gates and extends to cover the control gate 221 . Further, an inter-gate dielectric layer (not shown) is also formed between the floating gate and the control gate 221 , and the inter-gate dielectric layer is used for isolation between the floating gate and the control gate 221 .

In this embodiment, the flash memory further includes a gate oxide layer and a dummy gate located between the semiconductor substrate 200 and the selection gate 222 , the dummy gate covers the gate oxide layer, wherein the material of the gate oxide layer is , The material of the tunnel oxide layer, the material of the redundant tunnel oxide layer 271 and the material of the redundant gate oxide layer 261 are all silicon oxide, and can be formed in the same process step.

There are trenches between the dummy gates, and the select gate 222 fills the trenches between the dummy gates and covers the dummy gates. And, the flash memory further includes an isolation layer (not shown), the isolation layer covers the bottom wall and the sidewall of the trench between the dummy gates for isolation.

In this embodiment, both the material of the dummy gate and the material of the control gate 221 may be doped polysilicon. The dummy gate, redundant dummy gate 262, floating gate, and redundant floating gate 272 may be formed in the same process. The redundant control gate 212, the redundant select gate 211, the select gate and the control gate may be formed in the same process to save process steps.

In this embodiment, the flash memory may be a non-volatile flash memory.

To sum up, in the flash memory and the layout structure thereof provided by the present invention, the redundant gate pattern of the layout structure of the flash memory includes the redundant selection gate pattern and the redundant control gate pattern which are connected as a whole, that is, the redundant selection gate pattern It is integrated with the redundant control gate pattern. During the manufacturing process of the flash memory, the redundant selection gate defined by the redundant selection gate pattern is in contact with the control gate defined by the redundant control gate pattern. There are no gaps. In this way, the overall size of the redundant gate composed of the redundant control gate and the redundant select gate is relatively large, which increases the contact area between the redundant gate and its bottom film layer. Therefore, in the manufacturing process of the flash memory, the redundant gate is not easily peeled off. In particular, the redundant gate can be prevented from peeling off in the cleaning process, so that the problem of the redundant gate peeling can be solved.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (10)

1. A layout structure of a flash memory, characterized in that it comprises a gate pattern and redundant gate patterns located on both sides of the gate pattern, and the redundant gate pattern comprises a redundant selection gate pattern connected as a whole and redundant control gate patterns, the redundant control gate patterns being closer to the gate patterns than the redundant select gate patterns. 2 . The layout structure of the flash memory according to claim 1 , wherein the redundant gate pattern and the gate pattern are arranged along a first direction, and the redundant gate pattern extends along a second direction. 3 . , the redundant gate pattern and the gate pattern are parallel to each other, wherein the second direction and the first direction are perpendicular to each other. 3 . The layout structure of the flash memory according to claim 2 , wherein the shape of the redundant gate pattern is a straight strip, and the size of the redundant control gate pattern in the second direction is equal to 3. 4 . The redundant selection gate patterns are of the same size. 4. The layout structure of the flash memory according to claim 2, wherein the gate pattern comprises a control gate pattern and a selection gate pattern arranged along the first direction, the control gate pattern and the selection gate pattern The gate patterns are parallel to each other, the size of the control gate pattern is larger than that of the selection gate pattern in the second direction, and one end of the selection gate pattern is aligned with one end of the control gate pattern. 5. The layout structure of the flash memory according to claim 4, wherein the shape of the selection gate pattern is a straight bar, and the selection gate pattern extends along the second direction; The shape is an inverted L shape, wherein the control gate pattern includes a first partial pattern extending along the first direction and a second partial pattern extending along the second direction, the second partial pattern being away from the first portion One end of the pattern is aligned with one end of the control gate pattern. 6. The flash memory layout structure of claim 2, wherein the flash memory layout further comprises active area patterns extending along the first direction and redundant active areas extending along the first direction area pattern, the redundant active area pattern is connected to both ends of the active area pattern, the projection of the active area pattern corresponds to the projection of the gate pattern, the redundant active area pattern The projection of is corresponding to the projection of the redundant gate pattern. 7. The layout structure of the flash memory according to claim 6, wherein the layout of the flash memory further comprises a connection pattern extending along the second direction, and the connection pattern is located between the active area pattern and the Redundant active area between graphics. 8. A flash memory, comprising: A gate formed on a semiconductor substrate and redundant gates located on both sides of the gate, the redundant gates include redundant select gates and redundant control gates, the redundant control gates are connected with the redundant gates. The redundant select gates are in contact with each other, and the redundant control gates are closer to the gates than the redundant select gates. 9 . The flash memory of claim 8 , wherein the redundant gate and the gate are arranged along a first direction, the redundant gate extends along a second direction, and the redundant gate The gate and the gate are parallel to each other, wherein the second direction and the first direction are perpendicular to each other. 10 . The flash memory according to claim 9 , wherein the cross-sectional shape of the redundant gate is straight, and the size of the redundant control gate in the second direction is the same as the redundant control gate. 11 . The remaining selection gates are the same size.

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