CN112071844A

CN112071844A - Mask plate of flash memory device and manufacturing method

Info

Publication number: CN112071844A
Application number: CN202010986500.2A
Authority: CN
Inventors: 陈宏�
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2020-09-18
Filing date: 2020-09-18
Publication date: 2020-12-11
Anticipated expiration: 2040-09-18
Also published as: CN112071844B

Abstract

The invention provides a mask of a flash memory device and a manufacturing method thereof, wherein the mask of the flash memory device comprises an active area mask and a floating gate mask, and the active area mask comprises: the manufacturing method of the flash memory device comprises a storage mask area and a peripheral mask area, wherein a first active area graph is arranged at the junction of the storage mask area and the peripheral mask area, in the manufacturing method of the flash memory device, a first active area can be defined at the junction of the storage area and the peripheral area through the active area mask, and when a dielectric layer, a control gate layer, a floating gate layer and a floating gate oxide layer of the peripheral area are etched, if over-etching is generated in the etching process, an etched object of the over-etching is a semiconductor substrate of the first active area.

Description

Mask plate of flash memory device and manufacturing method

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a mask plate of a flash memory device and a manufacturing method thereof.

Background

At present, a Flash memory device (also called Flash memory) has become the mainstream of a non-volatile memory, a Floating Gate (FG) and a Tunnel Oxide layer (Tunnel Oxide) are added to a memory cell of the Flash memory device based on a conventional MOS transistor structure, and an Isolation region is further prepared by a Shallow Trench Isolation (STI) technique in the present Flash memory device.

Fig. 1 is a schematic structural diagram of a flash memory device according to the prior art. A typical method of manufacturing a flash memory device in the prior art generally includes: a first step, providing a semiconductor substrate 10, sequentially forming a floating gate oxide layer 20 and a floating gate layer 30 on the semiconductor substrate 10, and etching the floating gate layer 30, the floating gate oxide layer 20 and the semiconductor substrate 10 to form a shallow trench, and filling an insulating medium material (namely, an STI HDPDE process) in the shallow trench to form a shallow trench isolation Structure (STI)40, wherein the shallow trench isolation structure can define active regions of a storage region I and a peripheral region II; then, performing a second step, forming a control gate layer (not shown) on the floating gate layer 30, forming a dielectric layer 50 on the control gate layer, etching the dielectric layer 50, the control gate layer, the floating gate layer 30 and the floating gate oxide layer 20 of the storage region I to form an opening, and depositing a material layer 60 in the opening; next, as shown in fig. 2, a third step is performed to etch the dielectric layer 50, the control gate layer, the floating gate layer 30 and the floating gate oxide layer 20 in the peripheral region II. However, in this step, an over-etching is usually caused, and the over-etching causes a deeper groove to be formed at the boundary between the peripheral region and the storage region, and in a subsequent process, the groove is more likely to form a defect, for example, a process layer is peeled off into the groove, so that the performance of the flash memory device may be reduced. Accordingly, it would be a problem to those skilled in the art to provide an improved method of manufacturing a flash memory device.

Disclosure of Invention

The invention aims to provide a mask plate of a flash memory device and a manufacturing method thereof, which aim to solve the problem of defects caused by a groove at the junction of a peripheral area and a storage area.

In order to solve the above technical problem, the present invention provides a mask for a flash memory device, the mask comprising:

the mask comprises an active area mask, a mask body and a mask layer, wherein the active area mask comprises a storage mask area and a peripheral mask area, and a first active area graph is formed at the junction of the storage mask area and the peripheral mask area;

the floating gate mask comprises a plurality of floating gate patterns, and the floating gate patterns are arranged in parallel along a first direction and cross over the first active region pattern along a second direction.

Optionally, in the mask of the flash memory device, a plurality of second active region patterns are formed in the storage mask region and the peripheral mask region, and the plurality of second active region patterns in the storage mask region and the peripheral mask region are arranged in parallel along the second direction; wherein the first direction is perpendicular to the second direction.

Optionally, in the mask of the flash memory device, the plurality of floating gate patterns cross the plurality of second active region patterns along the second direction.

Optionally, in the mask of the flash memory device, the floating gate pattern includes a curved pattern and two straight bar patterns respectively connected to two ends of the curved pattern, the curved pattern includes two curved portions that are opposite in concave direction and are connected into a whole, and the curved portion has a notch.

Optionally, in the mask of the flash memory device, the mask of the flash memory device further includes a word line contact hole mask, the word line contact hole mask includes a plurality of contact hole patterns, and the plurality of contact hole patterns respectively correspond to the plurality of notches of the bending portion.

Based on the same inventive concept, the invention also provides a manufacturing method of the flash memory device, and the mask adopting the flash memory device comprises the following steps:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a storage region and a peripheral region, and a floating gate oxide layer and a floating gate layer are sequentially formed on the semiconductor substrate;

adopting an active area mask plate to define a first active area at the junction of the storage area and the peripheral area, and defining a plurality of second active areas in the semiconductor substrate of the storage area and the peripheral area;

sequentially forming a control gate layer and a dielectric layer, wherein the control gate layer covers the floating gate layer;

etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer of the storage region to form an opening by adopting a floating gate mask, wherein part of the surface of the semiconductor substrate is exposed by the opening;

sequentially forming a tunneling oxide layer and a word line layer in the opening, wherein the tunneling oxide layer covers the inner wall of the opening, and the word line layer covers the tunneling oxide layer and fills the opening;

and etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer in the peripheral region, and stopping etching on the surface of the semiconductor substrate.

Optionally, in the manufacturing method of the flash memory device, the method for defining the first active region at the boundary between the storage region and the peripheral region, and defining the plurality of second active regions in the semiconductor substrate of the storage region and the peripheral region includes:

the floating gate mask is adopted to etch the floating gate layer, the floating gate oxide layer and the semiconductor substrate to form a shallow trench;

forming an isolation layer, wherein the isolation layer fills the shallow trench to form a shallow trench isolation structure, and the shallow trench isolation structure defines the first active region and the plurality of second active regions; the control grid layer also covers the shallow trench isolation structure.

Optionally, in the method for manufacturing the flash memory device, the method for etching the dielectric layer, the control gate layer, the floating gate layer, and the floating gate oxide layer of the storage region to form an opening includes:

etching the dielectric layer by using the floating gate mask to form a first penetrating opening in the dielectric layer, wherein part of the control gate layer is exposed out of the first opening;

forming a first side wall, wherein the first side wall covers the side wall of the first opening;

etching the exposed control gate layer by using the first side wall as a mask to form a through second opening in the control gate layer and expose part of the floating gate layer;

forming a second side wall, wherein the second side wall covers the side wall of the second opening and extends to cover the first side wall;

etching the exposed floating gate layer by using the second side wall as a mask to form a third opening, wherein the third opening extends into the floating gate oxide layer; wherein the third opening communicates with the second opening and the first opening and constitutes the opening.

Optionally, in the manufacturing method of the flash memory device, after the dielectric layer, the control gate layer, the floating gate layer, and the floating gate oxide layer in the peripheral region are etched, the manufacturing method of the flash memory device further includes:

removing the dielectric layer to expose the control gate layer covered by the dielectric layer;

and etching the exposed control gate layer, the floating gate layer and the floating gate oxide layer, and stopping etching on the surface of the semiconductor substrate to form a storage unit.

Optionally, in the manufacturing method of the flash memory device, after the memory cell is formed, the manufacturing method of the flash memory device further includes:

forming an interlayer film layer covering the memory cell;

and etching the interlayer film layer by adopting a word line contact hole mask to form a word line contact hole, wherein the word line contact hole is aligned to the word line layer.

In the mask of the flash memory device and the manufacturing method thereof provided by the invention, the mask of the flash memory device comprises an active area mask and a floating gate mask, and the active area mask comprises: the storage mask region and the peripheral mask region are provided with a first active region graph, the active region mask can define a first active region at the junction of the storage region and the peripheral region, when a dielectric layer, a control gate layer, a floating gate layer and a floating gate oxide layer of the peripheral region are etched, etching stops on the surface of a semiconductor substrate, if over-etching is generated, an etched object of the over-etching is the semiconductor substrate of the first active region, compared with the prior art, the etching selection ratio can be improved, so that grooves can be prevented from being formed in the side wall of a storage unit, defects are avoided, and the performance of a flash memory device is improved.

Drawings

FIGS. 1-2 are schematic structural diagrams of a prior art flash memory device;

fig. 3 is a schematic structural diagram of a mask of a flash memory device according to an embodiment of the present invention;

fig. 4 is a schematic flow chart illustrating a method for manufacturing a flash memory device according to an embodiment of the present invention;

fig. 5 to 13 are schematic structural diagrams formed by a method of manufacturing a flash memory device according to an embodiment of the present invention;

wherein the reference numbers are as follows:

10-a semiconductor substrate; 20-floating gate oxide layer; 30-a floating gate layer; 40-shallow trench isolation structures; 50-a dielectric layer;

101-flash memory device mask; 102-storage mask area; 103-peripheral mask region; 104-a first active area pattern; 105-a second active area pattern; 106-floating gate pattern; 1041-a graph of curves; 1042-straight bar pattern; 107-contact hole pattern; 100-a semiconductor substrate; 111-a storage area; 112-a peripheral region; 113-shallow trenches; 120-shallow trench isolation structures; 130-floating gate oxide layer; 140-a floating gate layer; 150-a control gate layer; 160-a dielectric layer; 171-a first opening; 172-first side wall; 173-a second opening; 174-second sidewall; 175-a third opening; 180-tunneling the oxide layer; 190-word line layer.

Detailed Description

The mask and the manufacturing method of the flash memory device according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

The inventor researches and discovers that the reason why the deeper groove is formed at the boundary between the peripheral region and the storage region in the prior art is that when the shallow trench isolation structure is defined as the active region, the shallow trench isolation structure is usually formed between the storage region and the peripheral region, that is, the shallow trench isolation structure is formed at the boundary between the storage region and the peripheral region, and due to the existence of the shallow trench isolation structure, when a process layer between the storage region and the peripheral region is etched later (for example, when a memory cell is formed), etching is stopped on the surface of the shallow trench isolation structure. Because the shallow trench isolation structure is usually made of an oxide layer, the shallow trench isolation structure is etched with a low selection ratio by an etching process, so that large over-etching is caused, a deep groove is formed at the junction of the storage region and the peripheral region, and the groove is easy to form defects. Based on the above, the invention provides a mask plate of a flash memory device and a manufacturing method thereof, which are used for solving the defect problem caused by a groove at the junction of a peripheral area and a storage area of the flash memory device.

Next, the mask and the manufacturing method of the flash memory device according to the present invention will be described in more detail with reference to the embodiments and the drawings.

Please refer to fig. 3, which is a schematic diagram of a mask structure of a flash memory device according to an embodiment of the present invention. As shown in fig. 3, the mask 101 of the flash memory device includes an active area mask, a floating gate mask, and a word line contact hole mask.

The active area mask comprises a storage mask area 102 and a peripheral mask area 103, a first active area graph 104 is formed at the junction of the storage mask area 102 and the peripheral mask area 103, and the first active area graph 104 extends along a first direction and is in a straight strip shape.

Specifically, a plurality of second active region patterns 105 are formed in the memory mask region 120 and the peripheral mask region 103, the plurality of second active region patterns 105 in the memory mask region 102 and the peripheral mask region 103 are arranged in parallel along the second direction, and a space exists between the plurality of second active region patterns 105. Wherein the first direction is perpendicular to the second direction. The second active region patterns 105 may define active regions in the semiconductor substrate, a region between two adjacent second active region patterns 105, or a region between the second active region patterns 105 and the first active region patterns 104 may define isolation regions of the semiconductor substrate, for example, shallow trench isolation structures of the isolation regions. Here, the first active region pattern 104 and the second active region pattern 105 have the same size.

The floating gate mask is used for defining a floating gate on the semiconductor substrate. Specifically, the floating gate mask includes a plurality of floating gate patterns 106, and the floating gate patterns 106 are arranged in parallel along a first direction and cross over the first active region pattern 104 along the second direction; further, the plurality of floating gate patterns 106 cross the plurality of second active region patterns 105 in the second direction.

Specifically, the floating gate pattern 106 includes a curved pattern 1014 and two straight bar patterns 1042 connected to two ends of the curved pattern 1014, and the curved pattern 1014 includes two curved portions that are concave and opposite and are connected together. Further, the curved pattern 1014 is S-shaped, and the curved pattern 1014 is S-shaped to increase the process window of the contact hole. Here, the curved patterns 1014 of the two adjacent floating gate patterns 106 may be arranged in a staggered manner, and the curved portions 1014 of the two adjacent floating gate patterns 106 may be arranged in a staggered manner.

The word line contact hole mask is used for forming word line contact holes. Specifically, the word line contact hole mask includes a plurality of contact hole patterns 107, and the plurality of contact hole patterns 107 respectively correspond to the recesses of the plurality of bent portions, that is, one contact hole pattern 107 corresponds to one recess of the bent portion, or a projection of each contact hole pattern 107 is located in the recess of each bent portion.

Please refer to fig. 4, which is a flowchart illustrating a method for manufacturing a flash memory device according to an embodiment of the present invention. Based on the same inventive concept, the invention also provides a manufacturing method of the flash memory device, and the manufacturing method of the flash memory device adopts the mask of the flash memory device. As shown in fig. 4, the method of manufacturing the flash memory device includes:

step S1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a storage region and a peripheral region, and a floating gate oxide layer and a floating gate layer are sequentially formed on the semiconductor substrate;

step S2: adopting an active area mask plate to define a first active area at the junction of the storage area and the peripheral area, and defining a plurality of second active areas in the semiconductor substrate of the storage area and the peripheral area;

step S3: sequentially forming a control gate layer and a dielectric layer, wherein the control gate layer covers the floating gate layer;

step S4: etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer of the storage region to form an opening by adopting a floating gate mask, wherein part of the surface of the semiconductor substrate is exposed by the opening;

step S5, sequentially forming a tunneling oxide layer and a word line layer in the opening, wherein the tunneling oxide layer covers the inner wall of the opening, and the word line layer covers the tunneling oxide layer and fills the opening;

and step S6, etching the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer in the peripheral area, and stopping etching on the surface of the semiconductor substrate.

Next, the above steps will be described in more detail with reference to fig. 5 to 13, and fig. 5 to 13 are schematic structural views formed by the method for manufacturing a flash memory device according to the present invention.

First, as shown in fig. 5, step S1 is performed to provide a semiconductor substrate 100, the semiconductor substrate 100 including a storage region 111 and a peripheral region 112; a floating gate oxide layer 130 and a floating gate layer 140 are sequentially formed on the semiconductor substrate 100, the semiconductor substrate 100 provides an operating platform for subsequent processes, and the semiconductor substrate 100 may be made of silicon. Next, a floating gate oxide layer 130 may be formed on the surface of the semiconductor substrate 100 by using a low pressure chemical vapor deposition, atomic layer deposition, thermal oxidation, or molecular beam epitaxy, and the material of the floating gate oxide layer 130 may be silicon oxide, such as silicon dioxide, and is preferably silicon dioxide, so as to enhance the interface adhesion between layers and provide for the isolation between the semiconductor substrate 100 and the floating gate layer 140.

Next, a floating gate layer 140 may be formed on the floating gate oxide layer 130 by a deposition method, and the material of the floating gate layer 140 may be polysilicon, which is used to form a floating gate, and may trap or lose electrons, so that the finally formed flash memory device has functions of storage and erasure.

Next, step S2 is performed to use an active area mask to define a first active area at the boundary between the storage area and the peripheral area, and to define a plurality of second active areas in the semiconductor substrate in the storage area and the peripheral area.

Specifically, the method for defining a first active region at the boundary of the storage region and the peripheral region and defining a plurality of second active regions in the semiconductor substrate of the storage region and the peripheral region comprises the following steps: the floating gate mask is used to etch the floating gate layer 140, the floating gate oxide layer 130 and the semiconductor substrate 100 to form the shallow trench 113. Further, the method for forming the shallow trench 113 includes: forming a pad silicon nitride layer (not shown) on the floating gate layer 140; then, forming a graphical photoresist layer on the pad nitride layer through the active area mask plate; and then, etching the pad nitride layer, the floating gate layer 140, the floating gate oxide layer 130 and the semiconductor substrate 100 by using the patterned photoresist layer as a mask to form the shallow trench 113, i.e. the shallow trench 113 is located in the pad nitride layer, the floating gate layer 140, the floating gate oxide layer 130 and the semiconductor substrate 100. That is, the shallow trench 113 penetrates the pad nitride layer, the floating gate layer 140 and the floating gate oxide layer 130. Then, the patterned photoresist layer is removed.

Next, as shown in fig. 6, forming an isolation layer, where the isolation layer fills the shallow trench 113 to form a shallow trench isolation structure 120, where the shallow trench isolation structure 120 defines the first active region and the plurality of second active regions; and removing the pad nitride layer. The first active region and the second active region have the same size and are positioned differently.

Next, as shown in fig. 7, step S3 is executed to sequentially form a control gate layer 150 and a dielectric layer 160, where the control gate layer 150 covers the floating gate layer 140 and the shallow trench isolation structure 120; the control gate layer 150 may be a polysilicon layer used for forming a control gate later, and the dielectric layer 160 may be a nitride layer, for example, a silicon nitride layer. Preferably, an inter-gate dielectric layer is further formed between the floating gate layer 140 and the control gate layer 150, and the inter-gate dielectric layer may be silicon oxide or a stacked structure of first silicon oxide, silicon nitride and second silicon oxide (ONO), which is used for isolation between the floating gate layer 140 and the control gate layer 150. In this embodiment, in order to better understand the gist of the present invention, a description of the change of the inter-gate dielectric layer in each step is omitted, and the illustration of the inter-gate dielectric layer is also omitted in fig. 5 to 13.

Next, step S4 is executed, as shown in fig. 8 to 9, a floating gate mask is used to etch the dielectric layer 160, the control gate layer 150, the floating gate layer 140, and the floating gate oxide layer 130 of the storage region 111, so as to form an opening, where a portion of the surface of the semiconductor substrate 100 is exposed.

Specifically, the method for etching the dielectric layer 160, the control gate layer 150, the floating gate layer 140, and the floating gate oxide layer 130 of the storage region 11 to form the opening 160 includes: as shown in fig. 8, the floating gate mask is used to etch the dielectric layer 160, so as to form a first opening 171 penetrating through the dielectric layer 160, and a portion of the control gate layer 150 is exposed by the first opening 171.

Then, as shown in fig. 9, a first sidewall layer 172 is formed, and the first sidewall layer 172 covers the sidewall of the first opening 171; then, etching the exposed control gate layer 150 by using the first sidewall layer 172 as a mask, so as to form a second through opening 173 in the control gate layer 150 and expose a portion of the floating gate layer; next, forming a second sidewall layer 174 covering the sidewalls of the second opening 173 and extending to cover the first sidewall; then, as shown in fig. 10, the exposed floating gate layer is etched by using the second sidewalls 172 as a mask to form a third opening 175, wherein the third opening 175 extends into the floating gate oxide layer 130; wherein the third opening 175 is in communication with the second opening 173 and the first opening 171 and constitutes the opening, that is, the opening includes the first opening 171, the second opening 173 and the third opening 175. The first sidewall layer 172 may be made of silicon oxide, and the second sidewall layer 174 may be made of silicon nitride.

Next, as shown in fig. 11, step S5 is performed to sequentially form a tunnel oxide layer 180 and a word line layer 190 in the opening 173, in which the tunnel oxide layer 180 covers inner walls of the opening (i.e., sidewalls and a bottom wall of the opening), and the word line layer 190 covers the tunnel oxide layer 180 and fills the opening. The tunnel oxide layer 180 serves to isolate the word line layer 190 from the floating gate layer 140, the control gate layer 150, and the semiconductor substrate 100.

Next, step S6 is executed, as shown in fig. 12, the dielectric layer 160, the control gate layer 150, the floating gate layer 140 and the floating gate oxide layer 130 in the peripheral region 112 are etched, and the etching stops on the surface of the semiconductor substrate 100 in the active region. Specifically, a patterned photoresist layer is formed, and the patterned photoresist layer covers the semiconductor substrate 100 of the storage region 111, that is, the patterned photoresist layer covers the dielectric layer 160 of the storage region 111 and the word line layer 190. Then, the dielectric layer 160, the control gate layer 150, the floating gate layer 140 and the floating gate oxide layer 130 in the peripheral region 112 are etched by using the patterned photoresist layer as a mask, and the etching stops on the surface of the semiconductor substrate 100 in the active region. Since the first active region is defined at the boundary of the storage region 111 and the peripheral region 112, the surface of the semiconductor substrate 100 stopped at the first active region can be etched during the etching process. Because the semiconductor substrate 100 is made of silicon, when over-etching occurs in the etching process, the semiconductor substrate 100 is less damaged by the over-etching, and compared with the prior art, the etching selection ratio of the etching process can be improved, so that a groove is prevented from being formed at the junction of the storage region 111 and the peripheral region 112, further, the defect caused by the groove is avoided, and the performance of the flash memory device is improved.

Next, as shown in fig. 13, the dielectric layer 160 is removed; then, exposing the control gate layer 150 covered by the dielectric layer; then, the exposed control gate layer 150, the floating gate layer 140 and the floating gate oxide layer 130 are etched, and the etching stops on the surface of the semiconductor substrate 100, so as to form a memory cell.

Finally, forming an interlayer film layer, wherein the interlayer film layer covers the storage unit; then, a word line contact hole mask is used to etch the interlayer film layer to form word line contact holes, which are aligned to the word line layer 190. The word line contact holes expose the surface of the word line layer 190, and conductive layers may be filled in the word line contact holes to form word line contact structures, so that the word lines are electrically connected to an external circuit through the word line contact structures, where the conductive layers may be made of metal, such as tungsten or copper.

In summary, in the mask of the flash memory device and the manufacturing method thereof provided by the invention, the first active region can be defined at the boundary of the storage region and the peripheral region through the active region mask, and when the dielectric layer, the control gate layer, the floating gate layer and the floating gate oxide layer of the peripheral region are etched and stopped on the surface of the semiconductor substrate, the first active region is defined at the boundary of the storage region and the peripheral region, so that the etching can be stopped on the surface of the semiconductor substrate of the first active region.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A mask for a flash memory device, comprising:

2. The mask of the flash memory device according to claim 1, wherein a plurality of second active region patterns are formed in each of the memory mask region and the peripheral mask region, and the plurality of second active region patterns in the memory mask region and the peripheral mask region are arranged in parallel along the second direction; wherein the first direction is perpendicular to the second direction.

3. The reticle for a flash memory device according to claim 2, wherein the plurality of floating gate patterns cross the plurality of second active region patterns in the second direction.

4. The mask for flash memory device according to claim 1, wherein the floating gate pattern comprises a curved pattern and two straight bar patterns respectively connected to two ends of the curved pattern, the curved pattern comprises two curved portions having opposite concave directions and integrally connected, and the curved portion has a recess.

5. The mask for a flash memory device according to claim 4, further comprising a word line contact hole mask including a plurality of contact hole patterns corresponding to the recesses of the plurality of bent portions, respectively.

6. A method of manufacturing a flash memory device using the mask for a flash memory device according to claim 1, comprising:

7. The method of manufacturing a flash memory device according to claim 6, wherein the method of defining a first active region at an intersection of the storage region and the peripheral region, and the method of defining a plurality of second active regions in the semiconductor substrate of the storage region and the peripheral region comprises:

8. The method of manufacturing a flash memory device according to claim 6, wherein the method of etching the dielectric layer, the control gate layer, the floating gate layer, and the floating gate oxide layer of the storage region to form an opening comprises:

9. The method of manufacturing a flash memory device according to claim 6, wherein after etching the dielectric layer, the control gate layer, the floating gate layer, and the floating gate oxide layer in the peripheral region, the method of manufacturing a flash memory device further comprises:

10. The method of manufacturing a flash memory device according to claim 9, wherein after the memory cell is formed, the method of manufacturing a flash memory device further comprises:

forming an interlayer film layer covering the memory cell;