CN110880508A - Transistor combination structure of integrated circuit memory and forming method thereof - Google Patents

Abstract

The invention provides a transistor combination structure of an integrated circuit memory and a forming method thereof. The effective area of the interface of the channel region and the word line is increased by forming a first notch in the substrate of the channel region, wherein the first notch is recessed relative to the first top surface of the channel region. Therefore, when the memory transistor formed by the active region and the word line is conducted, the formed conducting channel is correspondingly formed along the shape of the interface between the channel region and the word line in an inversion mode, so that the length and/or the width of the conducting channel can be increased, the short channel effect of the memory transistor can be effectively improved, and the conducting current of the memory transistor can be increased.

Description

Transistor combination structure of integrated circuit memory and method of forming the same

technical field

The present invention relates to the technical field of semiconductor integrated circuits, in particular to a transistor combination structure of an integrated circuit memory and a method for forming the same, and a semiconductor integrated circuit device.

Background technique

In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic devices, memory devices and analog circuits, among which memory devices occupy a considerable proportion of integrated circuit products. A memory usually includes a plurality of memory cells, the memory cells usually include an active region, and a memory transistor can be formed by using the active region, for example.

FIG. 1 is a schematic structural diagram of an active region of a memory cell. As shown in FIG. 1 , the active region 10 can be used to form a memory transistor, for example, so an active region 10S and a drain region 10D are defined on the active region 10 . And the portion between the source region 10S and the drain region 10D constitutes a channel region 10C. When the memory transistor is turned on, an inversion conductive channel can be formed in the channel region 10C, so that the source region 10S and the drain region 10D can flow current through the conductive channel.

With the increasing integration of semiconductor devices, it has become a trend to improve the integration density of memory. However, under the requirement of component size reduction, the size of the conductive channel of the storage transistor will also be reduced accordingly, resulting in a short channel effect of the storage transistor, and reducing the on-current and saturation current of the storage transistor.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a transistor combination structure of an integrated circuit memory, so as to solve the problems of the short channel effect of the memory transistor and the decrease of the on-current of the existing integrated circuit memory with the continuous reduction of the device size.

In order to solve the above technical problems, the present invention provides a transistor combination structure of an integrated circuit memory, including:

a substrate having a plurality of active regions therein; and,

A plurality of word lines are formed in the substrate, the word lines intersect with the corresponding active regions in their extending directions, and the active regions and part of the word lines together constitute an integrated circuit memory memory transistors;

A portion of the active region corresponding to the word line constitutes a channel region, the substrate corresponding to the channel region has a first top surface, and a substrate of the channel region is formed with a first top surface. At least one first notch recessed relative to the first top surface, the word line covers the first top surface of the channel region and fills the first notch.

Optionally, the active region extends along the active length direction, the bottom surface of the first notch and the first top surface form a first stepped structure, and the first stepped structure is perpendicular to the active region. The source regions are arranged step by step in the extension direction.

Optionally, the first notch extends along an extension direction of the active region, and has the same length dimension as the channel region in the extension direction.

Optionally, a plurality of word line trenches are formed in the substrate, the word lines are filled in the word line trenches, and the word line trenches pass through the corresponding active region in the extension direction thereof. The channel region; wherein, a portion of the word line trench corresponding to the channel region forms a gate trench, and a bottom surface of the gate trench corresponds to the first top surface of the channel region , the first notch is recessed relative to the bottom surface of the gate trench.

Optionally, the word line trench further has a plurality of connection trenches in the extension direction thereof, and the connection trenches are located between the adjacent gate trenches in the extension direction of the word line, so that the The adjacent gate trenches in the extension direction of the word line communicate with each other.

Optionally, in the word line trench, the bottom surface of the gate trench protrudes from the bottom surface of the connection trench and has protruding sidewalls, and the word line fills the gate trench and The connection trench covers the protruding sidewall to form the gate of the fin field effect transistor.

Optionally, the first notch is provided on a side of the gate trench close to the connection trench, and the bottom surface of the first notch protrudes from the bottom surface of the connection trench, so as to The bottom surface of the connection trench, the bottom surface of the first notch and the bottom surface of the gate trench form a multi-level stepped structure, and the multi-level stepped structure extends perpendicular to the active region Arranged step by step in the direction.

Optionally, the substrate further includes a trench isolation structure, and the trench isolation structure surrounds the periphery of the active region to isolate the adjacent active regions.

Optionally, parts of the active region located on both sides of the word line constitute source and drain regions of the storage transistor, and the substrate corresponding to the source and drain regions has a second top surface, and corresponds to the source and drain regions. At least one second notch recessed relative to the second top surface is formed in the substrate of the source and drain regions.

Optionally, the active region extends along the active length direction, the bottom surface of the second notch and the second top surface form a second stepped structure, and the second stepped structure is perpendicular to the active region. The source regions are arranged step by step in the extension direction.

Optionally, the second notch extends along the extension direction of the active region, and has the same length dimension as the corresponding source region or drain region in the extension direction of the active region.

Optionally, the first notch of the channel region and the second notch of the source-drain region both extend along the extension direction of the active region, and in the same active region, The height projection area of the first notch and the height projection area of the second notch are connected to each other on the same straight line.

Optionally, a plurality of the active regions all extend along the same direction, and are aligned in the extending direction to form a plurality of active rows, and two adjacent two of the plurality of the active rows The combination of active rows constitutes an active row group; wherein, in the two active rows of each of the active row groups, the active regions located on different rows are all on the side close to each other or on a side away from each other. The side is formed with the first notch and the second notch.

Optionally, a plurality of the active regions are aligned in the extending direction of the word line to form a plurality of active columns, and in two adjacent active columns, one of the active columns is The plurality of active regions all extend along the first direction, and the plurality of active regions in another active column all extend along the second direction, so that the two adjacent active columns are relative to a center line Mirror symmetry, and the two adjacent active regions located in different columns virtually intersect on the center line along the extending direction of the two active regions and have virtual connection points;

Wherein, a plurality of the active regions are connected in series based on the virtual connection points to form a plurality of active strings, and two adjacent active strings in the plurality of the active strings are combined to form an active string group (110B), in each of the two active strings of the active string group, the active regions located on different active strings are formed with the first gap and the second gap.

Another object of the present invention is to provide a method for forming a transistor combination structure of an integrated circuit memory, including:

A substrate is provided, the substrate has a plurality of active regions, and a channel region is defined in the active region, and the parts of the active region located on both sides of the channel region are used for forming source and drain regions of transistors in integrated circuit memories;

at least one first notch is formed in the substrate of the channel region, the substrate corresponding to the channel region has a first top surface, the first notch is opposite to the first top of the channel region The surface is recessed so that after a plurality of word lines are formed, the word lines intersect the corresponding active regions in their extending directions to cover the channel regions of the active regions, and the word lines correspond to the A portion of the channel region covers the first top surface of the channel region and fills the first gap.

Optionally, the method for forming the word line includes:

A word line mask layer is formed on the substrate, a plurality of first openings are opened in the word line mask layer, the extension direction of the first openings intersects with the extension direction of the active region, and exposing the channel region of the active region;

The substrate is etched using the word line mask layer as a mask to form a plurality of word line trenches in the substrate, and the word line trenches pass through the corresponding active regions in their extending direction. A channel region, and the part of the word line trench corresponding to the channel region constitutes a gate trench, and the first gap is also formed in the gate trench, and the first gap is opposite to the The bottom surface of the gate trench is recessed;

Filling word line material in the word line trenches to form the word lines.

Optionally, a portion of the word line trenches corresponding to the gate trenches adjacent in the extension direction of the word line constitutes a connection trench, and the bottom surface of the connection trench is lower than the gate Bottom surface of the pole groove.

Optionally, the forming step of the first gap includes:

forming a shielding mask layer on the substrate, a plurality of second openings are opened in the shielding mask layer, and the second openings expose part of the channel region; and,

The substrate is etched using the shielding mask layer as a mask to form a plurality of initial grooves in the substrate of the channel region, and the initial grooves are used to form the first notch.

Optionally, after forming the initial groove, forming the word line trench and forming the first notch at the same time, the forming step includes:

The word line mask layer is formed on the substrate, and the first opening of the word line mask layer exposes the channel region of the active region in its extending direction, and exposes the corresponding to the initial recess in the channel region; and,

etching the substrate by using the word line mask layer as a mask to form a plurality of the word line trenches in the substrate, wherein the initial grooves corresponding to the channel regions are etched The first notch is formed after etching.

Optionally, a plurality of the active regions all extend along the same direction, and are aligned in the extending direction to form a plurality of active rows, and two adjacent two of the plurality of the active rows The combination of active banks constitutes an active bank group.

Optionally, the second openings of the shielding mask layer extend along the extending direction of the active regions, and each of the second openings exposes the active elements in each of the active row groups. and the initial groove extends along the extension direction of the active region and has the same characteristics as the active region. length dimension.

Optionally, a plurality of the active regions are aligned in the extending direction of the word line to form a plurality of active columns, and in two adjacent active columns, one of the active columns is The plurality of active regions all extend along the first direction, and the plurality of active regions in another active column all extend along the second direction, so that the two adjacent active columns are relative to a center line Mirror symmetry, and two adjacent active regions located in different columns virtually intersect on the center line along the extending direction of the two active regions and have virtual connection points; wherein a plurality of the active regions The regions are connected in series based on the virtual connection points to form a plurality of waveform-extending active strings, and two adjacent active strings among the plurality of active strings are combined to form an active string group.

Optionally, the second openings of the shielding mask layer extend in a waveform corresponding to the active strings, and each of the second openings exposes the active regions in each of the active strings at two positions. The active strings are close to each other to expose a part of the channel region; and the initial groove extends along the active region in the corresponding active region, and is provided with the corresponding active region. same length dimension.

Optionally, the first opening of the word line mask layer exposes a part of the initial groove, and a part of the initial groove corresponding to the channel region is used to form the first gap, Parts of the initial groove located on both sides of the channel region are used to form a second gap, and the second gap corresponds to the source and drain regions.

Another object of the present invention is to provide a semiconductor integrated circuit device, comprising:

a substrate having a plurality of active regions therein; and,

a plurality of conductive lines formed in the substrate, the conductive lines intersect with the corresponding active regions in their extending directions, and the active regions and a part of the conductive lines together constitute a transistor;

Wherein, a portion of the active region corresponding to the conductive line constitutes a channel region, the substrate corresponding to the channel region has a first top surface, and a substrate of the channel region is formed with a first top surface. At least one gap recessed relative to the first top surface, the conductive line covers the first top surface of the channel region and fills the gap.

In the transistor combination structure of the integrated circuit provided by the present invention, by forming a first notch in the substrate of the active region corresponding to the channel region, the first notch is recessed relative to the first top surface of the channel region. That is, it is equivalent to that the channel region has an uneven surface, which not only has the first surface, but also has the bottom surface and sidewalls of the first notch recessed relative to the first surface, thereby greatly increasing the number of channel regions and characters. Effective area of line junctions. When the storage transistor composed of the active region and the word line is turned on, the conductive channel formed in the channel region is correspondingly formed along the interface of the channel region and the word line in an inversion shape, so that the The cross-sectional shape of the formed conductive channel in the predetermined direction is bent, which is beneficial to increase the length dimension and/or the width dimension of the conductive channel, thereby improving the short channel effect of the formed memory transistor, and increase the on-current of the memory transistor. Based on this, it is also beneficial to realize the reduction of the memory size of the integrated circuit memory.

Description of drawings

1 is a schematic structural diagram of an active region of a memory cell;

2 is a top view of the integrated circuit memory in Embodiment 1 of the present invention;

3 is a schematic structural diagram of the active region of the integrated circuit memory in Embodiment 1 of the present invention;

4a is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in FIG. 2 along a1-a1' direction;

Fig. 4b is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in Fig. 2 along a2-a2' direction;

Fig. 4c is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in Fig. 2 along the b1-b1' direction;

Fig. 4d is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in Fig. 2 along the b2-b2' direction;

FIG. 5 is a schematic structural diagram of the integrated circuit memory in Embodiment 1 of the present invention shown in FIG. 4a after word lines are omitted;

6 is a top view of the integrated circuit memory in Embodiment 2 of the present invention;

7a is a schematic cross-sectional view of the integrated circuit memory in the second embodiment of the present invention shown in FIG. 6 in the aa' direction;

7b is a schematic cross-sectional view of the integrated circuit memory in the second embodiment of the present invention shown in FIG. 6 in the bb' direction;

8 is a schematic flowchart of a method for forming an integrated circuit memory in Embodiment 3 of the present invention;

9a to 12a are top views of the method for forming an integrated circuit memory in the third embodiment of the present invention during the manufacturing process;

9b, 10b to 10c, 11b to 11c, and 12b are schematic cross-sectional views of the method for forming an integrated circuit memory in the third embodiment of the present invention during the manufacturing process.

Among them, the reference numerals are as follows:

10-active region; 10C-channel region;

10S-source region; 10D-drain region;

100-substrate;

110-active region; 110C-channel region;

110S-source region; 110D-drain region;

111C-conductive channel; 111SD-second gap;

110A-active row group; 110B-active string group;

110P - virtual connection point;

120 - trench isolation structure; 121 - isolation structure;

200 - word lines;

200G-gate part; 200L-connection part;

300-wordline trench;

300G-gate trench; 300L-connection trench;

310G - first notch;

400 - isolation layer;

500 - masking mask layer;

510-second opening; 511-initial groove;

600-word line mask layer; 610-first opening;

T11-the first top surface; T12-the bottom surface of the first notch;

T13 - the bottom surface of the connection groove;

T21 - the second top surface; T22 - the bottom surface of the second notch;

H1-first height position; H2-second height position;

H3-the third height position; H4-the fourth height position;

H5 - fifth height position.

Detailed ways

The integrated circuit memory, the method for forming the same, and the semiconductor device proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

Example 1

2 is a top view of the integrated circuit memory in the first embodiment of the present invention, FIG. 3 is a schematic structural diagram of the active area of the integrated circuit memory in the first embodiment of the present invention, and FIG. 4a is the first embodiment of the present invention shown in FIG. 2 . A schematic cross-sectional view of the memory in the a1-a1' direction shown in FIG. 4b is a cross-sectional schematic view of the memory in the a2-a2' direction in the first embodiment of the present invention shown in FIG. 2, and FIG. 4c is the implementation of the present invention shown in FIG. 2 FIG. 4d is a schematic cross-sectional view of the memory in the first embodiment of the present invention shown in FIG. 2 along the b2-b2' direction. With reference to FIGS. 2 , 3 , and FIGS. 4 a to 4 d , the transistor combination structure of the integrated circuit memory includes: a substrate 100 and a plurality of word lines 200 formed on the substrate 100 .

The substrate 100 has a plurality of active regions 110; and also has a trench isolation structure 120 in the substrate, and the trench isolation structure 120 surrounds the periphery of the active region 110 to isolate adjacent to the active region 110 .

2 , the active regions 110 extend along the active length direction. In this embodiment, all the active regions 110 extend along the first direction (Z1 direction), and a plurality of the active regions 110 extend along the first direction (Z1 direction). The source regions 110 are arranged in an array. In this embodiment, a plurality of the active regions 110 are aligned in the active length direction to form a plurality of active rows, wherein two adjacent active rows in the plurality of active rows can be arranged The rows are combined to form an active row group 110A.

2, 3 and 4a-4d, a plurality of word lines 200 are formed in the substrate 100 and extend obliquely with respect to the extending direction of the active region (in this embodiment, the The word line extends along the Y direction), the word line 200 intersects the corresponding active region 100 in the extension direction of the word line, and the active region 110 and part of the word line 200 together constitute an integrated circuit The transistor combination structure of the memory.

Referring to FIG. 3 in conjunction with FIG. 4 a , the portions of the active region 110 located on both sides of the word line 200 constitute the source region 110S and the drain region 110D of the memory transistor. And, a portion of the active region 110 corresponding to the word line 200 constitutes a channel region 110C, the substrate 100 has a first top surface T11 corresponding to the channel region 110C, and the channel region 110C has a first top surface T11. At least one first notch 310G recessed relative to the first top surface T11 is formed in the substrate 100 , that is, the bottom surface T12 of the first notch 310G is opposite to the first top surface T11 of the channel region 110C more sinking. The word line 200 covers the first top surface T11 and fills the first gap 310G.

It should be noted that, when the memory transistor formed by the word line 200 and the active region 110 is turned on, the substrate corresponding to the channel region 110C and close to the word line 200 can be inverted. A conductive channel 111C is formed. Wherein, since the first notch 310G is recessed on the first top surface T11 of the channel region 110C, the substrate surface corresponding to the channel region 110C appears as an uneven surface (that is, the surface corresponding to the channel region 110C is The cross-sectional shape of the substrate surface in a predetermined direction is a bent structure), and the word line 200 correspondingly covers the substrate surface of the channel region along the uneven surface of the channel region 110C. In this way, when the memory transistor is turned on, an inversion-formed conductive channel 111C is correspondingly formed in the substrate along the boundary morphology of the word line 200 and the substrate surface of the channel region 110C, Therefore, the cross-sectional shape of the formed conductive channel 111C in the predetermined direction can be a bent structure, which is beneficial to increase the size of the conductive channel 111C of the memory transistor in the predetermined direction.

For example, the cross-sectional shape of the conductive channel 111C in the direction from the source region to the drain region (ie, in the length direction of the conductive channel 111C) is bent, which is equivalent to increasing the conductive channel The length of 111C can improve the short channel effect of the memory transistor; or, the conductive channel 111C is in the direction perpendicular to the source region to the drain region (ie, in the width direction of the conductive channel 111C). ) is bent in cross-sectional shape, which is equivalent to increasing the width of the conductive channel 110C, thereby effectively increasing the on-current of the storage transistor, which is beneficial to improve the conduction performance of the storage transistor.

Continuing to refer to FIGS. 4 a to 4 d , in this embodiment, the cross-sectional shape of the conductive channel 111C in the width direction thereof is bent. 4a shows a schematic cross-sectional view of the conductive channel 111C in the width direction, so the conductive particles in the conductive channel 111C shown in FIG. 4a flow along the direction perpendicular to the paper surface; A schematic cross-sectional view of the conductive channel 111C in the length direction is shown, so the conductive particles in the conductive channel 111C shown in FIGS. 4d and 4c are along the source region 110S to the drain region 110D or the drain region 110D to the source region 110S. direction flow. Therefore, in this embodiment, by forming the first notch 310G, the total width dimension of the conductive channel 111C is increased in the width direction of the conductive channel 111C, so that the conductive channel formed by the inversion type can be further widened The width dimension of 111C is beneficial to improve the on-current of the storage transistor.

2, 3 and 4a, the bottom surface T12 and the first top surface T11 of the first notch 310G in this embodiment form a first stepped structure, and the first stepped structure is perpendicular to the The active regions are arranged step by step in the extending direction. Further, the first notch 310G can also extend along the extending direction of the active region, and has the same length dimension as the channel region 110C in the extending direction. That is, the first gap 310G extends along a direction parallel to the active region, and can extend to the entire channel region 110C in the extending direction, so the entire channel region 110C can form a stepped structure.

FIG. 5 is a schematic structural diagram of the integrated circuit memory in Embodiment 1 of the present invention shown in FIG. 4a after word lines are omitted. As shown in FIG. 4 a and FIG. 5 , the word lines 200 in this embodiment are buried in the substrate 100 for buried word lines.

Specifically, a plurality of word line trenches 300 are formed in the substrate 100 , and the word line 200 is filled in the word line trenches 300 . Therefore, the word line trenches 300 correspond to the width of the word line 200 . In addition, the word line trenches 300 pass through the corresponding active regions 110 in the extension direction of the word lines, so that the word lines 200 can communicate with the corresponding active regions 110 in the extension direction of the word lines. intersect.

And, the portion of the word line trench 300 corresponding to the active region 110 forms a gate trench 300G, and the portion of the word line 200 filling the gate trench 300G is used to form the gate portion 200G of the memory transistor . Wherein, the bottom surface of the gate trench 300G is the first top surface T11 of the channel region 110C, and the first gap 310G is the corresponding recess relative to the bottom surface of the gate trench. .

Specifically, the top surface of the substrate non-corresponding word line has a first height position H1, the bottom surface T11 of the gate trench 300G has a second height position H2, and the bottom surface of the first gap 310G T12 has a third height position H3, wherein the first height position H1 is higher than the second height position H2, and the second height position H2 is higher than the third height position H3.

4a and 5, the word line trench 300 further has a plurality of connection trenches 300L in the extension direction thereof, and the connection trenches 300L are located at the gate adjacent to the word line extension direction between the gate trenches 300G, so that the adjacent gate trenches 300G in the extension direction of the word line communicate with each other; the word line 200 fills the connection trench 300L to form a connection part 200L, and the connection part 200L and the gate portion 200G are connected to each other.

It can be considered that the connection trench 300L corresponds to the trench isolation structure 120 , and the connection portion 200L of the word line is correspondingly formed in the trench isolation structure 120 . Wherein, the isolation structure 121 is formed in the trench isolation structure 120 , and the connection portion 200L is formed on the isolation structure 121 .

5 , in the word line trench 300 of this embodiment, the bottom surface T11 of the gate trench 300G protrudes from the bottom surface T13 of the connection trench 300L and has protruding sidewalls, The word line 200 fills the gate trench 300G and the connection trench 300L and covers the protruding sidewall to form the gate of the fin field effect transistor. Alternatively, it can be understood that the bottom surface T13 of the connection structure 300L is recessed relative to the bottom surface T11 of the gate trench 300G, which is the top surface of the isolation structure 121 in the trench isolation structure 120 in this embodiment. lower than the first top surface T11 of the channel region 110C.

That is, the substrate corresponding to the channel region 110C protrudes from the isolation structures 121 on both sides thereof, so that the word line 200 can not only cover the top surface of the channel region 110C, but also cover the channel region Protruding sidewalls on both sides of 110C. When the formed fin field effect transistor is turned on, not only a conductive channel can be formed in the substrate where the channel region is close to the top surface, but also a conductive channel can be formed in the substrate where the gate region is close to the sidewall of the protrusion. A conductive channel is also formed, further increasing the width dimension of the conductive channel of the memory transistor.

Further, the first notch 310G is disposed on a side of the gate trench 300G close to the connection trench 300L, and the bottom surface T12 of the first notch 310G is opposite to the connection trench 300L. The bottom surface T13 protrudes so that the bottom surface T13 of the connection trench, the bottom surface T12 of the first notch and the bottom surface T11 of the gate trench form a multi-level stepped structure, and the multi-level stepped structure is They are arranged step by step perpendicular to the extending direction of the active region (perpendicular to the Z1 direction).

In this embodiment, the bottom surface T13 of the connecting trench 300L has a fourth height position H4, the fourth height position H4 of the bottom surface T13 of the connecting trench 300L, and the bottom surface T12 of the first gap 310G The third height position H3, the second height position H2 of the bottom surface T11 of the gate trench 300G, and the first height position H1 of the top surface of the substrate non-corresponding word line, present multiple levels in sequence from low to high Step structure.

It should be noted that, since the first notch 310G and the connecting groove 300L communicate with each other, the side wall of the first notch 310G near the connecting structure 300L is removed, so that the bottom of the first notch 310G is removed. The surface T12 conforms to the sidewalls of the connecting trenches 300L to form the multi-step structure.

Correspondingly, in the conductive channel 111C formed in the substrate adjacent to the gate portion 300G along the surface topography of the substrate when the memory transistor is turned on, the conductive channel 111C is in the width direction of the conductive channel 111C. The cross-sectional shape of the upper part is correspondingly presented as a multi-level stepped structure.

3 and 4b, the parts of the active region 110 located on both sides of the word line 200 respectively constitute the source region 110S and the drain region 110D of the storage transistor, and the substrate corresponds to the source region 110S and the drain region 110D. The source region 110S and the drain region 110D have a second top surface T21; and at least one second notch recessed relative to the second top surface T21 is formed in the substrate corresponding to the source region 110S and the drain region 110D 111SD.

In this embodiment, the substrate surfaces corresponding to the source region 110S and the drain region 110D also appear as uneven surfaces, which correspondingly increases the surface areas of the source region 110S and the drain region 110D. Therefore, on the basis of not changing the projection size of the source region 110S and the drain region 110D in the height direction, the source region 110S and the drain region 110D and other elements subsequently formed above the source region 110S and the drain region 110D are effectively increased The contact area between the source regions 110S and the drain region 110D can be reduced accordingly; alternatively, the source region 110S and the drain region 110S can also be reduced under the condition that the surface areas of the source region 110S and the drain region 110D remain unchanged. The projected size of the region 110D in the height direction (that is, reducing the size that the source region 110S and the drain region 110D need to occupy on the substrate), so that the overall size of the formed memory transistor can be further reduced, It is beneficial to realize high-density arrangement of integrated circuit memory.

2 and 4b, in the source region 110S and the drain region 110D, the bottom surface T22 and the second top surface T21 of the second notch 111SD may further form a second step structure, And the second step structures are arranged step by step in a direction perpendicular to the extending direction of the active region. Further, the second notch 111SD can also extend along the extension direction (Z1 direction) of the active region, and has the same length as the corresponding source region or drain region in the extension direction of the active region size. That is, in this embodiment, the arrangement of the second notch 111SD in the source region 110S and the drain region 110D is similar to the arrangement of the first notch 310G in the channel region 110C, and both are located along the active The extension direction of the zone extends.

In an optional solution, in the same active region, the height projection of the first notch 310G of the channel region 110C and the height projection of the second notch 111SD of the source region 110S/drain region 110D The ends of the zones are connected to each other. That is, in this embodiment, the first notch 310G is deeper than the second notch 111SD, but in the height projection area, the first notch 310G and the second notch 111SD can extend on the same straight line superior.

Specifically, the height positions of the second top surfaces T21 of the source regions 110S and the drain regions 110D correspond to the first height positions H1 of the top surfaces of the non-corresponding word lines of the substrate as described above, that is, the second The top surface T21 has a first height position H1, and the bottom surface T22 of the second notch has a fifth height position H5, which is lower than the first height position H1. In this embodiment, the height difference between the first height position H1 and the fifth height position H5 corresponding to the source region 110S and the drain region 110D corresponds to the second height position H2 and the third height position H2 of the gate trench 300G. The height differences between the height positions H3 are equal or similar.

Continuing to refer to FIG. 2 , in this embodiment, a plurality of the active regions 110 are aligned in the extending direction (the Z1 direction) to form a plurality of active rows. The two adjacent active rows in the middle are combined to form an active row group 110A. Wherein, in each of the two active rows of the active row group 110A, the active regions 110 located on different rows are formed with the first notches on the side close to each other or the side away from each other 310G and the second notch 111SD. That is, the first notches 310G located in different rows are close to or away from each other, and the second notches 111SD located in different rows are close to or away from each other.

Since in the active row group 110A, the two active rows are aligned along the extending direction thereof (that is, the arranging direction is parallel to the extending direction of the active region), the first notch 310G and the second The notches 111SD are arranged at the same linear position of each active row in the arrangement direction thereof. In this way, when preparing the first notch and the second notch, it is beneficial to reduce the difficulty of preparing the first notch and the second notch.

In addition, the transistor assembly structure of the integrated circuit memory further includes an isolation layer 400 , the isolation layer 400 is formed on the substrate 100 and fills the word line trench 300 located above the word line 200 part to cover the word line 200 .

Embodiment 2

The difference from the first embodiment is that, in the integrated circuit memory in this embodiment, some of the active regions of the plurality of active regions extend along the first direction, and another part of the active regions extend along the second direction.

6 is a top view of the integrated circuit memory in the second embodiment of the present invention, FIG. 7a is a schematic cross-sectional view of the integrated circuit memory in the aa' direction in the second embodiment of the present invention shown in FIG. 6 , and FIG. 7b is the schematic diagram shown in FIG. 6 The cross-sectional schematic diagram of the integrated circuit memory in the second embodiment of the present invention in the bb' direction.

6 and 7a-7b, in this embodiment, a plurality of the active regions 110 are aligned along the extending direction of the word line 200 to form a plurality of active columns, and adjacent to each other. In the two active columns, the plurality of active regions 110 in one active column extend along the first direction (Z1 direction), and the plurality of active regions 110 in the other active column extend along the first direction (Z1 direction). It extends in two directions (Z2 direction), so that the two adjacent active columns are mirror-symmetrical with respect to a center line. In addition, two adjacent active regions 110 located in different columns virtually intersect on the center line along the extending direction of the two active regions and have a virtual connection point 110P.

Further, a plurality of the active regions 110 are connected in series based on the virtual connection point 110P to form a plurality of active strings, and the active strings are correspondingly extended in a waveform structure. In this embodiment, the active strings extend in a waveform perpendicular to the extending direction of the word lines, that is, the active strings extend in the X direction. Wherein, two adjacent active strings among the plurality of active strings are combined to form an active string group 110B. In an optional solution, in each of the two active strings of the active string group 110B, the active regions 110 located on different active strings are formed on the side close to each other or the side away from each other. The first notch 310G and the second notch 111SD.

Continuing to refer to FIG. 6 and FIG. 7b , the substrate 100 has a plurality of trench isolation structures 120 , and a plurality of isolation structures 121 are formed in the trench isolation structures 120 for making adjacent active The zones 110 are isolated from each other. In this embodiment, since a plurality of the active regions 110 are aligned in the column direction, and the trench isolation structures 120 are correspondingly provided between adjacent active columns, they are formed in adjacent active columns. The isolation structures 121 between the active columns correspondingly extend along the extending direction of the word lines 200 .

Embodiment 3

8 is a schematic flowchart of the method for forming an integrated circuit memory in Embodiment 3 of the present invention, and FIGS. 9a to 12a are top views of the method for forming an integrated circuit memory in Embodiment 3 of the present invention during the preparation process; 10b to 10c , 11b to 11c and 12b are schematic cross-sectional views of the method for forming an integrated circuit memory according to Embodiment 3 of the present invention during the manufacturing process. Each step of the method for forming an integrated circuit memory in this embodiment will be described in detail below with reference to the accompanying drawings.

In step S100, referring specifically to FIG. 9a and FIG. 9b, a substrate 100 is provided, the substrate 100 has a plurality of active regions 110, and a channel region 110C is defined in the active region 110, Parts of the active region 110 located on both sides of the channel region 110C are used to form the source and drain regions of the transistor combination structure of the integrated circuit memory.

In this embodiment, a plurality of the active regions 110 all extend along the same direction (Z1 direction), and are aligned in the extending direction to form a plurality of active rows, two of the plurality of active rows Two adjacent active rows are combined to form an active row group 110A.

Step S200, referring specifically to FIGS. 10a-12a, 10b-10c, 11b-11c and 12b, forming at least one first gap 310G in the substrate of the channel region 110C, corresponding to the channel region The substrate of 110C has a first top surface T11, and the first gap 310G is recessed with respect to the first top surface T11 of the channel region 110C, so that after a plurality of word lines 200 are formed, the word lines 200 It intersects with the corresponding active region 110 in its extending direction, and the part of the word line 200 corresponding to the active region covers the first top surface T11 of the channel region 110C and fills the first top surface T11 of the channel region 110C. A notch 310G.

Since a first notch 310G recessed relative to the first top surface T11 is formed in a part of the channel region 110C, another part of the channel region 110C still has the first top surface T11, so that the channel region 110C With the uneven surface, when the word line 200 is formed to constitute a memory transistor, the size of the conductive channel of the memory transistor can be increased.

In this embodiment, the formed word lines 200 are buried word lines, that is, the word lines 200 are formed in the substrate. 11a and 12a, the method for forming the word line 200 includes: first, forming a word line trench 300 in the substrate 100, and the word line trench 300 passes through the active region. The channel region 110C and the portion of the word line trench 300 corresponding to the channel region constitute a gate trench 300G, and the first gap 310G is further formed in the gate trench 300G; Next, word line material is filled in the word line trench 300 to form the word line 200 , and the word line 200 fills the gate trench 300G and further fills the first gap 310G.

Further, the first notch 310G and the word line trench 300 are formed in the same step, that is, the word line trench 300 is formed on the bottom of the word line trench 300 while the word line trench 300 is formed. The first notch is 310G. The method for forming the first notch 310G, the word line trench 300 and the word line 200 in this embodiment will be described in detail below with reference to the accompanying drawings.

The first step, specifically referring to FIG. 10a and FIG. 10b, is to form a shadow mask layer 500 on the substrate 100. The shadow mask layer 500 is provided with a plurality of second openings 510. The second openings 510 exposes part of the channel region 110C, and correspondingly covers another part of the channel region 110C. In this step, the top surface of the substrate 100 has a first height position H1.

As shown in FIG. 10a, a plurality of active regions 110 in this embodiment constitute a plurality of active rows, the plurality of active rows are aligned in the extending direction of the active regions, and further combined to constitute a plurality of active rows Group 110A. At this time, the second openings 510 of the shielding mask layer 500 can be extended along the extending direction of the active region, and each of the second openings 510 can expose each of the active rows The active regions 110 in the group 110A are in portions where the two active rows are close to each other to expose part of the channel regions 110C. That is, part of the channel regions 110C of the plurality of active regions 110 can be exposed at the same time by one opening, so that the opening size of the second opening 510 can be increased, which is beneficial to improve the corresponding the photolithography process window of the second opening.

In the second step, referring to FIG. 10a and FIG. 10c in particular, the substrate 100 is etched using the masking mask layer 500 as a mask to form a lining of a plurality of initial grooves 511 in the channel region 110C Bottom 100. Then, the cover mask layer 500 can be removed. In this step, the bottom surface of the formed initial groove 511 may have a fifth height position H5 lower than the first height position H1.

In this embodiment, the second opening 510 exposes the active region 110 along the extending direction of the active region, so that the formed initial groove 511 correspondingly extends along the active region The initial groove 511 has the same length dimension as the active region 110, that is, the initial groove 511 extends over the entire active region 110 in the extending direction of the active region middle.

In the third step, referring to FIG. 11a and FIG. 11b in particular, a word line mask layer 600 is formed on the substrate 100. A plurality of first openings 610 are opened in the word line mask layer 600. The extending direction of the first opening 610 intersects with the extending direction of the active region, and exposes the channel region 110C of the active region, and correspondingly exposes the initial groove 511 in the extending direction thereof The portion located in the channel region 110C.

In this embodiment, the initial groove 511 is formed in the channel region 110C, and further extends to the active region 110 at the periphery of the channel region. Based on this, the first opening 610 of the word line mask layer 600 only exposes a part of the initial groove 511 , wherein a part of the initial groove 511 corresponding to the channel region is used to form all the initial grooves 511 . For the first notch, the portions of the initial groove 511 located on both sides of the channel region are used to form a second notch 111SD, and the second notch 111SD corresponds to the source region 110S and the drain region 110D.

The fourth step, specifically referring to FIGS. 11 a and 11 c , etching the substrate 100 using the word line mask layer 600 as a mask to form a plurality of word line trenches 300 in the substrate 100 , the word line trench 300 passes through the channel region 110C of the corresponding active region in its extending direction, and the portion of the word line trench 300 corresponding to the channel region 110C constitutes a gate trench 300G. And, the initial groove 511 corresponding to the channel region forms the first notch 310G after etching, and the first notch 310G is formed in the gate trench 300G, that is, the gate A portion of the trench 300G corresponding to the initial groove 511 is recessed relative to the bottom surface T11 of the gate trench to form the first gap 310G. In this way, the first gap 310G can be formed in the gate trench 300G while the gate trench 300G is formed.

Wherein, the bottom surface T11 of the gate channel of the word line trench 300 has a second height position H2, and the bottom surface T12 of the first notch has a third height position H3, and the third height position H3 is lower than the second height position H2.

Further, the word line trench 300 further includes a connection trench 300L, and the connection structure 300L is located between the adjacent gate trenches 300G in the extension direction of the word line, and is used for connection in the extension direction of the word line on the adjacent gate trenches 300G.

In a preferred solution, the bottom surface T13 of the connection trench 300L is more submerged than the bottom surface T11 of the gate trench 300G, that is, the bottom surface T11 of the gate trench is relative to the connection trench. The bottom surface T13 protrudes and has protruding side walls. The bottom surface T13 of the connection channel has a fourth height position H4, and the fourth height position H4 is lower than the second height position H2 of the bottom surface of the gate trench.

Optionally, the first notch 310G is close to the connection groove 300L and communicates with the connection groove 300L, and the bottom surface T13 of the connection groove is deeper than the bottom surface T12 of the first notch. . Therefore, the bottom surface T11 of the gate trench, the bottom surface T12 of the first notch 310G and the bottom surface T13 of the connection trench may form a multi-level stepped structure.

The fifth step, specifically referring to FIGS. 12 a and 12 b , fills the word line trenches with a word line material to form the word line 200 . The word line 200 fills the gate trench, the first gap and the connection trench.

The portion of the word line 200 filled with the gate trench and the first gap constitutes a gate portion 200G, and the portion of the word line 200 filled with the connection trench constitutes a connection portion 200L. And, the portions of the active region 110 located on both sides of the word line 200 are used to form the source region 110S and the drain region 110D of the storage transistor.

So far, a plurality of buried word lines 200 are formed in the substrate 100, and the portion of the word lines 200 corresponding to the channel region 110C not only fills the gate trench but also further fills the first gap.

Further, after forming the word line 200, the method further includes:

Step S300 , as shown in FIG. 12 b , an isolation layer 400 is formed on the substrate 100 to cover the word lines 200 .

Further, the top of the word line 200 is lower than the top of the word line trench. At this time, the isolation layer 400 further fills the part of the word line trench above the word line, so as to improve the resistance to the word line. Isolation effect of word lines.

It should be noted that, in this embodiment, a plurality of active regions extending along the same direction and being aligned and arranged are taken as an example to explain the formation method of the integrated circuit memory. However, in other embodiments, when the multiple active regions are arranged in the manner shown in FIG. 6 , the shape of the second opening of the mask layer can be adjusted accordingly.

Specifically, in other embodiments, a plurality of the active regions are aligned in the extending direction of the word lines to form a plurality of active columns, and in two adjacent active columns, wherein The plurality of active regions in one active column all extend along the first direction, and the plurality of active regions in the other active column all extend along the second direction, so that the adjacent two active regions The columns are mirror-symmetrical with respect to a center line, and two adjacent active regions located in different columns virtually intersect on the center line along the extending direction of the two active regions and have virtual connection points. Wherein, a plurality of the active regions are connected in series based on the virtual connection points to form a plurality of waveform-extending active strings, and two adjacent active strings in the plurality of the active strings are combined to form an active string with source string group.

Based on this, when the initial grooves are formed, the second openings of the mask layer can be extended to correspond to the active strings, and each of the second openings exposes the holes in each of the active strings. The active region is in a portion where the two active strings are close to each other to expose part of the channel region. At this time, the second openings also extend in a waveform to correspond to the shape of the active strings, and the formed initial grooves can also extend along the active regions in the corresponding active regions, and have the same length dimension as the corresponding active region.

In addition, in the field of semiconductor integrated circuits, the transistor combination structure of the integrated circuit memory described above can also be modified accordingly, so as to be suitable for other semiconductor integrated circuit devices. Specifically, the semiconductor integrated circuit device includes:

a substrate having a plurality of active regions therein; and,

a plurality of conductive lines formed in the substrate, the conductive lines intersect with the corresponding active regions in their extending directions, and the active regions and a part of the conductive lines together constitute a transistor;

Wherein, a portion of the active region corresponding to the conductive line constitutes a channel region, the substrate corresponding to the channel region has a first top surface, and a substrate of the channel region is formed with a first top surface. At least one gap recessed relative to the first top surface, the conductive line covers the first top surface of the channel region and fills the gap.

In the above semiconductor integrated circuit device, the length and/or width of the conduction channel of the transistor of the semiconductor integrated circuit device can also be effectively increased, thereby effectively improving the conduction performance of the transistor and the short-channel effect of the transistor. In other words, the semiconductor integrated circuit device can effectively reduce the short-channel effect of the transistor while reducing the size of the device, and prevent the on-current of the transistor from being too small, so as to ensure the on-performance of the transistor.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (25)

1. A transistor combination structure of an integrated circuit memory, characterized in that, comprising: a substrate having a plurality of active regions therein; and, A plurality of word lines are formed in the substrate, the word lines intersect with the corresponding active regions in the extension direction of the word lines, and the active regions are formed by the active regions and the word lines in the active region The internal parts together constitute the storage transistor of the integrated circuit memory; Wherein, a groove portion corresponding to the word line in the active region constitutes a channel region, the substrate corresponding to the channel region has a first top surface, and the substrate of the channel region has a first top surface. At least one first notch recessed relative to the first top surface is formed, and the word line covers the first top surface of the channel region and fills the first notch. 2 . The transistor combination structure of an integrated circuit memory as claimed in claim 1 , wherein the active region extends along the active length direction, and the bottom surface of the first notch and the first top surface constitute the structure. 3 . A first step structure, the first step structure is arranged step by step in a direction perpendicular to the extension direction of the active region. 3 . The transistor combination structure of an integrated circuit memory according to claim 2 , wherein the first notch extends along an extension direction of the active region, and is connected to the channel in the extension direction. 4 . The zones have the same length dimension. 4. The transistor combination structure of an integrated circuit memory according to claim 1, wherein a plurality of word line trenches are formed in the substrate, the word lines are filled in the word line trenches, and the word line trenches pass through the channel regions of the corresponding active regions in a word line extending direction; The part of the word line trench corresponding to the channel region forms a gate trench, the bottom surface of the gate trench corresponds to the first top surface of the channel region, and the first gap Recessed relative to the bottom surface of the gate trench. 5 . The transistor combination structure of an integrated circuit memory according to claim 4 , wherein the word line trench further has a plurality of connection trenches in the extension direction of the word line, and the connection trench is located on the word line. 6 . between the adjacent gate trenches in the extension direction, so that the adjacent gate trenches in the extension direction of the word line communicate with each other. 6 . The transistor combination structure of an integrated circuit memory as claimed in claim 5 , wherein, in the word line trenches, the bottom surface of the gate trench protrudes from the bottom surface of the connection trench and Having protruding sidewalls, the word line fills the gate trenches and the connection trenches and covers the protruding sidewalls to form the gate of the fin field effect transistor. 7 . The transistor combination structure of an integrated circuit memory according to claim 6 , wherein the first notch is disposed on a side of the gate trench close to the connection trench, and the first The bottom surface of the notch protrudes relative to the bottom surface of the connection trench, so that the bottom surface of the connection trench, the bottom surface of the first notch and the bottom surface of the gate trench form a multi-level stepped structure , the multi-level stepped structures are arranged step by step in a direction perpendicular to the extending direction of the active region. 8. The transistor combination structure of an integrated circuit memory according to claim 1, wherein a trench isolation structure is further formed in the substrate, and the trench isolation structure surrounds the periphery of the active region, to isolate the adjacent active regions. 9 . The transistor combination structure of an integrated circuit memory according to claim 1 , wherein the parts of the active region located on both sides of the word line constitute source and drain regions of the memory transistor. 10 . , the substrate corresponding to the source and drain regions has a second top surface, and each of the substrates corresponding to the source and drain regions is formed with at least one second notch recessed relative to the second top surface. 10. The transistor combination structure of an integrated circuit memory according to claim 9, wherein the active region extends along the active length direction, and the bottom surface of the second notch and the second top surface constitute The second step structure is arranged step by step in a direction perpendicular to the extending direction of the active region. 11 . The transistor combination structure of an integrated circuit memory according to claim 10 , wherein the second notch extends along the extending direction of the active region, and is aligned with the extending direction of the active region. 12 . Corresponding source or drain regions have the same length dimension. 12 . The transistor combination structure of an integrated circuit memory according to claim 9 , wherein the first notch of the channel region and the second notch of the source-drain region are both along an active length. 13 . direction, and in the same active area, the height projection area of the first notch and the height projection area of the second notch are connected to each other on the same straight line. 13. The transistor combination structure of an integrated circuit memory as claimed in claim 9, wherein a plurality of the active regions extend along the same direction and are aligned in the active length direction to form a plurality of active regions source row, two adjacent active rows in the plurality of active rows are combined to form an active row group; wherein, in the two active rows of each active row group, the two active rows located in different The active regions on the row are all formed with the first notch and the second notch on a side close to each other or a side away from each other. 14 . The transistor combination structure of an integrated circuit memory according to claim 9 , wherein a plurality of the active regions are aligned and arranged in the extension direction of the word line to form a plurality of active columns, and adjacent to each other. 15 . In the two active columns, the plurality of active regions in one active column all extend along the first direction, and the plurality of active regions in the other active column all extend along the second direction, so that all the active regions extend along the second direction. The two adjacent active columns are mirror-symmetrical with respect to a center line, and two adjacent active regions located in different columns virtually intersect on the center line along the extension direction of the two active regions while having virtual connection points; Wherein, a plurality of the active regions are connected in series based on the virtual connection points to form a plurality of active strings, and two adjacent active strings in the plurality of the active strings are combined to form an active string group , in each of the two active strings of the active string group, the active regions located on different active strings are formed with the first notch and the the second gap. 15. A method for forming a transistor combination structure of an integrated circuit memory, comprising: A substrate is provided, the substrate has a plurality of active regions, and a channel region is defined in the active region, and the parts of the active region located on both sides of the channel region are used to form an integrated a source-drain region of a transistor combination structure of a circuit memory; and, forming at least one first notch in the substrate of the channel region, wherein the substrate corresponding to the channel region has a first top surface, the first notch is opposite to the first notch of the channel region The top surface is recessed so that after a plurality of word lines are formed, the word lines intersect the corresponding active regions in the extension direction of the word lines to cover the channel regions of the active regions, and the word lines correspond to A portion of the channel region covers the first top surface of the channel region and fills the first gap. 16. The method of claim 15, wherein the method of forming the word lines comprises: A word line mask layer is formed on the substrate, a plurality of first openings are opened in the word line mask layer, the extension direction of the first openings intersects with the extension direction of the active region, and is exposed out the channel region of the active region; The substrate is etched using the word line mask layer as a mask to form a plurality of word line trenches in the substrate, and the word line trenches pass through the corresponding active regions in their extending direction. A channel region, and the part of the word line trench corresponding to the channel region constitutes a gate trench, and the first gap is also formed in the gate trench, and the first gap is opposite to the the bottom surface of the gate trench is recessed; and, Filling word line material in the word line trenches to form the word lines. 17 . The method of claim 16 , wherein a portion of the word line trenches corresponding to the gate trenches adjacent to each other in the extension direction of the word line forms a connection trench, 17 . The bottom surface of the connection trench is lower than the bottom surface of the gate trench. 18. The method of claim 16, wherein the step of forming the first notch comprises: forming a shadow mask layer on the substrate, a plurality of second openings are opened in the shadow mask layer, the second openings expose part of the channel region; and, The substrate is etched using the shielding mask layer as a mask to form a plurality of initial grooves in the substrate of the channel region, and the initial grooves are used to form the first notch. 19. The method of claim 18, wherein after the initial groove is formed, the word line trench is formed and the first notch is formed at the same time, and the forming step comprises: The word line mask layer is formed on the substrate, and the first opening of the word line mask layer exposes the channel region of the active region in the extension direction of the word line, and exposes corresponding to the initial groove in the channel region; and, etching the substrate by using the word line mask layer as a mask to form a plurality of the word line trenches in the substrate, wherein the initial grooves corresponding to the channel regions are etched The first notch is formed after etching. 20. The forming method of claim 19, wherein a plurality of the active regions all extend along the same direction, and are aligned in the active extending direction to form a plurality of active rows, a plurality of Two adjacent active rows in the active row are combined to form an active row group. 21. The forming method of claim 20, wherein the second openings of the shielding mask layer extend along an extending direction of the active region, and each of the second openings exposes The active regions in each of the active row groups are in a portion where the two active rows are close to each other to expose part of the channel regions; and, the initial grooves extend along the active regions direction and have the same length dimension as the active region. 22. The method of claim 19, wherein a plurality of the active regions are aligned in the extending direction of the word lines to form a plurality of active columns, and two adjacent active regions are arranged in alignment in the extending direction of the word lines. In the active columns, the plurality of active regions in one active column all extend along the first direction, and the plurality of active regions in the other active column all extend along the second direction, so that the phase Two adjacent active columns are mirror-symmetrical with respect to a center line, and two adjacent active regions located in different columns virtually intersect on the center line along the extending direction of the two active regions. A virtual connection point; wherein a plurality of the active regions are connected in series based on the virtual connection point to form a plurality of active strings extending in a waveform, and two active strings adjacent to each other in the plurality of the active strings The combination constitutes an active string group. 23. The method of claim 22, wherein the second openings of the shielding mask layer extend in a waveform corresponding to the active string, and each of the second openings exposes each of the second openings. The active regions in the active string group are in a portion where the two active strings are close to each other, so as to expose part of the channel region; and the initial groove is in the corresponding active region along the active region. The active regions extend and have the same length dimension as the corresponding active regions. 24. The method of claim 21 or 23, wherein the first opening of the word line mask layer exposes a part of the initial groove, and the initial groove corresponds to the groove The part in the channel region is used to form the first gap, and the part of the initial groove on both sides of the channel region is used to form a second gap, and the second gap corresponds to the source and drain regions middle. 25. A semiconductor integrated circuit device, comprising: a substrate having a plurality of active regions therein; and, A plurality of conductive lines are formed in the substrate, the conductive lines intersect with the corresponding active regions in the extending direction of the conductive lines, and are formed by the active regions and the conductive lines in the active region. The parts in the area together constitute a transistor; Wherein, a portion of the active region corresponding to the conductive line constitutes a channel region, the substrate corresponding to the channel region has a top surface, and the substrate corresponding to the channel region is formed with relatively all the At least one notch is recessed on the top surface, and the conductive line covers the top surface of the channel region and fills the notch.

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