CN208655643U

CN208655643U - The transistor combination structure and semiconductor device of integrated circuit memory

Info

Publication number: CN208655643U
Application number: CN201821450553.7U
Authority: CN
Inventors: 赵亮
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-09-05
Filing date: 2018-09-05
Publication date: 2019-03-26
Anticipated expiration: 2028-09-05

Abstract

The utility model provides the transistor combination structure and semiconductor device of a kind of integrated circuit memory.By forming the first notch being recessed relative to the first top surface of channel region in the substrate of channel region, to increase the effective area of channel region and wordline boundary.Therefore, in the memory transistor conducting being made of active area and wordline, it can make to be formed by conducting channel and be formed accordingly along the interface pattern transoid of channel region and wordline, so as to increase the length and/or width of conducting channel, and then the short-channel effect of memory transistor can be effectively improved and the conducting electric current of memory transistor can be improved.

Description

The transistor combination structure and semiconductor device of integrated circuit memory

Technical field

The utility model relates to semiconductor integrated circuit technology field, in particular to a kind of crystal of integrated circuit memory Pipe composite structure and a kind of semiconductor device.

Background technique

In current semiconductor industry, IC products can be divided mainly into three categories type: logical device, memory device And analog circuit, wherein memory device occupies sizable ratio in IC products.It is generally included in memory more A storage unit, the storage unit generally includes an active area, and for example constitutes memory transistor using the active area.

Fig. 1 is a kind of structural schematic diagram of the active area of storage unit, as shown in Figure 1, active area 10 for example can be used for structure At memory transistor, therefore active area 10S and drain region 10D are defined on the active area 10, and in the source region 10S and described Part constituting channel area 10C between the 10D of drain region.In memory transistor conducting, transoid one can be formed in channel region 10C Conducting channel, so that the source region 10S and the drain region 10D be made to realize current flowing by the conducting channel.

As the integrated level of semiconductor devices is continuously increased, the integration density for promoting memory has become a kind of trend. However, the size of the conducting channel of memory transistor can also reduce therewith, and then cause to deposit under the requirement of component size reduction The short-channel effect of transistor is stored up, and the conducting electric current and saturation current decline of memory transistor can be made.

Utility model content

It is existing to solve the purpose of this utility model is to provide a kind of transistor combination structure of integrated circuit memory Integrated circuit memory with the continuous reduction of device size, be easy to appear short-channel effect and the conducting of memory transistor The problem of electric current declines.

In order to solve the above technical problems, the utility model provides a kind of transistor combination structure of integrated circuit memory, Include:

One substrate has multiple active areas in the substrate；And

A plurality of wordline, formed in the substrate, the wordline in their extension direction with the corresponding active area phase It hands over, and collectively forms the memory transistor of integrated circuit memory by the active area and the part wordline；

Wherein, the part constituting channel area of the wordline, the lining of the corresponding channel region are corresponded in the active area Bottom has the first top surface, and at least the one of the relatively described first top surface recess is formed in the substrate of the channel region A first notch, the wordline cover first top surface of the channel region and fill first notch.

Optionally, the active area extends along active length direction, the bottom surface of first notch and described first Top surface constitutes first step structure, and the first step structure is arranged stepwise on the extending direction perpendicular to the active area Cloth.

Optionally, first notch along the active area extending direction extend, and on the extending direction with The channel region has identical length dimension.

Optionally, multiple wordline grooves are formed in the substrate, the wordline is filled in the wordline groove, and The wordline groove passes through the channel region of corresponding active area in their extension direction；Wherein, the wordline groove corresponds to institute The part for stating channel region constitutes gate trench, and the bottom surface of the gate trench corresponds to first top table of the channel region Face, first notch are recessed relative to the bottom surface of the gate trench.

Optionally, the wordline groove in their extension direction also have multiple connection grooves, the connection ditch slot position in On wordline extending direction between the adjacent gate trench, so that the gate trench adjacent on wordline extending direction It is interconnected.

Optionally, in the wordline groove, bottom surface of the bottom surface of the gate trench relative to the connection groove Protrusion side wall is protruded and has, the wordline fills the gate trench and the connection groove and covers the protrusion side wall, To constitute the grid of fin formula field effect transistor.

Optionally, the gate trench is arranged on the side of the connection groove in first notch, and institute The bottom surface for stating the first notch is prominent relative to the bottom surface of the connection groove, so that the bottom surface of the connection groove, institute The bottom surface of the bottom surface and the gate trench of stating the first notch constitutes multi-stage stairs structure, and the multi-stage stairs structure is being hung down Directly in arranging stepwise on the extending direction of the active area.

Optionally, also there is groove isolation construction, the groove isolation construction is centered around the active area in the substrate Periphery, the adjacent active area is isolated.

Optionally, the part in the active area positioned at the wordline two sides constitutes the source-drain area of the memory transistor, The substrate of the corresponding source-drain area has the second top surface, and is each formed in the substrate of the corresponding source-drain area opposite At least one second notch of the second top surface recess.

Optionally, the active area extends along active length direction, the bottom surface of second notch and described second Top surface constitutes second step structure, and the second step structure is arranged stepwise on the extending direction perpendicular to the active area Cloth.

Optionally, second notch extends along the extending direction of the active area, and in the extension of the active area Has identical length dimension with corresponding source region or drain region on direction.

Optionally, first notch of the channel region and second notch of the source-drain area have each along described The extending direction of source region extends, and in the same active area, the height projection area of first notch and described second The height projection area of notch is connected with each other on the same line.

Optionally, multiple active areas extend each along same direction, and alignment is arranged with structure in their extension direction At multiple active rows, in multiple active rows, adjacent two-by-two two active rows, which are combined, constitutes active row's group；Wherein, every In two active rows of one active row's group, the active area on different rows deviates from side close to each other or mutually Side be formed with first notch and second notch.

Optionally, multiple active areas are aligned on the extending direction of the wordline arranges to constitute multiple active column, And in two adjacent active column, wherein multiple active areas in an active column extend each along first direction, Ling Yiyou Multiple active areas in the column of source extend each along second direction, so that two adjacent active column are relative to a center line mirror As symmetrical, and between adjacent two active areas in different lines along the extending direction of two active areas at the center Virtually intersect on line and there is virtual link point；

Wherein, multiple active areas be based on the virtual link point contact with constitute it is multiple have a subject string, multiple described have Adjacent two-by-two two have subject string combination composition one to have subject string group (110B) in subject string, have in each two for having subject string group In subject string, described the is formed with positioned at the sides that difference has the active area on subject string to deviate from side close to each other or mutually One notch and second notch.

The further object of the utility model is to provide a kind of semiconductor device, comprising:

One substrate has multiple active areas in the substrate；And

A plurality of call wire, formed in the substrate, the call wire in their extension direction with it is corresponding described active Area's intersection, and transistor is collectively formed by the active area and the part call wire；

Wherein, the part constituting channel area of the call wire is corresponded in the active area, corresponds to the described of the channel region Substrate has the first top surface, and is formed with the relatively described first top surface recess at least in the substrate of the channel region One notch, the call wire cover first top surface of the channel region and fill the notch.

In the transistor combination structure of integrated circuit provided by the utility model, by corresponding to channel region in active area The first notch is formed in substrate, which is recessed relative to the first top surface of channel region.That is, being equivalent to the channel region With uneven surface, not only there is first surface, also there is the bottom table for the first notch being recessed relative to first surface Face and side wall, to considerably increase the effective area of channel region and wordline boundary.In the storage being made of active area and wordline When transistor turns, the conducting channel formed in channel region is that the interface pattern accordingly along channel region and wordline is anti- Type is formed, therefore can make to be formed by the cross sectional shape of conducting channel in a predetermined direction in bending, to be conducive to increase The length dimension and/or width dimensions of the conducting channel, and then the short-channel effect of constituted memory transistor can be improved, And increase the conducting electric current of memory transistor.Based on this, also helps and realize its memory-size of integrated circuit memory Reduction.

Detailed description of the invention

Fig. 1 is a kind of structural schematic diagram of the active area of storage unit；

Fig. 2 is the top view of the integrated circuit memory in the utility model embodiment one；

Fig. 3 is the structural schematic diagram of integrated circuit memory its active area in the utility model embodiment one；

Fig. 4 a is diagrammatic cross-section of the memory in the utility model embodiment one shown in Fig. 2 along the direction a1-a1 '；

Fig. 4 b is diagrammatic cross-section of the memory in the utility model embodiment one shown in Fig. 2 along the direction a2-a2 '；

Fig. 4 c is diagrammatic cross-section of the memory in the utility model embodiment one shown in Fig. 2 along the direction b1-b1 '；

Fig. 4 d is diagrammatic cross-section of the memory in the utility model embodiment one shown in Fig. 2 along the direction b2-b2 '；

Fig. 5 is knot of the integrated circuit memory after omitting wordline in the utility model embodiment one shown in Fig. 4 a Structure schematic diagram；

Fig. 6 is the top view of the integrated circuit memory in the utility model embodiment two；

Fig. 7 a is section of the integrated circuit memory on the direction aa ' in the utility model embodiment two shown in fig. 6 Schematic diagram；

Fig. 7 b is section of the integrated circuit memory on the direction bb ' in the utility model embodiment two shown in fig. 6 Schematic diagram；

Fig. 8 is the flow diagram of the forming method of the integrated circuit memory in the utility model embodiment three；

Fig. 9 a~Figure 12 a is that the forming method of the integrated circuit memory in the utility model embodiment three was prepared at it Top view in journey；

Fig. 9 b, Figure 10 b~Figure 10 c, Figure 11 b~Figure 11 c and Figure 12 b are the integrated circuit in the utility model embodiment three Diagrammatic cross-section of the forming method of memory in its preparation process.

Wherein, appended drawing reference is as follows:

10- active area；10C- channel region；

10S- source region；The drain region 10D-；

100- substrate；

110- active area；110C- channel region；

110S- source region；The drain region 110D-；

111C- conducting channel；The second notch of 111SD-；

The active row's group of 110A-；110B- has subject string group；

110P- virtual link point；

120- groove isolation construction；121- isolation structure；

200- wordline；

200G- gate portion；200L- interconnecting piece；

300- wordline groove；

300G- gate trench；300L- connection groove；

The first notch of 310G-；

400- separation layer；

500- shadow mask layer；

510- second is open；The initial groove of 511-；

600- wordline mask layer；610- first is open；

The first top surface of T11-；The bottom surface of the first notch of T12-；

The bottom surface of T13- connection groove；

The second top surface of T21-；The bottom surface of the second notch of T22-；

The first height and position of H1-；The second height and position of H2-；

H3- third height position；The 4th height and position of H4-；

The 5th height and position of H5-.

Specific embodiment

Below in conjunction with the drawings and specific embodiments to the utility model proposes integrated circuit memory and forming method thereof, Semiconductor devices is described in further detail.According to following explanation, will be become apparent from feature the advantages of the utility model.It needs to illustrate , attached drawing is all made of very simplified form and using non-accurate ratio, only conveniently, lucidly to aid in illustrating originally The purpose of utility model embodiment.

Embodiment one

Fig. 2 is the top view of the integrated circuit memory in the utility model embodiment one, and Fig. 3 is the utility model implementation The structural schematic diagram of integrated circuit memory its active area in example one, Fig. 4 a are the utility model embodiment one shown in Fig. 2 In memory along the direction a1-a1 ' diagrammatic cross-section, Fig. 4 b be the utility model embodiment one shown in Fig. 2 in storage For device along the diagrammatic cross-section in the direction a2-a2 ', Fig. 4 c is the memory in the utility model embodiment one shown in Fig. 2 along b1- The diagrammatic cross-section in the direction b1 ', Fig. 4 d are the memory in the utility model embodiment one shown in Fig. 2 along the direction b2-b2 ' Diagrammatic cross-section.In conjunction with shown in Fig. 2, Fig. 3 and Fig. 4 a~Fig. 4 d, the transistor combination structure packet of the integrated circuit memory Include: one substrate 100 and multiple wordline 200 for being formed on the substrate 100.

There are multiple active areas 110 in the substrate 100；And also there is groove isolation construction in the substrate 120, the groove isolation construction 120 is centered around the periphery of the active area 110, the adjacent active area 110 is isolated.

Emphasis is refering to what is shown in Fig. 2, the active area 110 extends along active length direction, and in the present embodiment, all has Source region 110 extends each along first direction (direction Z1) and multiple active areas 110 are arranged in array.The present embodiment In, multiple active areas 110 be aligned on active length direction arrangement to constitute multiple active rows, wherein can will it is multiple described in Adjacent two-by-two two active rows combine and constitute an active row and organize 110A in active row.

Continuing with shown in Fig. 2, Fig. 3 and Fig. 4 a~Fig. 4 d, a plurality of wordline 200 is formed in the substrate 100 simultaneously opposite Extend (in the present embodiment, the wordline extends along the Y direction) in the extending direction inclination of the active area, the wordline 200 Intersect on wordline extending direction with the corresponding active area 100, and by the active area 110 and the part wordline 200 Collectively form the transistor combination structure of integrated circuit memory.

Emphasis is with reference to Fig. 3 and combines shown in Fig. 4 a, and the part structure of 200 two sides of wordline is located in the active area 110 At the source region 110S and drain region 110D of the memory transistor.And the portion of the wordline 200 is corresponded in the active area 110 Divide constituting channel area 110C, the corresponding channel region 110C of the substrate 100 that there is the first top surface T11, and in the ditch At least one first notch 310G of the relatively described first top surface T11 recess is formed in the substrate 100 of road area 110C, that is, The bottom surface T12 of the first notch 310G more sinks relative to the first top surface T11 of the channel region 110C.The wordline 200 coverings the first top surface T11 simultaneously fills the first notch 310G.

It should be noted that the memory transistor being made of the wordline 200 and the active area 110, in its conducting When, corresponding to being capable of one conducting channel 111C of transoid formation in the channel region 110C and the substrate of the close wordline 200.Its In, since recess has the first notch 310G on the first top surface T11 of the channel region 110C, to make corresponding channel region The substrate surface of 110C shows as uneven surface (that is, section of the substrate surface of corresponding channel region 110C in a predetermined direction Face shape is bending structure), the wordline 200 is described in the uneven surface covering along the channel region 110C accordingly The substrate surface of channel region.In this way, the conducting channel 111C that transoid is formed is i.e. accordingly along institute when memory transistor conducting It states the boundary morphogenesis of wordline 200 and the substrate surface of the channel region 110C in the substrate, therefore can make to be formed Conducting channel 111C cross sectional shape in a predetermined direction be bending structure, and then be conducive to improve the memory transistor Conducting channel 111C size in a predetermined direction.

For example, the conducting channel 111C is on the direction of source region to drain region (that is, in the length of the conducting channel 111C On direction) cross sectional shape be in bending, that is, the length of the conducting channel 111C is increased, so as to improve State the short-channel effect of memory transistor；Alternatively, the conducting channel 111C in the direction perpendicular to source region to drain region (that is, In the width direction of the conducting channel 111C) cross sectional shape be in bending, then equivalent to increase the conducting channel The width of 110C is conducive to improve the memory transistor so as to effectively improve the conducting electric current of the memory transistor Conduction property.

With continued reference to shown in Fig. 4 a~Fig. 4 d, in the present embodiment, the conducting channel 111C cutting in the width direction Face shape is in bending.Wherein, Fig. 4 a illustrates the schematic cross-section of conducting channel 111C in the direction of the width, therefore Fig. 4 a Shown in conducting particles in conducting channel 111C be along the direction circulation perpendicular to paper；Fig. 4 d and Fig. 4 c are illustrated and are led The schematic cross-section of electric channel 111C in the longitudinal direction, therefore the conductive particle in conducting channel 111C shown in Fig. 4 d and Fig. 4 c Son is circulated along the direction of source region 110S to drain region 110D or drain region 110D to source region 110S.Therefore, in the present embodiment, lead to It crosses to form the first notch 310G, to have increased the overall width ruler of conducting channel 111C in the width direction of conducting channel 111C It is very little, so as to further widen the width dimensions for the conducting channel 111C that transoid is formed, be conducive to improve the storage crystalline substance The conducting electric current of body pipe.

In conjunction with shown in Fig. 2, Fig. 3 and Fig. 4 a, the bottom surface T12 of the first notch 310G in the present embodiment and first top Surface T11 constitute first step structure, and the first step structure on the extending direction perpendicular to the active area by Rank arrangement.Further, the first notch 310G can also extend along the extending direction of the active area, and in the extension Has identical length dimension with the channel region 110C on direction.That is, the first notch 310G is along being parallel to active area Direction extend, and can extend to the entire channel region 110C in their extension direction, therefore the entire channel region 110C may make up step structure.

Fig. 5 is knot of the integrated circuit memory after omitting wordline in the utility model embodiment one shown in Fig. 4 a Structure schematic diagram.In conjunction with shown in Fig. 4 a and Fig. 5, the wordline 200 in the present embodiment is buried in the substrate 100 for buried word line In.

Specifically, being formed with multiple wordline grooves 300 in the substrate 100, the wordline 200 is filled in the wordline ditch In slot 300, therefore the extending direction of the corresponding wordline 200 of the wordline groove 300 extends；Also, the wordline groove 300 The corresponding active area 110 is passed through on wordline extending direction, to make the wordline 200 can on wordline extending direction Intersect with corresponding active area 110.

And the part of the corresponding active area 110 of the wordline groove 300 constitutes gate trench 300G, the wordline The part of the 200 filling gate trench 300G is used to constitute the gate portion 200G of memory transistor.Wherein, the gate trench The bottom surface of 300G is the first top surface T11 of the channel region 110C, the first notch 310G, that is, corresponding phase For the bottom surface recess of the gate trench.

Specifically, the top surface of the substrate non-corresponding wordline has the first height and position H1, the gate trench The bottom surface T11 of 300G has third height with the bottom surface T12 of the second height and position H2 and the first notch 310G Position H3, wherein the first height and position H1 is higher than the second height and position H2, the second height and position H2 and is higher than third height position H3。

With continued reference to described in Fig. 4 a and Fig. 5, the wordline groove 300 also has multiple connection grooves in their extension direction 300L, the connection groove 300L is between the gate trench 300G adjacent on wordline extending direction, so that in word The adjacent gate trench 300G is interconnected on line extending direction；The wordline 200 fill the connection groove 300L with Interconnecting piece 200L, the interconnecting piece 200L and the gate portion 200G is constituted to be connected with each other.

It is believed that the connection groove 300L is corresponding in the groove isolation construction 120, the company of the wordline Socket part 200L is formed in accordingly in the groove isolation construction 120.Wherein, in the groove isolation construction 120 formed every From structure 121, the interconnecting piece 200L is formed on the isolation structure 121.

Emphasis is refering to what is shown in Fig. 5, in the embodiment of the present invention wordline groove 300, the bottom surface of the gate trench 300G T11 is prominent relative to the bottom surface T13 of the connection groove 300L and has protrusion side wall, and the wordline 200 fills the grid The pole groove 300G and connection groove 300L simultaneously covers the protrusion side wall, to constitute the grid of fin formula field effect transistor. Or it is to be understood that the bottom surface T13 for connecting and composing 300L is recessed relative to the bottom surface T11 of the gate trench 300G It falls into, in the present embodiment, the top surface of isolation structure 121 is lower than the channel region 110C in the as described groove isolation construction 120 The first top surface T11.

That is, the substrate of the corresponding channel region 110C is protruded relative to the isolation structure 121 of its two sides, to make wordline 200 can not only cover the top surface of the channel region 110C, can also cover the protrusion side wall of the two sides the channel region 110C. The fin formula field effect transistor constituted can not only form conduction in its conducting in substrate of the channel region close to top surface Channel can also be also formed with conducting channel in the substrate of the protrusion side wall in the gate regions, further increase The width dimensions of the conducting channel of the memory transistor.

Further, the gate trench 300G is arranged in close to the connection groove 300L's in the first notch 310G On side, and the bottom surface T12 of the first notch 310G is prominent relative to the bottom surface T13 of the connection groove 300L, So that bottom surface T13, the bottom surface T12 of first notch and the bottom surface T11 of the gate trench of the connection groove Multi-stage stairs structure is constituted, the multi-stage stairs structure is on the extending direction (perpendicular to the direction Z1) perpendicular to the active area It arranges stepwise.

In the present embodiment, the bottom surface T13 of the connection groove 300L has the 4th height and position H4, the connection groove The third height position H3 of the bottom surface T12 of the 4th height and position H4 of the bottom surface T13 of 300L, the first notch 310G, The first of the top surface of the second height and position H2 and substrate non-corresponding wordline of the bottom surface T11 of the gate trench 300G Height and position H1, is successively presented multi-stage stairs structure from low to high.

It should be noted that since the first notch 310G and connection groove 300L is interconnected, described first Notch 310G is removed close to the side wall for connecting and composing the side 300L, to make the bottom surface T12 of the first notch 310G The side wall for connecting the connection groove 300L is complied with, to constitute the multi-stage stairs structure.

Correspondingly, being connected in the memory transistor, and along the surface of substrate in the substrate close to gate portion 300G In the conducting channel 111C that pattern transoid is formed, the cross sectional shape of the conducting channel 111C in the width direction is in accordingly It is now multi-stage stairs structure.

Then shown in emphasis combination Fig. 3 and Fig. 4 b, positioned at the part point of 200 two sides of wordline in the active area 110 The source region 110S and drain region 110D and the substrate for not constituting the memory transistor correspond to the source region 110S and drain region 110D has the second top surface T21；And it is each formed in the substrate of the corresponding source region 110S and drain region 110D opposite At least one second notch 111SD of the second top surface T21 recess.

In the present embodiment, the substrate surface of the corresponding source region 110S and drain region 110D also shows as the table of out-of-flatness Face has accordingly increased the surface area of the source region 110S and the drain region 110D.Therefore, based on not changing the source region 110S On the basis of the projection size of the drain region 110D in the height direction, the source region 110S and the drain region are effectively increased 110D and the contact area being subsequently formed between other elements square thereon, and then contact resistance can be reduced accordingly；Or Person can also reduce the source region 110S in the case where the surface area of the holding source region 110S and drain region 110D is constant With the projection size of the drain region 110D in the height direction (that is, reducing the source region 110S and the drain region 110D in substrate The size occupied required for upper), it so can further reduce the overall dimensions of constituted memory transistor, be conducive to reality The highly dense arrangement of existing integrated circuit memory.

With continued reference to shown in Fig. 2 and 4b, in the source region 110S and the drain region 110D, second notch The bottom surface T22 of 111SD and the second top surface T21 can further constitute second step structure, and the second step Structure is arranged stepwise on the extending direction perpendicular to the active area.Further, the second notch 111SD can also be along The extending direction (direction Z1) of the active area extends, and on the extending direction of the active area with corresponding source region or drain region Has identical length dimension.That is, in the present embodiment, the second notch 111SD in the source region 110S and the drain region 110D, It is similar with the setting of the first notch 310G in the channel region 110C, it is to extend along the extending direction of the active area.

In optional scheme, in same active area, the height of the first notch 310G of the channel region 110C is thrown The end in the height projection area of the second notch 111SD of shadow zone and source region 110S/ drain region 110D is connected with each other.That is, In the present embodiment, the first notch 310G more sinks relative to the second notch 111SD, however in height projection area, The first notch 310G and the second notch 111SD can extend on the same line.

Specifically, the height and position of the second top surface T21 of the source region 110S and drain region 110D is i.e. corresponding as above First height and position H1 of the top surface of the substrate non-corresponding wordline, i.e., the described second top surface T21 have the first height Position H1, the bottom surface T22 of second notch have a 5th height and position H5, and the 5th height and position H5 is lower than described the One height and position H1.In the present embodiment, the height of the first height and position H1 and the 5th of the corresponding source region 110S and drain region 110D Height difference between the H5 of position, between the second height and position H2 of corresponding gate trench 300G and third height position H3 Height difference is equal or close.

With continued reference to shown in Fig. 2, in the present embodiment, multiple active areas 110 are in their extension direction (on the direction Z1) To constitute multiple active rows, two active rows adjacent two-by-two in multiple active rows can combine composition one has for alignment arrangement Source row organizes 110A.Wherein, the active area 110 in two active rows that each active row organizes 110A, on different rows The first notch 310G and second notch are formed on the side deviated from side close to each other or mutually 111SD.That is, the first notch 310G being located on different rows is close to each other or mutually deviates from, the second notch on different rows 111SD is close to each other or mutually deviates from.

Due to active row organize 110A in, two active row extend along direction alignment arrangement (i.e. arragement direction with have Source region extending direction is parallel), therefore the first notch 310G and the second notch 111SD can be arranged in each active row On same linear position on its arragement direction.In this way, can have when preparing first notch and second notch Conducive to the preparation difficulty for reducing by first notch and second notch.

In addition, the transistor combination structure of the integrated circuit memory further includes a separation layer 400, the separation layer 400 are formed on the substrate 100, and fill the part for being located at 200 top of wordline in the wordline groove 300, to cover Cover the wordline 200.

Embodiment two

Difference with embodiment one is, the integrated circuit memory in the present embodiment, partially has in multiple active areas Source region extends along a first direction, and another part active area extends along second direction.

Fig. 6 is the top view of the integrated circuit memory in the utility model embodiment two, and Fig. 7 a is shown in fig. 6 reality With diagrammatic cross-section of the integrated circuit memory in new embodiment two on the direction aa ', Fig. 7 b is shown in fig. 6 practical Diagrammatic cross-section of the integrated circuit memory on the direction bb ' in new embodiment two.

In conjunction with shown in Fig. 6 and Fig. 7 a~Fig. 7 b, in the present embodiment, multiple active areas 110 are along the wordline 200 Extending direction alignment is arranged to constitute multiple active column, and in two adjacent active column, wherein more in an active column A active area 110 extends each along first direction (direction Z1), and multiple active areas 110 in another active column are each along second party Extend to (direction Z2), so that two adjacent active column are relative to a center line mirror symmetry.Also, it is located at different lines In virtually intersect on the center line between adjacent two active areas 110 along the extending direction of two active areas and have Virtual link point 110P.

Further, multiple active areas 110 be based on the virtual link point 110P contact with constitute it is multiple have subject string, It is described to there is subject string to extend accordingly with waveform configuration.It is described to have subject string in the extension perpendicular to the wordline in the present embodiment Waveform extends on direction, i.e., described to have subject string to extend in X-direction.Wherein, multiple described to there are adjacent two-by-two in subject string two to have Subject string combination, which constitutes one, subject string group 110B.In optional scheme, have in subject string in each two for having subject string group 110B, Described first is formed with positioned at the side that difference has the active area 110 on subject string to deviate from side close to each other or mutually to lack Mouth 310G and the second notch 111SD.

With continued reference to described in Fig. 6 and Fig. 7 b, there is multiple groove isolation constructions 120, the groove in the substrate 100 Multiple isolation structures 121 are formed in isolation structure 120, for keeping adjacent active area 110 mutually isolated.In the present embodiment, Since multiple active areas 110 are aligned arrangement in a column direction, and it is arranged accordingly between adjacent active column Groove isolation construction 120 is stated, therefore the isolation structure 121 being formed between the adjacent active column is accordingly along institute The extending direction for stating wordline 200 extends.

Embodiment three

It is illustrated in the present embodiment by the forming method to integrated circuit memory, it is practical new this is explained further The transistor combination structure of tandem circuit memory provided by type.

Fig. 8 is the flow diagram of the forming method of the integrated circuit memory in the utility model embodiment three, Fig. 9 a ~Figure 12 a is vertical view of the forming method of the integrated circuit memory in the utility model embodiment three in its preparation process Figure；Fig. 9 b, Figure 10 b~Figure 10 c, Figure 11 b~Figure 11 c and Figure 12 b are the integrated circuit storage in the utility model embodiment three Diagrammatic cross-section of the forming method of device in its preparation process.The integrated circuit in the present embodiment is stored with reference to the accompanying drawing Each step of the forming method of device is described in detail.

In step S100, with specific reference to a substrate 100 shown in Fig. 9 a and Fig. 9 b, is provided, have in the substrate 100 multiple Active area 110, and definition has channel region 110C in the active area 110, is located at the channel region in the active area 110 The part of the two sides 110C is used to constitute the source-drain area of the transistor combination structure of integrated circuit memory.

In the present embodiment, multiple active areas 110 extend each along same direction (direction Z1), and in its extending direction Upper alignment arrangement is to constitute multiple active rows, and two active rows adjacent two-by-two combine that constitute one active in multiple active rows Row organizes 110A.

Step S200 is formed extremely with specific reference to shown in Figure 10 a~12a and Figure 10 b~10c, Figure 11 b~11c and Figure 12 b For a few first notch 310G in the substrate of the channel region 110C, the substrate of the corresponding channel region 110C has the first top Surface T11, the first notch 310G are recessed relative to the first top surface T11 of the channel region 110C, thus in shape After a plurality of wordline 200, the wordline 200 intersects with the corresponding active area 110 in their extension direction, and described The part of the corresponding active area of wordline 200 covers the first top surface T11 of the channel region 110C and fills described the One notch 310G.

Due to being formed with the first notch relative to the first top surface T11 recess in the partial region of the channel region 110C Still there is the first top surface T11, so that channel region 110C be made to have unevenness in another part region of 310G, channel region 110C Surface can increase the conduction of the memory transistor therefore when forming the wordline 200 to constitute memory transistor The size of channel.

In the present embodiment, being formed by wordline 200 is buried word line, i.e., the described wordline 200 is formed in the substrate.Tool For body with reference to shown in Figure 11 a and Figure 12 a, the forming method of the wordline 200 includes: firstly, forming wordline groove 300 in the lining In bottom 100, the wordline groove 300 passes through the channel region 110C of the active area and the wordline groove 300 corresponds to The part of the channel region constitutes gate trench 300G, and first notch is also formed in the gate trench 300G 310G；Then, filling wordline material is in the wordline groove 300, and to form the wordline 200, the wordline 200 is filled described Gate trench 300G simultaneously further fills the first notch 310G.

Further, the first notch 310G and the wordline groove 300 are formed in same step, that is, are forming institute While stating wordline groove 300, the first notch 310G is formed on the bottom of the wordline groove 300.Below in conjunction with attached To in the present embodiment, the forming method of the first notch 310G, wordline groove 300 and wordline 200 are described in detail figure.

First step, with specific reference to described in Figure 10 a and Figure 10 b, one shadow mask layer 500 of formation is in the substrate 100, institute It states and offers multiple second openings 510 in shadow mask layer 500, second opening 510 exposes the part channel region 110C, and another part channel region 110C is covered accordingly.In this step, the top surface of the substrate 100 is high with first Spend position H1.

As shown in Figure 10 a, multiple active areas 110 in the present embodiment constitute multiple active rows, it is multiple it is active come it is active It is aligned arrangement on the extending direction in area, and is further combined and constitutes multiple active rows' group 110A.At this point, the shadow mask can be made Second opening 510 of layer 500 extends along the extending direction of the active area, and keeps each second opening 510 sudden and violent Expose each active row and organize active area 110 in the 110A part close to each other in two active rows, to expose part The channel region 110C.That is, the part channel region 110C for being open using one while exposing multiple active areas 110, thus Be conducive to improve when can increase the opening size of second opening 510, and then see the second opening described in the definition it is corresponding described in The lithographic process window of second opening.

Second step is to serve as a contrast described in mask etching with the shadow mask layer 500 with specific reference to described in Figure 10 a and Figure 10 c Bottom 100, to form multiple initial grooves 511 in the substrate 100 of the channel region 110C.Then, the covering can be removed Mask layer 500.In this step, the bottom surface that can make to be formed by initial groove 511 has a 5th height and position H5, and described the Five height and position H5 are lower than the first height and position H1.

In the present embodiment, second opening 510 exposes the active area along the extending direction of the active area 110, to make to be formed by initial groove 511 accordingly along the extending direction extension of the active area, and make described initial Groove 511 has length dimension identical with the active area 110, i.e., extension of the described initial groove 511 in the active area It is extended on direction in the entire active area 110.

Third step forms a wordline mask layer 600 on the substrate 100 with specific reference to shown in Figure 11 a and Figure 11 b, Offered in the wordline mask layer 600 it is multiple first opening 610, it is described first opening 610 extending direction with it is described active The extending direction in area intersects, and exposes the channel region 110C of the active area, and corresponding sudden and violent in their extension direction Expose the part that the initial groove 511 is located in the channel region 110C.

In the present embodiment, the initial groove 511 is formed in the channel region 110C, also further extends to channel region In the active area 110 of periphery.Based on this, it is described just that first opening 610 of the wordline mask layer 600 only exposes part Beginning groove 511, wherein the corresponding part in the channel region of the initial groove 511 is used to form first notch, institute The part in initial groove 511 positioned at the channel region two sides is stated for constituting one second notch 111SD, second notch 111SD is corresponding in the source region 110S and drain region 110D.

Four steps is to serve as a contrast described in mask etching with the wordline mask layer 600 with specific reference to shown in Figure 11 a and Figure 11 c Bottom 100, to form multiple wordline grooves 300 in the substrate 100, the wordline groove 300 passes through in their extension direction The channel region 110C of corresponding active area, and the part of the corresponding channel region 110C of the wordline groove 300 constitutes grid ditch Slot 300G.And the corresponding initial groove 511 in the channel region constitutes the first notch 310G after etching, it is described First notch 310G is formed in the gate trench 300G, that is, the gate trench 300G corresponds to the initial groove 511 Part is recessed relative to the bottom surface T11 of the gate trench, to constitute the first notch 310G.In this way, can formed While the gate trench 300G, the first notch 310G is formed in the gate trench 300G.

Wherein, the bottom surface T11 of the grid groove of the wordline groove 300 has the second height and position H2, and described first There is the bottom surface T12 of notch third height position H3, the third height position H3 to be lower than the second height and position H2.

Further, the wordline groove 300 further includes connection groove 300L, and the 300L that connects and composes is located in wordline On extending direction between the adjacent gate trench 300G, for being connected to the grid ditch adjacent on wordline extending direction Slot 300G.

In preferred scheme, the bottom surface T13 of the connection groove 300L is more sunken to down the bottom of the gate trench 300G The bottom surface T11 of surface T11, i.e., the described gate trench are prominent relative to the bottom surface T13 of the connection groove and have protrusion Side wall.Wherein, there is the bottom surface T13 of the connection raceway groove the 4th height and position H4, the 4th height and position H4 to be lower than grid Second height and position H2 of pole trench bottom surfaces.

Optionally, the first notch 310G is close to connection groove 300L, and is connected to the connection groove 300L, and The bottom surface T13 of the connection groove more sinks relative to the bottom surface T12 of first notch.Therefore the bottom table of gate trench The bottom surface T13 of face T11, the bottom surface T12 of the first notch 310G and connection groove may make up multi-stage stairs structure.

5th step, with specific reference to wordline material shown in Figure 12 a and Figure 12 b, is filled in the wordline groove, to be formed The wordline 200.The wordline 200 fills the gate trench, first notch and the connection groove.

Wherein, the part that the gate trench and first notch are filled in the wordline 200 constitutes gate portion 200G, The part that the connection groove is filled in the wordline 200 constitutes interconnecting piece 200L.And it is located at institute in the active area 110 The part for stating 200 two sides of wordline is used to constitute the source region 110S and drain region 110D of the memory transistor.

So far, that is, a plurality of buried word line 200 is formd in the substrate 100, and makes the wordline 200 described in the correspondence The part of channel region 110C is not only filled with gate trench and also further fills the first notch.

Further, after forming the wordline 200, further includes:

Step S300 is continued to refer to figure 1 shown in 2b, a separation layer 400 is formed on the substrate 100, for covering State wordline 200.

Further, the top of the wordline 200 be lower than the wordline groove top, at this time the separation layer 400 into One step fills the part that the wordline groove is located above the wordline, to improve the isolation effect to the wordline.

It should be noted that being to extend and be aligned arrangement each along same direction with multiple active areas in the present embodiment to illustrate Release the forming method for illustrating integrated circuit memory.However, in other embodiments, multiple active areas are for example, by using shown in Fig. 6 Arrangement mode when, then can adjust accordingly shadow mask layer second opening pattern.

Specifically, in other embodiments, multiple active areas are aligned arrangement on the extending direction of the wordline To constitute multiple active column, and in two adjacent active column, wherein multiple active areas in an active column are each along One direction extends, and multiple active areas in another active column extend each along second direction, so that described adjacent two active Column are relative to a center line mirror symmetry, and along two active areas between adjacent two active areas in different lines Extending direction virtually intersects on the center line and has virtual link point.Wherein, multiple active areas are based on the void For quasi- tie point series winding to constitute the subject string that has that multiple waveforms extend, multiple described have adjacent two-by-two in subject string two to have subject string group Closing composition one has subject string group.

Based on this, then when forming initial groove, the second of shadow mask layer can be made, which to be open described in correspondence, subject string waveform Extend, and each second opening exposes and each described has the active area in subject string group to have subject string close to each other at two Part, to expose the part channel region.At this point, second opening also extends for waveform to there is subject string described in correspondence Pattern, and can also make to be formed by initial groove in corresponding active area along active area extension, and have with corresponding Source region has identical length dimension.

In addition, in semiconductor integrated circuit field, it can also be by the transistor group of above-described integrated circuit memory It closes structure and carries out corresponding modification, suitable for other semiconductor devices.Specifically, the integrated electricity of the semiconductor Road device includes:

One substrate has multiple active areas in the substrate；And

In semiconductor device as described above, capable of equally effectively increasing semiconductor device, it is brilliant The length and/or width of the conducting channel of body pipe, so as to effectively improve the conduction property of transistor and the short ditch of transistor Channel effect.In other words, crystalline substance can be effectively reduced in the case where realizing device dimensions shrink in the semiconductor device The problem of short-channel effect, occurs for body pipe, and avoids the conducting electric current of transistor too small, to ensure the conduction of the transistor Energy.

Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other The difference of embodiment, the same or similar parts in each embodiment may refer to each other.

Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the scope of the utility model Fixed, any change, the modification that the those of ordinary skill in the utility model field does according to the disclosure above content belong to right and want Seek the protection scope of book.

Claims

1. a kind of transistor combination structure of integrated circuit memory characterized by comprising

Substrate has multiple active areas in the substrate；And

A plurality of wordline is formed in the substrate, and the wordline intersects on wordline extending direction with the corresponding active area, The memory transistor of integrated circuit memory is collectively formed by the part of the active area and the wordline in the active area；

Wherein, the groove part constituting channel area of the wordline, the lining of the corresponding channel region are corresponded in the active area Bottom has the first top surface, and at least the one of the relatively described first top surface recess is formed in the substrate of the channel region A first notch, the wordline cover first top surface of the channel region and fill first notch.

2. the transistor combination structure of integrated circuit memory as described in claim 1, which is characterized in that the active area edge Active length direction extend, the bottom surface of first notch and first top surface constitute first step structure, described First step structure is arranged stepwise on the extending direction perpendicular to the active area.

3. the transistor combination structure of integrated circuit memory as claimed in claim 2, which is characterized in that first notch Extend along the extending direction of the active area, and has identical length ruler with the channel region on the extending direction It is very little.

4. the transistor combination structure of integrated circuit memory as described in claim 1, which is characterized in that shape in the substrate At there is multiple wordline grooves, the wordline is filled in the wordline groove, and the wordline groove is in wordline extending direction On pass through the channel region of corresponding active area；

Wherein, the part that the wordline groove corresponds to the channel region constitutes gate trench, the bottom surface pair of the gate trench First top surface of the channel region is answered, first notch is recessed relative to the bottom surface of the gate trench.

5. the transistor combination structure of integrated circuit memory as claimed in claim 4, which is characterized in that the wordline groove Also there are multiple connection grooves on wordline extending direction, the connection ditch slot position is described in adjacent on wordline extending direction Between gate trench, so that the gate trench adjacent on wordline extending direction is interconnected.

6. the transistor combination structure of integrated circuit memory as claimed in claim 5, which is characterized in that the wordline groove In, the bottom surface of the gate trench is prominent relative to the bottom surface of the connection groove and has protrusion side wall, the wordline It fills the gate trench and the connection groove and covers the protrusion side wall, to constitute the grid of fin formula field effect transistor Pole.

7. the transistor combination structure of integrated circuit memory as claimed in claim 6, which is characterized in that first notch The gate trench is set on the side of the connection groove, and the bottom surface of first notch is relative to described The bottom surface for connecting groove is prominent, so that the bottom surface and the grid of the bottom surface of the connection groove, first notch The bottom surface of groove constitutes multi-stage stairs structure, the multi-stage stairs structure on the extending direction perpendicular to the active area by Rank arrangement.

8. the transistor combination structure of integrated circuit memory as described in claim 1, which is characterized in that in the substrate also Be formed with groove isolation construction, the groove isolation construction is centered around the periphery of the active area, be isolated it is adjacent described in have Source region.

9. the transistor combination structure of integrated circuit memory as described in any one of claims 1 to 8, which is characterized in that institute State the source-drain area that the part in active area positioned at the wordline two sides constitutes the memory transistor, the institute of the corresponding source-drain area It states substrate and is each formed with the relatively described second top surface recess with the second top surface, and in the substrate of the corresponding source-drain area At least one second notch.

10. the transistor combination structure of integrated circuit memory as claimed in claim 9, which is characterized in that the active area Extend along active length direction, the bottom surface of second notch and second top surface constitute second step structure, institute Second step structure is stated to arrange stepwise on the extending direction perpendicular to the active area.

11. the transistor combination structure of integrated circuit memory as claimed in claim 10, which is characterized in that described second lacks Opening's edge the extending direction of the active area extend, and have on the extending direction of the active area with corresponding source region or drain region Standby identical length dimension.

12. the transistor combination structure of integrated circuit memory as claimed in claim 9, which is characterized in that the channel region First notch and second notch of the source-drain area extend each along active length direction, and same described In active area, the height projection area of first notch mutually interconnects on the same line with the height projection area of second notch It connects.

13. the transistor combination structure of integrated circuit memory as claimed in claim 9, which is characterized in that have described in multiple Source region extends each along same direction, and to constitute multiple active rows, multiple described have for alignment arrangement on active length direction Two active rows adjacent two-by-two, which combine, in the row of source constitutes active row's group；Wherein, have at two of each active row's group In the row of source, the side that the active area on different rows deviates from side close to each other or mutually is formed with described first and lacks Mouth and second notch.

14. the transistor combination structure of integrated circuit memory as claimed in claim 9, which is characterized in that have described in multiple Source region is aligned arrangement on wordline extending direction to constitute multiple active column, and in two adjacent active column, wherein one Multiple active areas in active column extend each along first direction, and multiple active areas in another active column are each along second direction Extend, so that adjacent two active column are relative to a center line mirror symmetry, and adjacent two in different lines Extending direction between a active area along two active areas virtually intersects on the center line and has virtual link point；

Wherein, multiple active areas be based on the virtual link point contact with constitute it is multiple have a subject string, multiple described have subject string In two-by-two adjacent two there is subject string combination to constitute one to have subject string group, have in subject string in each two for having subject string group, position In difference there is the active area on subject string to deviate from side close to each other or mutually sides be formed with first notch and Second notch.

15. a kind of semiconductor device characterized by comprising

Substrate has multiple active areas in the substrate；And

A plurality of call wire, formed in the substrate, the call wire on call wire extending direction with it is corresponding described active Area's intersection, and transistor is collectively formed by the part of the active area and the call wire in the active area；

Wherein, the part constituting channel area of the call wire, the substrate of the corresponding channel region are corresponded in the active area With top surface, and it is formed in the substrate of the channel region at least one notch of the relatively described top surface recess, institute Call wire is stated to cover the top surface of the channel region and fill the notch.