CN110569173B - Server health management chip based on Loongson IP core and implementation method - Google Patents
Server health management chip based on Loongson IP core and implementation method Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
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- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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Abstract
The invention discloses a server health management chip based on a Loongson IP core and an implementation method, which belong to the field of chip design, and the technical problem to be solved by the invention is how to realize the autonomous controllability of a whole module of a chip, and the adopted technical scheme is as follows: the chip comprises a Loongson main processor, a Loongson coprocessor, an internal bus interconnection module, a high-speed interface module, a low-speed interface module and a video compression engine module, wherein the Loongson main processor and the Loongson coprocessor both adopt a Loongson IP core as a main processing unit of the chip; the Loongson main processor and the Loongson coprocessor are respectively connected with an internal bus interconnection module, and the internal bus interconnection module is respectively connected with the high-speed interface module, the low-speed interface module and the video compression engine module. The invention also discloses a server health management implementation method based on the Loongson IP core.
Description
Technical Field
The invention relates to the field of chip design, in particular to a server health management chip based on a Loongson IP core and an implementation method.
Background
Servers have been developed in recent years as key equipment for a new generation of information-oriented industries. The core chip mainly comprises three parts, namely a CPU chip, an exchange chip and a health management chip, wherein the health management chip is used as a management and control chip of the server and is a window of the server, and the core chip plays a vital role in safe and efficient use of the server. At present, the CPU and the exchange chip of the three chips are all realized home-made substitution, and the health management chip is not realized home-made in the late stage. Therefore, how to realize the autonomous control of the whole chip module is a technical problem in the prior art.
Disclosure of Invention
The invention provides a server health management chip based on a Loongson IP core and an implementation method thereof, and aims to solve the problem of how to realize the autonomous controllability of all modules of the chip.
The technical task of the invention is realized according to the following mode, the server health management chip based on the Loongson IP core comprises a Loongson main processor, a Loongson coprocessor, an internal bus interconnection module, a high-speed interface module, a low-speed interface module and a video compression engine module, wherein the Loongson main processor and the Loongson coprocessor both adopt the Loongson IP core as a main processing unit of the chip; the Loongson main processor and the Loongson coprocessor are respectively connected with an internal bus interconnection module, and the internal bus interconnection module is respectively connected with the high-speed interface module, the low-speed interface module and the video compression engine module.
Preferably, the Loongson main processor is used for running an operating system, various application layer software and control instructions; the Loongson coprocessor is used for completing low-speed tasks and assisting the Loongson main processor.
Preferably, the internal bus interconnection module comprises an AXI to APB interconnection unit, an AXI interconnection unit and an AHB interconnection unit;
an APB bus is led out from the AXI-APB interconnection unit and used for accessing the low-speed interface module;
an AXI-4 bus is led out from the AXI interconnection unit, and the AXI-4 bus is used for accessing an external memory to finish the operation on the memory;
an AHB bus is led out from the AHB interconnection unit and used for accessing the high-speed interface module.
Preferably, the high-speed interface module supports gigabit ethernet, USB interface, DVI video interface, and DDR3 interface; the Loongson main processor and the Loongson coprocessor access the DDR3 interface controller IP through an AXI-4 bus to complete the operation on the memory; the Loongson main processor and the Loongson coprocessor access the gigabit Ethernet and the USB interface through an AHB.
Preferably, the low-speed interface module supports an LPC interface, a UART interface, an IIC interface, an SPI interface and a GPIO interface; the Loongson main processor and the Loongson coprocessor convert an AXI interface into an APB interface through an internal bus interconnection module, and access an LPC interface, a UART interface, an IIC interface and an SPI interface.
Preferably, the video compression engine module adopts an H.264 standard compression algorithm, supports 1080P definition compression, and realizes a KVM over IP function based on the compression technology.
A server health management implementation method based on a Loongson IP core comprises the following steps:
s1, inputting an external video input signal into a Loongson main processor and a Loongson coprocessor through a DVI video interface, converting the external video input signal into an RGB signal through a DVI video interface IP, and caching the RGB signal into a video signal stream Buffer;
s2, reading the RGB signals by the video compression IP when the video stream is cached to a set frame number, completing hardware JPEG compression and caching to a compression Buffer;
s3, when the compression Buffer caches to the set frame number, calling the DDR3 interface controller IP through DMA, writing the IP into a corresponding memory address, and finishing the temporary storage of video compression;
s4, after video compression of a set frame is completed, the Loongson main processor and the Loongson coprocessor call a DDR3 interface controller IP to send a video in the DDR3 interface to a remote computer through a gigabit Ethernet, after local health management information is collected by an external acquisition chip, the health management information is read into the chip through a low-speed interface module and is sent to the Loongson main processor and the Loongson coprocessor through an APB interface and an internal bus interconnection module;
and S5, the Loongson main processor and the Loongson coprocessor are sent to the remote computer through the Ethernet and displayed on a Web interface, so that monitoring of related health information is completed.
Preferably, the mouse and keyboard information of the remote computer in the steps S4 and S5 is sent to the Loongson main processor and the Loongson coprocessor via the AHB bus and the internal bus interconnection module through the gigabit ethernet, and after the Loongson main processor and the Loongson coprocessor make a judgment, the signal of the mouse and keyboard information is directly sent out from the AHB bus to the corresponding USB port
Preferably, the health management information in step S4 includes a voltage signal and a current signal of the server.
Preferably, in step S4, the low-speed interface module adopts an IIC interface.
The server health management chip based on the Loongson IP core and the implementation method have the following advantages:
the invention adopts a Loongson IP core as a processor unit to realize the autonomous controllability of the whole chip module;
the Loongson main processor and the Loongson coprocessor are composed of a master-slave architecture, and the Loongson main processor is responsible for running an operating system and various application layer software; the co-processing unit loongson main processor is responsible for processing some low-speed tasks and assisting the loongson main processor;
the Loongson main processor and the Loongson coprocessor are used as a CPU unit, so that the independent control of the CPU unit is realized; the system supports three internal buses, namely an AXI-4 bus, an AHB bus and an APB bus, wherein the AXI-4 bus is used for accessing an external memory, the AHB bus is used for accessing a high-speed interface, and the APB bus is used for accessing a low-speed interface; meanwhile, the system supports abundant peripheral interfaces such as gigabit Ethernet, USB interfaces, DVI interfaces and IIC interfaces, supports KVM over IP functions, can realize remote visual monitoring of mainboard information, and has the advantages of exquisite design, advanced technology, convenience and simplicity in use and wide application prospect.
Drawings
The invention is further described below with reference to the accompanying drawings.
Fig. 1 is a block diagram of a server health management chip based on a Loongson IP core.
Detailed Description
The server health management chip based on the Loongson IP core and the implementation method thereof according to the present invention are described in detail below with reference to the drawings and the specific embodiments of the specification.
Example 1:
as shown in fig. 1, the server health management chip based on the Loongson IP core of the present invention includes a Loongson main processor, a Loongson coprocessor, an internal bus interconnection module, a high-speed interface module, a low-speed interface module and a video compression engine module, wherein the Loongson main processor and the Loongson coprocessor both use the Loongson IP core as a main processing unit of the chip; the Loongson main processor and the Loongson coprocessor are respectively connected with an internal bus interconnection module, and the internal bus interconnection module is respectively connected with the high-speed interface module, the low-speed interface module and the video compression engine module.
The Loongson main processor is used for running an operating system, various application layer software and control instructions; the Loongson coprocessor is used for finishing low-speed tasks and assisting the Loongson main processor.
The internal bus interconnection module comprises an AXI-APB interconnection unit, an AXI interconnection unit and an AHB interconnection unit; an APB bus is led out from the AXI-APB interconnection unit and used for accessing the low-speed interface module; an AXI-4 bus is led out from the AXI interconnection unit, and the AXI-4 bus is used for accessing an external memory to finish the operation on the memory; an AHB bus is led out from the AHB interconnection unit and used for accessing the high-speed interface module.
The high-speed interface module supports a gigabit Ethernet, a USB interface, a DVI video interface and a DDR3 interface; the Loongson main processor and the Loongson coprocessor access the DDR3 interface controller IP through an AXI-4 bus to complete the operation on the memory; the Loongson main processor and the Loongson coprocessor access the gigabit Ethernet and the USB interface through an AHB.
Preferably, the low-speed interface module supports an LPC interface, a UART interface, an IIC interface, an SPI interface and a GPIO interface; the Loongson main processor and the Loongson coprocessor convert an AXI interface into an APB interface through an internal bus interconnection module and access an LPC interface, a UART interface, an IIC interface and an SPI interface.
The video compression engine module adopts an H.264 standard compression algorithm, supports 1080P definition compression and realizes a KVM over IP function based on the compression technology.
Example 2:
the invention discloses a server health management implementation method based on a Loongson IP core, which comprises the following steps:
s1, inputting an external video input signal into a Loongson main processor and a Loongson coprocessor through a DVI video interface, converting the external video input signal into an RGB signal through a DVI video interface IP, and caching the RGB signal into a video signal stream Buffer;
s2, reading the RGB signals by the video compression IP when the video stream is cached to a set frame number, completing hardware JPEG compression and caching to a compression Buffer;
s3, when the compression Buffer caches to the set frame number, calling the DDR3 interface controller IP through DMA, writing the IP into a corresponding memory address, and finishing the temporary storage of video compression;
s4, after video compression of a set frame is completed, the Loongson main processor and the Loongson coprocessor call a DDR3 interface controller IP to send a video in the DDR3 interface to a remote computer through a gigabit Ethernet, after local health management information is collected by an external acquisition chip, the health management information is read into the chip through a low-speed interface module and is sent to the Loongson main processor and the Loongson coprocessor through an APB interface and an internal bus interconnection module;
and S5, the Loongson main processor and the Loongson coprocessor are sent to a remote computer through the Ethernet and displayed on a Web interface, so that monitoring of the related health information is completed.
In the step S4 and the step S5, the mouse and keyboard information of the remote computer is transmitted to the Loongson main processor and the Loongson coprocessor through the gigabit Ethernet via the AHB bus and the internal bus interconnection module, and after the Loongson main processor and the Loongson coprocessor make judgment, the signals of the mouse and keyboard information are directly transmitted to the corresponding USB port from the AHB bus
The health management information in step S4 includes a voltage signal and a current signal of the server.
And step S4, the low-speed interface module adopts an IIC interface.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A server health management chip based on a Loongson IP core is characterized by comprising a Loongson main processor, a Loongson coprocessor, an internal bus interconnection module, a high-speed interface module, a low-speed interface module and a video compression engine module, wherein the Loongson main processor and the Loongson coprocessor both adopt the Loongson IP core as a main processing unit of the chip; the Loongson main processor and the Loongson coprocessor are respectively connected with an internal bus interconnection module, and the internal bus interconnection module is respectively connected with a high-speed interface module, a low-speed interface module and a video compression engine module;
the working process of the chip is as follows:
s1, inputting an external video input signal into a Loongson main processor and a Loongson coprocessor through a DVI video interface, converting the external video input signal into an RGB signal through a DVI video interface IP, and caching the RGB signal into a video signal stream Buffer;
s2, reading the RGB signals by the video compression IP when the video stream is cached to a set frame number, completing hardware JPEG compression and caching to a compression Buffer;
s3, when the compressed Buffer caches the set frame number, calling the DDR3 interface controller IP through DMA, writing the IP into a corresponding memory address, and finishing the temporary storage of video compression;
s4, after video compression of a set frame is completed, the Loongson main processor and the Loongson coprocessor call a DDR3 interface controller IP to send a video in the DDR3 interface to a remote computer through a gigabit Ethernet, after local health management information is collected by an external acquisition chip, the health management information is read into the chip through a low-speed interface module and is sent to the Loongson main processor and the Loongson coprocessor through an APB interface and an internal bus interconnection module;
and S5, the Loongson main processor and the Loongson coprocessor are sent to a remote computer through the Ethernet and displayed on a Web interface, so that monitoring of the related health information is completed.
2. The server health management chip based on the Loongson IP core as claimed in claim 1, wherein the Loongson main processor is used for running an operating system, various application layer software and control instructions; the Loongson coprocessor is used for completing low-speed tasks and assisting the Loongson main processor.
3. The server health management chip based on the Loongson IP core of claim 1 or 2, wherein the internal bus interconnection module comprises an AXI-to-APB interconnection unit, an AXI interconnection unit and an AHB interconnection unit;
an APB bus is led out from the AXI-APB interconnection unit and used for accessing the low-speed interface module;
an AXI-4 bus is led out from the AXI interconnection unit, and the AXI-4 bus is used for accessing an external memory to finish the operation on the memory;
and an AHB bus is led out from the AHB interconnection unit and used for accessing the high-speed interface module.
4. The Loongson IP core-based server health management chip of claim 3, wherein the high-speed interface module supports gigabit Ethernet, USB interface, DVI video interface and DDR3 interface; the Loongson main processor and the Loongson coprocessor access the DDR3 interface controller IP through the AXI-4 bus to complete the operation on the memory; the Loongson main processor and the Loongson coprocessor access the gigabit Ethernet and the USB interface through an AHB.
5. The Loongson IP core-based server health management chip of claim 3, wherein the low-speed interface module supports an LPC interface, a UART interface, an IIC interface, an SPI interface, and a GPIO interface; the Loongson main processor and the Loongson coprocessor convert an AXI interface into an APB interface through an internal bus interconnection module and access an LPC interface, a UART interface, an IIC interface and an SPI interface.
6. The Loongson IP core-based server health management chip of claim 1, wherein the video compression engine module supports 1080P definition compression using an H.264 standard compression algorithm.
7. A server health management implementation method based on a Loongson IP core is characterized by comprising the following steps:
s1, external video input signals are input into a Loongson main processor and a Loongson coprocessor through a DVI video interface, converted into RGB signals through a DVI video interface IP and cached to a video signal stream Buffer;
s2, reading the RGB signals by the video compression IP when the video stream is cached to a set frame number, completing hardware JPEG compression and caching to a compression Buffer;
s3, when the compression Buffer caches to the set frame number, calling the DDR3 interface controller IP through DMA, writing the IP into a corresponding memory address, and finishing the temporary storage of video compression;
s4, after video compression of a set frame is completed, the Loongson main processor and the Loongson coprocessor call the DDR3 interface controller IP to send the video in the DDR3 interface to a remote computer through a gigabit Ethernet, after local health management information is collected by an external acquisition chip, the health management information is read into the chip through a low-speed interface module and is sent to the Loongson main processor and the Loongson coprocessor through an APB interface and an internal bus interconnection module;
and S5, the Loongson main processor and the Loongson coprocessor are sent to the remote computer through the Ethernet and displayed on a Web interface, so that monitoring of related health information is completed.
8. The method for implementing server health management based on the Loongson IP core according to claim 7, wherein mouse and keyboard information of the remote computer in the step S4 and the step S5 is sent to the Loongson main processor and the Loongson coprocessor through a gigabit Ethernet via an AHB bus and an internal bus interconnection module, and after the Loongson main processor and the Loongson coprocessor make a judgment, signals of the mouse and keyboard information are directly sent out to the corresponding USB port from the AHB bus.
9. The method for implementing server health management based on Loongson IP core in claim 7, wherein the health management information in the step S4 comprises a voltage signal and a current signal of the server.
10. The method for implementing server health management based on Loongson IP core as claimed in claim 7, wherein the low speed interface module in step S4 adopts IIC interface.
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| CN112199322A (en) * | 2020-09-30 | 2021-01-08 | 中国电力科学研究院有限公司 | A power intelligent control terminal and its RISC-V-based SOC power chip architecture |
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