CN216565293U

CN216565293U - Image acquisition system based on ESP8266 wireless communication circuit

Info

Publication number: CN216565293U
Application number: CN202122633626.4U
Authority: CN
Inventors: 刘晓霞
Original assignee: Beijing Shengxun Technology Co ltd
Current assignee: Beijing Shengxun Technology Co ltd
Priority date: 2021-10-31
Filing date: 2021-10-31
Publication date: 2022-05-17
Anticipated expiration: 2031-10-31

Abstract

The utility model discloses an image acquisition system based on an ESP8266 wireless communication circuit, which relates to the technical field of image acquisition and comprises a CMOS image acquisition module, a main control module, a wireless communication circuit, a storage module and a power module, wherein the CMOS image acquisition module comprises an AR0230CS sensor and an SLVS interface, the storage module comprises a 256Mb Flash module and a 4Gb DDR3 module, the wireless communication circuit selects the ESP8266 as the main control chip for use, in addition, when the ESP is used as the communication module for application, a terminal device is accessed to the Internet for data transmission by converting a serial port into WIFI, and on the basis of analyzing the power consumption tension of increasingly miniaturized and integrated aerospace image devices, an interface scheme taking a domestic video processing chip Hi3516D as a core is designed, so that the device can use the interface to realize the functions of low power consumption, low code rate and high quality image acquisition and transmission.

Description

Image acquisition system based on ESP8266 wireless communication circuit

Technical Field

The utility model relates to the technical field of low-power-consumption image acquisition, in particular to an image acquisition system based on an ESP8266 wireless communication circuit.

Background

With the rapid development of the electronic industry and the continuous and severe aerospace experimental conditions, the miniaturization and integration of the carrying equipment are continuously improving the requirements, and the image data plays an increasingly important data support role as an intuitive data source.

For aerospace equipment, the space is generally limited, the energy consumption is precious, and the bandwidth is limited, so that the power consumption of a carried image acquisition system is reduced as much as possible on the premise of ensuring the image quality, the image acquisition system is expected to work for a long time, the code rate is reduced as much as possible, the storage space is expected to be saved, the bandwidth utilization rate is reduced, and the storage space and the bandwidth utilization rate are expected to be saved.

For example, for some telemetry equipment, the telemetry broadband is generally 2Mb/s to 5Mb/s, the working time can be as long as several hours, the running state image of the equipment needs to be acquired in real time, for most feasible schemes, some common ABM processor architectures can be used for real-time transmission, but the image resolution is reduced; some design frames adopting FPGA acquisition, Flash storage and DDR reading can achieve the open resolution, but the requirements on instantaneity and code rate do not reach the standard.

The miniaturization of the embedded system equipment and the high integration of the chip enable the power consumption of the chip to be obviously increased. After the chip works stably, the temperature rises by 10 ℃, and the reliability of the chip is reduced by about half. The problems include electromigration, increase of wiring resistance, increase of line delay and the like, and finally the delay fault rate is increased.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem of providing an image acquisition system based on an ESP8266 wireless communication circuit aiming at the defects of the background technology, and designs an interface scheme taking a domestic video processing chip Hi3516D as a core on the basis of analyzing the power consumption tension of increasingly miniaturized and integrated aerospace image equipment, so that the equipment can realize the image acquisition and transmission functions of low power consumption, low code rate and high quality by using the interface.

The utility model adopts the following technical scheme for solving the technical problems:

an image acquisition system based on an ESP8266 wireless communication circuit comprises a CMOS image acquisition module, a main control module, a wireless communication circuit, a storage module and a power module, wherein the CMOS image acquisition module comprises an AR0230CS sensor and an SLVS interface, the storage module comprises a 256Mb Flash module and a 4Gb DDR3 module, the AR0230CS sensor is connected with the main control module through the SLVS interface, the Flash module and the DDR3 module are respectively connected with the main control module, and the wireless communication circuit is connected with the main control module through an RS422 interface;

the wireless communication circuit comprises an antenna ANT1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a resistor R1, a resistor R2, an inductor L1, an inductor L2, a chip U1, a chip U2, a chip U3 and a VDD terminal, wherein the antenna ANT1 is connected with one end of the inductor L1 and one end of the capacitor C6 respectively, the other end of the inductor L1 is grounded, the other end of the capacitor C6 is connected with one end of the inductor L2 and the pin 2 of the chip U1 respectively, the other end of the inductor L2 is grounded, the pin 3 of the chip U1 and the pin 4 of the chip U1 are connected with one end of the capacitor C4, one end of the capacitor C5 and the VDD terminal respectively, the other end of the capacitor C4 and the other end of the capacitor C5 are grounded respectively, the pin 1 of the chip U1 is connected with one end of the capacitor C3, the pin 30 of the chip U3 and the other end of the pin U3 of the capacitor U3 are connected with the pin 3, the pin 3 of the chip U3, and the pin 3 of the chip is connected with the chip 3, and the pin 3 of the chip U3, and the pin 3 of the chip is connected with the pin 3, and the pin 3 of the chip is connected with the chip 3, and the pin 3 of the chip 3, and the chip 3 is connected with the chip 3, and the pin 3 of the chip U3 is connected with the chip 3, the other end of the resistor R1 is grounded, the pin 28 of the chip U1 is respectively connected with one end of the capacitor C1 and the pin 1 of the chip U2, the pin 2 of the chip U2 is grounded, the other end of the capacitor C1 is grounded, the pin 4 of the chip U2 is grounded, the pin 3 of the chip U2 is respectively connected with one end of the capacitor C2 and the pin 27 of the chip U1, the other end of the capacitor C2 is grounded, the pin 18 of the chip U1 is connected with the pin 7 of the chip U3, the pin 19 of the chip U1 is connected with the pin 3 of the chip U3, the pin 20 of the chip U1 is connected with the pin 1 of the chip U3, the pin 21 of the chip U1 is connected with the pin 6 of the chip U3 through the resistor R2, the pin 22 of the chip U1 is connected with the pin 2 of the chip U3, the pin 23 of the chip U1 is connected with the pin 5 of the chip U3, and the pin 17 of the chip U1 is respectively connected with the pin 11 and the pin VDD of the chip U1.

As a further preferable scheme of the image acquisition system based on the ESP8266 wireless communication circuit, the power module includes an AVS voltage-regulating single circuit and an inner core voltage output circuit, and the AVS voltage-regulating single circuit and the inner core voltage output circuit include a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first inductor L1, a chip MP2122, a voltage +5V end, a voltage-regulating circuit output AVS end, and an inner core voltage output CPU end;

wherein, the +5V end is respectively connected with one end of a first capacitor C1, one end of a second capacitor C2, the EN1 end of a chip MP2122 and the IN end of the chip MP2122, the other end of the first capacitor C1 and the other end of the second capacitor C2 are connected and grounded, the SW1 end of the chip MP2122 is connected with one end of a first inductor L1, the other end of the first inductor L1 is respectively connected with one end of a first resistor R1, one end of a third capacitor C3, one end of a fourth capacitor C4 and the core voltage output CPU end, the other end of the third capacitor C3 and the other end of a fourth capacitor C4 are connected and grounded, the other end of the first resistor R1 is respectively connected with one end of a third resistor R3, one end of a fourth resistor R4 and one end of a second resistor R2, the other end of the third resistor R3 is grounded, the other end of the fourth resistor R4 is connected with one end of a sixth resistor R6, the other end of the sixth resistor R9358 is connected with one end of the fifth capacitor C3646, the other end of the fifth resistor R5 is connected to the AVS terminal of the voltage-regulating circuit, the other end of the fifth capacitor C5 is grounded, and the other end of the second resistor R2 is connected to the FB1 terminal of the MP 2122.

As a further preferable scheme of the image acquisition system based on the ESP8266 wireless communication circuit, the master module adopts a Hi3516D chip of the domestic hais company, receives data from the CMOS image acquisition module through the MIPI manager, performs optimization processing and H264 coding compression, and outputs the data to the RS422 wireless communication circuit through the USRT interface.

As a further preferable scheme of the image acquisition system based on the ESP8266 wireless communication circuit, the model of the chip of the Flash module is MX25L 25635F.

As a further preferable scheme of the image acquisition system based on the ESP8266 wireless communication circuit, the chip model of the DDR3 module is K4B4G 1646E.

Compared with the prior art, the utility model adopting the technical scheme has the following technical effects:

1. the utility model relates to an image acquisition system based on an ESP8266 wireless communication circuit, which designs an interface scheme taking a domestic video processing chip Hi3516D as a core on the basis of analyzing the power consumption tension of increasingly miniaturized and integrated aerospace image equipment, so that the equipment can realize the image acquisition and transmission functions of low power consumption, low code rate and high quality by applying the interface;

2. the utility model adopts an ESP8266 wireless communication circuit, which comprises an antenna ANT1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a resistor R1, a resistor R2, an inductor L1, an inductor L2, a chip U1, a chip U2, a chip U3 and a VDD end, wherein the ESP8266 is selected as a main control chip for use, in addition, when the ESP is used as a communication module, the terminal equipment is accessed to the Internet for data transmission by converting a serial port into WIFI, a basic network topological structure is adopted in the communication mode, the ESP8266 is a serial port-to-wireless module chip, firmware is arranged in the ESP8266 wireless communication circuit, the operation is simple, and time sequence signals do not need to be written;

3. the image acquisition module adopts a high-dynamic low-power AR0230CS sensor, has a high dynamic range of 96dB and a high signal-to-noise ratio of 41dB, and has the maximum output capacity of 1080P @60 fps;

4. the storage module of the utility model uses a 256Mb Flash module and a 4Gb DDR3 module, the DDR3 supports the highest working frequency of 600MHz, and a low power consumption mode can be set;

5. the main control module adopts a Hi3516D chip of a domestic Haishi company, receives data from a CMOS image acquisition module through an MIPI manager, performs optimization processing and H264 coding compression, outputs the data to an RS422 wireless communication circuit through a USRT interface, triggers the chip from an advanced low-power-consumption process and a low-power-consumption framework, simultaneously adopts an inner core of ARM Cortex A7, and has the maximum output capacity of 1080P @60 fps;

6. the utility model can further reduce the power consumption and exert the advantage of the Hi3516D low-power-consumption architecture, thereby adding AVS support for the power supply branch which is key to the main control chip and has higher power consumption, and leading the Hi3516D to dynamically adjust the two paths of voltage according to the occupancy rates of CPUs operating different services.

Drawings

FIG. 1 is a schematic diagram of the structure of an image acquisition system of the present invention;

FIG. 2 is a wireless communication circuit of the present invention

Fig. 3 is a circuit diagram of the power module of the present invention.

Detailed Description

The technical scheme of the utility model is further explained in detail by combining the attached drawings:

the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An image acquisition system based on an ESP8266 wireless communication circuit is shown in figure 1 and comprises a CMOS image acquisition module, a main control module, a wireless communication circuit, a storage module and a power module, wherein the CMOS image acquisition module comprises an AR0230CS sensor and an SLVS interface, the storage module comprises a 256Mb Flash module and a 4Gb DDR3 module, the AR0230CS sensor is connected with the main control module through the SLVS interface, the Flash module and the DDR3 module are respectively connected with the main control module, and the wireless communication circuit is connected with the main control module through an RS422 interface; the image acquisition module adopts a high-dynamic low-power AR0230CS sensor and sends image data to the main control module through an SLVS interface. The high-power-factor optical fiber has a high dynamic range of 96dB, a high signal-to-noise ratio of 41dB and a maximum output capacity of 1080P @60 fps.

The main control module adopts a Hi3516D chip of a domestic Seishi company, receives data from a CMOS image acquisition module through an MIPI manager, performs optimization processing and H264 coding compression, outputs the data to an RS422 wireless communication circuit through a USRT interface, is triggered by an advanced low-power-consumption process and a low-power-consumption framework, simultaneously adopts an ARM Cortex A7 kernel, and has the maximum output capacity of 1080 @ P60 fps.

The storage module of the utility model uses a 256Mb Flash module and a 4Gb DDR3 module, the DDR3 supports the highest working frequency of 600MHz, and a low power consumption mode can be set; the chip model of the Flash module is MX25L25635F, and the chip model of the DDR3 module is K4B4G 1646E.

As shown in fig. 2, the wireless communication circuit includes an antenna ANT1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a resistor R1, a resistor R2, an inductor L1, an inductor L2, a chip U1, a chip U2, a chip U3, and a VDD terminal, wherein the antenna ANT1 is connected to one end of the inductor L1 and one end of the capacitor C6, respectively, the other end of the inductor L1 is grounded, the other end of the capacitor C6 is connected to one end of the inductor L2 and the pin 2 of the chip U1, respectively, the other end of the inductor L2 is grounded, the pin 3 of the chip U1 and the pin 4 of the chip U1 are connected to one end of the capacitor C4, one end of the capacitor C5 and the VDD terminal, respectively, the other end of the capacitor C4 and the other end of the capacitor C5 are grounded, the pin 1 of the chip U1 is connected to one end of the capacitor C3, the pin 3 of the VDD, the pin 3 of the U3 and the pin 3 of the chip U3, the pin 3 of the chip 3 and the pin 3 of the chip U3 are connected to the chip 3, the other end of the resistor R1 is grounded, the pin 28 of the chip U1 is respectively connected with one end of the capacitor C1 and the pin 1 of the chip U2, the pin 2 of the chip U2 is grounded, the other end of the capacitor C1 is grounded, the pin 4 of the chip U2 is grounded, the pin 3 of the chip U2 is respectively connected with one end of the capacitor C2 and the pin 27 of the chip U1, the other end of the capacitor C2 is grounded, the pin 18 of the chip U1 is connected with the pin 7 of the chip U3, the pin 19 of the chip U1 is connected with the pin 3 of the chip U3, the pin 20 of the chip U1 is connected with the pin 1 of the chip U3, the pin 21 of the chip U1 is connected with the pin 6 of the chip U3 through the resistor R2, the pin 22 of the chip U1 is connected with the pin 2 of the chip U3, the pin 23 of the chip U1 is connected with the pin 5 of the chip U3, and the pin 17 of the chip U1 is respectively connected with the pin 11 and the pin VDD of the chip U1.

The ESP8266 is selected as a main control chip, and when the ESP8266 is applied as a communication module, the terminal equipment is connected to the Internet for data transmission through serial port-to-WIFI conversion, a basic network topological structure is adopted in a communication mode, the ESP8266 is a serial port-to-wireless module chip, firmware is carried in the ESP8266, user operation is simple, and time sequence signals do not need to be written.

The power supply module mainly adopts high-efficiency DC/DC such as MP2122 and the like. Through current evaluation, two more critical power supplies with larger power consumption are considered emphatically, the average current is about 900mA, and the maximum current is 1A aiming at the voltage of 1.1V of the core of Hi 3516D; considering the influence of temperature and leaving more than 50% of design margin, and then selecting according to layout space, cost and supply period, the MP2122 is selected to provide the core 1.1V voltage of Hi 3516D.

As shown in fig. 3, the power module includes an AVS voltage-regulating single circuit and an inner core voltage output circuit, where the AVS voltage-regulating single circuit and the inner core voltage output circuit include a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first inductor L1, a chip MP2122, a voltage +5V terminal, an AVS output terminal of the voltage-regulating circuit, and a CPU output terminal of the inner core voltage;

wherein, the +5V end is respectively connected with one end of a first capacitor C1, one end of a second capacitor C2, the EN1 end of a chip MP2122, and the IN end of the chip MP2122, the other end of the first capacitor C1 and the other end of the second capacitor C2 are connected and grounded, the SW1 end of the chip MP2122 is connected with one end of a first inductor L1, the other end of the first inductor L1 is respectively connected with one end of a first resistor R1, one end of a third capacitor C3, one end of a fourth capacitor C4 and the core voltage output CPU end, the other end of the third capacitor C3 and the other end of a fourth capacitor C4 are connected and grounded, the other end of the first resistor R1 is respectively connected with one end of a third resistor R3, one end of a fourth resistor R4 and one end of a second resistor R2, the other end of the third resistor R3 is grounded, the other end of the fourth resistor R4 is connected with one end of a sixth resistor R87452, the other end of the sixth resistor R9358 is connected with one end of the fifth resistor R3646 and one end of the fifth capacitor C5, the other end of the fifth resistor R5 is connected with the output AVS end of the voltage regulating circuit, the other end of the fifth capacitor C5 is grounded, and the other end of the second resistor R2 is connected with the FB1 end of the chip MP 2122.

While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that the described embodiments may be modified in various different ways without departing from the spirit and scope of the present invention. Accordingly, the drawings and description are illustrative in nature and should not be construed as limiting the scope of the utility model.

Claims

1. An ESP8266 wireless communication circuit-based image acquisition system is characterized in that: the CMOS image acquisition module comprises an AR0230CS sensor and an SLVS interface, the storage module comprises a 256Mb Flash module and a 4Gb DDR3 module, the AR0230CS sensor is connected with the main control module through the SLVS interface, the Flash module and the DDR3 module are respectively connected with the main control module, and the wireless communication circuit is connected with the main control module through an RS422 interface;

the wireless communication circuit comprises an antenna ANT1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a resistor R1, a resistor R2, an inductor L1, an inductor L2, a chip U1, a chip U2, a chip U3 and a VDD terminal, wherein the antenna ANT1 is respectively connected with one end of the inductor L1 and one end of the capacitor C6, the other end of the inductor L1 is grounded, the other end of the capacitor C6 is respectively connected with one end of the inductor L2 and the pin 2 of the chip U1, the other end of the inductor L2 is grounded, the pin 3 of the chip U1 and the pin 4 of the chip U1 are respectively connected with one end of the capacitor C4, one end of the capacitor C5 and the VDD terminal, the other end of the capacitor C4 and the other end of the capacitor C5 are respectively grounded, the pin 1 of the chip U1 is respectively connected with one end of the pin C3, the pin 30 of the capacitor U3, the pin R3 of the chip U3 and the pin 3 of the chip 3, and the pin 3 of the chip 3 is connected with the chip 3, the other end of the resistor R1 is grounded, the pin 28 of the chip U1 is respectively connected with one end of the capacitor C1 and the pin 1 of the chip U2, the pin 2 of the chip U2 is grounded, the other end of the capacitor C1 is grounded, the pin 4 of the chip U2 is grounded, the pin 3 of the chip U2 is respectively connected with one end of the capacitor C2 and the pin 27 of the chip U1, the other end of the capacitor C2 is grounded, the pin 18 of the chip U1 is connected with the pin 7 of the chip U3, the pin 19 of the chip U1 is connected with the pin 3 of the chip U3, the pin 20 of the chip U1 is connected with the pin 1 of the chip U3, the pin 21 of the chip U1 is connected with the pin 6 of the chip U3 through the resistor R2, the pin 22 of the chip U1 is connected with the pin 2 of the chip U3, the pin 23 of the chip U1 is connected with the pin 5 of the chip U3, and the pin 17 of the chip U1 is respectively connected with the pin 11 and the pin VDD of the chip U1.

2. The image acquisition system based on the ESP8266 wireless communication circuit as claimed in claim 1, wherein: the power supply module comprises an AVS voltage regulating single circuit and an inner core voltage output circuit, wherein the AVS voltage regulating single circuit and the inner core voltage output circuit comprise a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first inductor L1, a chip MP2122, a voltage +5V end, a voltage regulating circuit output AVS end and an inner core voltage output CPU end;

wherein, the +5V end is respectively connected with one end of a first capacitor C1, one end of a second capacitor C2, the EN1 end of a chip MP2122 and the IN end of the chip MP2122, the other end of the first capacitor C1 and the other end of the second capacitor C2 are connected and grounded, the SW1 end of the chip MP2122 is connected with one end of a first inductor L1, the other end of the first inductor L1 is respectively connected with one end of a first resistor R1, one end of a third capacitor C3, one end of a fourth capacitor C4 and the core voltage output CPU end, the other end of the third capacitor C3 and the other end of a fourth capacitor C4 are connected and grounded, the other end of the first resistor R1 is respectively connected with one end of a third resistor R3, one end of a fourth resistor R4 and one end of a second resistor R2, the other end of the third resistor R3 is grounded, the other end of the fourth resistor R4 is connected with one end of a sixth resistor R6, the other end of the sixth resistor R9358 is connected with one end of the fifth capacitor C3646, the other end of the fifth resistor R5 is connected with the output AVS end of the voltage regulating circuit, the other end of the fifth capacitor C5 is grounded, and the other end of the second resistor R2 is connected with the FB1 end of the chip MP 2122.

3. The image acquisition system based on the ESP8266 wireless communication circuit as claimed in claim 1, wherein: the main control module adopts a Hi3516D chip, receives data from the CMOS image acquisition module through the MIPI manager, performs optimization processing and H264 coding compression, and outputs the data to the RS422 wireless communication circuit through the USRT interface.

4. The image acquisition system based on the ESP8266 wireless communication circuit as claimed in claim 1, wherein: the chip model of the Flash module is MX25L 25635F.

5. The image acquisition system based on the ESP8266 wireless communication circuit as claimed in claim 1, wherein: the chip model of the DDR3 module is K4B4G 1646E.