CN113038138A

CN113038138A - Embedded image processing and returning system

Info

Publication number: CN113038138A
Application number: CN202110311493.0A
Authority: CN
Inventors: 曾维; 于森; 李言
Original assignee: Chengdu Univeristy of Technology
Current assignee: Chengdu Univeristy of Technology
Priority date: 2021-04-09
Filing date: 2021-04-09
Publication date: 2021-06-25

Abstract

The application provides a solution for an embedded image processing and returning system aiming at the problem of transferring the load of processing image data to an embedded device. The platform realizes communication with an upper computer by establishing an LwIP protocol stack, adopts ZYNQ software and hardware collaborative design, and performs data parallel accelerated computing processing by a DMA transmission mechanism. The upper computer sends image data to ZYNQ through the gigabit Ethernet for processing, and the image can be displayed on the platform in real time after being processed and can be transmitted back to the upper computer in real time by using the gigabit Ethernet. Therefore, the requirements of large data quantity of high-resolution images, high data transmission rate and the like are met.

Description

Embedded image processing and returning system

Technical Field

The invention belongs to the field of embedded image processing, and particularly relates to a method for performing data interaction processing by a DMA (direct memory access) transmission mechanism and returning a processing result in real time through a gigabit Ethernet.

Background

The Xilinx ZYNQ-7000 fully Programmable SoC single chip is integrated with two parts of a Processing System (PS) and a Programmable Logic (PL). The PS part comprises a high-performance dual-core ARM processor, and the PL part comprises an FPGA logic unit and DSP resources. The PS and the PL in the chip are mutually interconnected by adopting an AXI (advanced eXtensible interface) bus, so that the SoC obtains more excellent performance with smaller area and lower power consumption.

At present, data centers generally adopt an execution scheme of centralized computing, that is, images are collected to the data centers and then are subjected to centralized processing. The following problems are: when the data volume is very large in a short time, if centralized calculation is adopted, a long time is required for completion, and even the risk of downtime may occur, so that the normal service of the data center is seriously affected. Aiming at the problem, the system realizes the image processing and returning system based on ZYNQ by combining idle computing resources of the embedded device, migrates the decomposed computing task to the embedded device, and deploys a plurality of same devices to achieve the purpose of processing larger data volume at the same time. In order to ensure the real-time performance of data transmission, gigabit ethernet is adopted as a transmission solution. The researcher can select the platform to output the processing result to the display with the HDMI interface, and can also select to receive the image processing result transmitted back to the upper computer by the gigabit Ethernet, so that the researcher can conveniently leave a sample for analysis.

Disclosure of Invention

Aiming at the problems, the invention provides an embedded image processing and returning system to solve the problems of long time delay and poor relevance of embedded image processing in the existing method. The specific scheme is as follows:

in a first aspect, the present application provides an embedded image processing and returning method, including:

a system block diagram as shown in figure 1. ZYNQ's processing system PS passes through the MIO interface configuration gigabit Ethernet module, obtains the image data that comes from host computer sending, and ARM end is analyzed out image data and is kept in DDR3 SDRAM. The programmable logic PL part reads data from the memory through a DMA transmission mechanism, the data is processed by an algorithm module in the FPGA, and after the data is processed by an image compression algorithm, the data is interactively written into the memory through an AXI ACP interface and a PS. Through the process, the image data can be read out from the memory and directly displayed on the HDMI display, and can also be transmitted back to the upper computer from the memory through the gigabit Ethernet at the PS end. In the development process of the verification platform, a Block Design hardware circuit is built by using VIVADO, and the SDK completes the realization of the system software function.

In a second aspect, the present application provides an embedded image processing and backhaul system, including:

hardware aspect: the system mainly comprises a ZYNQ chip, a DDR3 memory, an HDMI, a gigabit Ethernet and power management, and is responsible for processing and returning received images in real time and executing logic operation.

In the aspect of algorithm: mainly, image analysis and image parallel processing operation are performed by using the PL terminal of ZYNQ.

Software aspect: mainly researches the realization of LwIP protocol, and the transplantation and interactive system interface design in ZYNQ system.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic diagram of a system framework provided in an example of the present application.

Fig. 2 is a schematic diagram of a simplified system hardware circuit structure provided in the example of the present application.

Fig. 3 is a schematic diagram of a system data flow provided in an example of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The invention provides an embedded image processing and returning system. Fig. 2 is a schematic diagram of a hardware circuit structure of an embedded image processing and returning system according to an embodiment of the present disclosure, and fig. 3 is a schematic diagram of a system data flow according to an embodiment of the present disclosure. The method mainly comprises the following steps:

the Read _ DMA module reads image data in the DDR3 memory through the AXI HP2 interface. And after reading, the read enable outputs a high level signal, and transmits the data to the Write _ DMA module for algorithm processing.

The Write _ DMA module comprises a set of image compression algorithm, and the FPGA is used for parallel processing and pipelining operation to process large-scale high-repeatability operation, so that the operation efficiency of the system is improved. And an AXI ACP interface is adopted to directly write in the memory, so that low-delay connection between a PL terminal and a PS terminal is realized, and the problem of cache consistency in the data transmission process is solved. The AXI ACP interface interacts with the Cache of the processor to inform the Cache that the area is refreshed, repeated refreshing operation is not needed, and Cache invalidation is avoided, so that the performance of the whole application program is improved.

The AXI _ DMA _ RD module reads out the processed data through the AXI HP0 interface for HDMI display, but the HDMI display has a picture tearing phenomenon due to direct reading. This is due to the frame synchronization between the Write _ DMA module writing and the AXI _ DMA _ RD module reading the memory information. In order to eliminate the picture tearing phenomenon, a frame flag signal is introduced. After the Write _ DMA module finishes writing the processed data into the memory, the frame flag signal is pulled low, and the AXI _ DMA _ RD module can read the memory through the AXI HP0 interface; when the frame flag signal is high, which indicates that the process is not completed with writing, the AXI _ DMA _ RD module waits for reading. In this way, the frame synchronization of the two is ensured, thereby avoiding the picture tearing phenomenon.

The HDMI _ trans module encodes, DC balances and parallel-serial converts the RGB data read from the memory by the AXI _ DMA _ RD module so as to output the RGB data to a display with an HDMI interface. Each RGB color channel requires instantiating an Encoder module and a Serializer module. The Encoder module encodes and DC balances 8-bit data to obtain 10-bit minimized data, and improves the reliability of signal transmission. The Serializer module implements the parallel-to-serial conversion function.

Meanwhile, the Conf _ List module provides configuration information for the above modules, including the width and height of the image. The processed image data in the memory can be transmitted back to the upper computer through the PS terminal gigabit Ethernet.

Claims

1. An embedded image processing and returning system, comprising: the device comprises a ZYNQ chip, a DDR3 memory, an HDMI module, a gigabit Ethernet communication module and a peripheral extension module;

the ZYNQ chip is a main data processing chip, and an XC7Z020CLG400-2 chip produced by Xilinx is selected and used for real-time analysis, processing and returning of image data;

the DDR3 memory, the PS end and the PL end of the ZYNQ carry out data interaction processing through a DMA transmission mechanism, and data are cached in the DDR3 memory;

the HDMI module completes the time sequence driving function of the HDMI display module by FPGA programmable logic resources, and adopts the transmission principle of minimizing transmission of differential signals;

the gigabit Ethernet communication module adopts a Marvell 88E1116R chip to provide local area network communication service, is responsible for short-distance related data transmission, and is in data communication with the MAC layer through an RGMII interface;

the peripheral extension module comprises a necessary reset circuit, a power supply module and communication transmission modules such as JTAG, UART and SD memory card modules, and the peripheral extension module mainly aims to ensure the normal operation of the system and also reduce the problems in the debugging link.

2. The system of claim 1, wherein the host computer sends the image data to the system via gigabit ethernet, the system performs real-time parsing and parallel accelerated processing of the image data using FPGA, and the processed data is transmitted back to the host computer via gigabit ethernet or displayed in real time via HDMI of the system.

3. The method as claimed in claim 2, wherein FPGA parallel processing and pipeline operation are used to process large-scale and high-repeatability operations, thereby improving the operational efficiency of the system, an AXI ACP interface is used to directly write in the memory, low-delay connection between the PL terminal and the PS terminal is realized, and the problem of cache consistency in the data transmission process is solved.