CN110418400B

CN110418400B - Symbol power tracking amplification system, operation method thereof and symbol tracking modulator

Info

Publication number: CN110418400B
Application number: CN201910361788.1A
Authority: CN
Inventors: 野见山贵弘; 金东秀; 白志先
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2018-04-30
Filing date: 2019-04-30
Publication date: 2024-03-08
Anticipated expiration: 2039-04-30
Also published as: CN110418400A; JP2019195168A; JP7393876B2

Abstract

The invention relates to a symbol power tracking amplifying system, comprising: a modem for generating data and symbol tracking signals; a symbol tracking modulator including a control circuit, a first voltage supply circuit and a second voltage supply circuit, and a switching circuit, the control circuit generating a first voltage level control signal and a second voltage level control signal in response to the symbol tracking signal, the first voltage supply circuit generating a first output voltage in response to the first voltage level control signal, the second voltage supply circuit generating a second output voltage in response to the second voltage level control signal, and the switching circuit outputting the first output voltage or the second output voltage as a power supply voltage in response to the switching control signal; a radio frequency block generating a radio frequency signal based on the data signal from the modem; and a power amplifier that adjusts a power level of the radio frequency signal based on the supply voltage. A method of operation of the symbol power tracking amplification system and a symbol tracking modulator are also provided.

Description

Symbol power tracking amplification system, operation method thereof and symbol tracking modulator

Cross Reference to Related Applications

The present application claims the benefits of korean patent application No. 10-2018-0050186 filed in the korean intellectual property office at month 4 and us patent application No. 16/233,192 filed in the us patent and trademark office at month 27, at month 12 of 2018, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

The present inventive concept relates to a symbol power tracking (symbol power tracking; SPT) amplification system, and more particularly, to an SPT amplification system supporting an SPT modulation technique and a wireless communication device including the SPT amplification system.

Background

Wireless communication devices, such as smartphones, tablet computers, and internet of things (Internet of Things; IOT) devices, use wideband code division multiple access (wideband code division multiple access; WCDMA) (third generation (3rd generation;3G)), long-term evolution (LTE), and LTE-advanced (fourth generation (4th generation;4G)) technologies for high-speed communications. With the development of communication technology, the transmitted/received signals require peak-to-average power ratios (peak-to-average power ratios; PAPRs) and high bandwidths. Therefore, when the power supply of the power amplifier of the transmitter is connected to the battery, the efficiency of the power amplifier may be lowered. In order to increase the efficiency of the power amplifier at high PAPR and high bandwidth, either average power tracking (average power tracking; APT) techniques or envelope tracking (envelope tracking; ET) modulation techniques may be used.

ET is a pathway of Radio Frequency (RF) amplifier design in which the power supply to an RF power amplifier is continuously regulated to ensure that the amplifier is operated at peak efficiency for each individual power transmitted. When ET modulation techniques are used, efficiency and linearity of the power amplifier may be improved. The chip configured to support the APT technology and the ET modulation technology may be referred to as a Supply Modulator (SM).

Research is being conducted on fifth generation (5 th-generation; 5G) communication technologies. 5G high speed data communication, which is faster than 4G communication technology, requires a suitable power modulation technique.

Disclosure of Invention

According to an exemplary embodiment of the inventive concept, there is provided a Symbol Power Tracking (SPT) amplifying system including: a modem configured to generate a data signal and a symbol tracking signal in response to an external data signal; a symbol tracking modulator comprising a control circuit, a first voltage supply circuit, a second voltage supply circuit, and a switching circuit, wherein the control circuit is configured to generate a first voltage level control signal and a second voltage level control signal in response to a symbol tracking signal, the first voltage supply circuit is configured to generate a first output voltage in response to the first voltage level control signal, the second voltage supply circuit is configured to generate a second output voltage in response to the second voltage level control signal, and the switching circuit is configured to output one of the first output voltage and the second output voltage as a power supply voltage in response to the switching control signal provided from the control circuit; a Radio Frequency (RF) block configured to generate an RF signal based on a data signal from the modem; and a power amplifier configured to adjust a power level of the RF signal based on the supply voltage output from the symbol tracking modulator.

According to an exemplary embodiment of the inventive concept, there is provided a symbol tracking modulator comprising: a control circuit configured to generate a first reference voltage and a second reference voltage in response to the sign-tracking signal; a first voltage supply circuit configured to generate a first output voltage in response to a first reference voltage; a second voltage supply circuit configured to generate a second output voltage in response to a second reference voltage; and a switching circuit configured to output one of the first output voltage and the second output voltage as a power supply voltage in response to a switching control signal supplied from the control circuit.

According to an exemplary embodiment of the inventive concept, there is provided a method of operating an SPT amplifying system, comprising: receiving communication environment information at the modem based on at least one parameter indicative of the communication environment; determining, at the modem, a number of symbols contained in the symbol group unit based on the communication environment information; and controlling the SPT amplification system via the modem based on the symbol group unit.

Drawings

The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

Fig. 1 is a schematic block diagram of a wireless communication device according to an exemplary embodiment of the inventive concept.

Fig. 2A and 2B are diagrams illustrating average power tracking techniques.

Fig. 3A and 3B are diagrams illustrating a Symbol Power Tracking (SPT) modulation technique according to an exemplary embodiment of the inventive concept.

Fig. 4A and 4B are block diagrams of symbol tracking modulators according to exemplary embodiments of the inventive concept.

Fig. 5 is a circuit diagram of a symbol tracking modulator according to an exemplary embodiment of the inventive concept.

Fig. 6 is a schematic diagram of signals for operation of the symbol tracking modulator of fig. 5.

Fig. 7A is a circuit diagram of a symbol tracking modulator capable of fast charge control according to an embodiment, and fig. 7B is a block diagram showing the operation of a fast charge control circuit configured to perform fast charge control.

Fig. 8 is a block diagram of a modem according to an exemplary embodiment of the inventive concept.

Fig. 9 is a diagram for illustrating a method of determining a symbol group unit based on a 5G-based frame structure based on a fifth generation (5G) frame structure.

Fig. 10 is a flowchart of a method of determining a symbol group unit based on a communication environment according to an exemplary embodiment of the inventive concept.

Fig. 11 is a schematic diagram of signals for operation of the symbol tracking modulator of fig. 5.

Fig. 12 is a circuit diagram of a symbol tracking modulator according to an exemplary embodiment of the inventive concept.

Fig. 13 is a schematic diagram of signals for operation of the symbol tracking modulator of fig. 11.

Fig. 14 is a block diagram of a symbol tracking modulator according to an exemplary embodiment of the inventive concept.

Fig. 15 is a circuit diagram of the first single-inductor multiple-output (SIMO) converter of fig. 14.

Fig. 16 and 17 are block diagrams of symbol tracking modulators according to exemplary embodiments of the inventive concept.

Fig. 18 is a block diagram of a wireless communication device according to an exemplary embodiment of the inventive concept.

Fig. 19 is a block diagram of a phased array antenna module according to an embodiment.

Fig. 20A and 20B are diagrams illustrating an SPT operation using SIDO according to an embodiment.

Fig. 21 is a block diagram of a PMIC including two buck converters configured to support a ripple injection hysteresis control function, according to an embodiment.

Description of the reference numerals

100: a wireless communication device/symbol power tracking amplification system;

110: a modem;

112: a baseband processor;

114: a symbol power tracking control module;

114a: a control module based on a 5G frame structure;

114b: a control module based on a communication environment;

130. 200, 300', 300", 400, 420, 500, 600: a symbol tracking modulator;

131. 210, 310', 310", 410, 510, 610: a symbol power tracking control circuit;

133: a voltage supply;

135. 240, 340', 340", 440, 540, 640: a switching circuit;

150: a radio frequency block;

170: a power amplifier;

212. 214: a digital-to-analog conversion circuit;

220: a first voltage supply circuit;

230: a second voltage supply circuit;

320. 320', 320": a first DC-DC converter;

322. 322', 322": a first conversion control circuit;

324. 324', 324": a first comparator;

330. 330', 330": a second DC-DC converter;

332. 332', 332": a second switching control circuit;

334. 334', 334": a second comparator;

350': a fast charge control circuit;

420: a first single-inductor multiple-output converter;

422: a single-inductor multi-output conversion control circuit;

424_1 to 424_n: a comparator;

426_1 to 426—n: a voltage generating circuit;

430: a second single-inductor multiple-output converter;

520: a DC-DC converter;

530: a linear amplifier;

620_1 to 620_m: a voltage supply circuit;

1000: a wireless communication device;

1010: an application specific integrated circuit;

1030: a special instruction set processor;

1050: a memory;

1070: a main processor;

1090: a main memory;

2000: a phased array antenna module;

2100. 3000: a power management integrated circuit;

2110. 2120: a DC-DC converter;

2130:1.1 volt linear leakage linear regulator;

2140. 3300: auxiliary linear leakage;

2150: a fast charge/discharge current source;

2160: a reference voltage generator;

2170: a controller;

2172: mobile industry processor interface slave;

2174: a main controller;

2175: a fast charge controller;

2176: a fixed frequency controller;

2178: an internal clock source;

2180: a multiplexer;

2200: a phased array transceiver;

2210_a, 2210_b: a transceiver circuit;

2220: a microcontroller unit;

2230: a mobile industry processor interface master device;

2240: internal linear leakage;

3100、BK _SPT : a first buck converter;

3200、BK _SIDO : a second buck converter;

ants: an antenna;

BUF: a buffer;

C ₁ ～C _n 、C _1.1V 、C _1.3V 、C _ac1 、C _ac2 、C _f1 、C _f2 、C _r1 、C _r2 、C _L1 、C _L2 : a capacitor;

C _a 、C” _a 、C _b 、C” _b : a capacitor element;

Cap.Swap: a switch control signal;

CLK: a clock signal;

COMP: a comparator;

C _SPT : an output capacitor element/output capacitor;

DAC sel: a digital-to-analog converter selection signal;

DAC1: a first digital-to-analog converter;

DAC2: a second digital-to-analog converter;

DATA: data;

DN: a second fast charge switch control signal;

DPC ₁ 、DPC ₂ 、SW _L1 、SW _L2 、SW _SD1 、SW _SD2 、SW _SIDO : a switch;

enables: an enable signal;

and (B): a feedback block;

FFC1: a first fixed frequency control signal;

FFC2: a second fixed frequency control signal;

FSS _1.3V 、FSS _C1 、FSS _C2 : a feedback selection switch;

ft_a, ft_b, ft_c, ft_d: a filter;

GND: grounding;

if_ckt_a, if_ckt_b: an intermediate frequency circuit;

interface_ CKTa, interface _CKTb: an interface circuit;

IS ₁ : a first current source;

IS ₂ : a second current source;

ITV1: a first subframe portion;

ITV2: a second subframe portion;

ITV3: a third subframe portion;

l: an inductor;

L _a 、L _b : an inductor element;

LNA: a low noise amplifier;

L _SIDO : a single inductance dual output inductor;

L _SPT : a symbol power tracking inductor;

LV ₁ : a first level;

LV ₂ : a second level;

LV ₃ : a third level;

mix_a, mix_b, mix_c, mix_d: a mixer;

M _N1 、M _N2 、M _P1 、M _P2 、M _P3 : a transistor;

mode sel. A mode selection signal;

N _a 、N _a1 ～N _an 、N _b 、N _OUT : an output node;

PA: a power amplifier;

PS: a phase shifter;

PWL _S1 、PWL _S2 、PWL _S3 : a signal;

rf_ckts: a radio frequency circuit;

R _f1a 、R _f1b 、R _f1c 、R _f1d 、R _f2a 、R _f2b 、R _f2c 、R _f2d : a resistor;

RF _IN : a radio frequency signal;

RF _OUT : a radio frequency output signal;

R _r1 、R _r2 : a variable resistor;

S_Sb1: a first symbol;

s_sb2: a second symbol;

s100, S120, S140: a step of;

sb_0: a first symbol portion/symbol;

sb_1: a second symbol portion/symbol;

sb_2: a third symbol portion/symbol;

sb_3: a fourth symbol portion/symbol;

sb_4, sb_5, sb_6, sb_7: a symbol;

sbg_0: a first symbol group portion;

sbg_1: a second symbol group portion;

sbg_2: a third symbol group portion;

sbg_3: a fourth symbol group portion;

SP1: a first signal path;

SP2: a second signal path;

spt_cs1: a first control signal;

spt_cs2: a second control signal;

SW_CS、SW_CS _a1 、SW_CS _a2 、SW_CS _b1 、SW_CS _b2 : a switch control signal;

SW_CS _a : a first switch control signal;

SW_CS _b : a second switch control signal;

SW _a 、SW _a1 ～SW _an 、SW _b 、SW _b1 、SW _b2 、SW _c1 、SW _c2 、SW _c3 、SW _c4 : a switching element;

swap_en: an enable signal;

SW _DN : a second fast charge control switch;

SW _SIDO : a single inductance dual output switch;

SW _UP : a first fast charge control switch;

t0, t1, t2, t3, t4, t5, t6, t7, t8, ta, t 'a, t "a, tb, t' b, t" b, tc, t 'c, t "c, td, t'd, t" d: a time point;

tick: a timing signal;

Trigger_spt, time: a trigger signal;

TRX Swa, TRX SWb: a transceiver switch;

ts_spt: a symbol tracking signal;

ts_spt1: a first symbol tracking signal;

ts_spt2: a second symbol tracking signal;

TX: a data signal;

UL Symbol 1: a first uplink symbol;

UL Symbol 2: a second uplink symbol;

UL Symbol 3: a third uplink symbol;

UP: a first fast charge switch control signal;

V _APT 、V _OUT1 ～V _OUTm 、V _SPT 、V _o1.3V : a power supply voltage;

V _C1 、V _C2 : a load capacitor voltage;

V _DD : a supply voltage;

VL_CS _a : a first voltage-level control signal;

VL_CS _b : a second voltage-level control signal;

V _OUTa : a first power supply voltage;

V _OUTa1 ～V _OUTan : a feedback signal;

V _OUTb : a second power supply voltage;

V _REF1 ～V _REFn : reference toA voltage;

V _REFa : a first reference voltage;

V _REFb : a second reference voltage;

vsel: a supply voltage is selected.

Detailed Description

Fig. 1 is a schematic block diagram of a wireless communication device 100 according to an exemplary embodiment of the inventive concept.

Referring to fig. 1, a wireless communication device 100 may include a modem 110, a symbol tracking modulator 130, a Radio Frequency (RF) block 150, and a power amplifier (or PA) 170. The configuration including the symbol tracking modulator 130 and the power amplifier 170 may be configured to amplify the RF signal RF _IN And outputs an RF output signal RF _OUT Symbol Power Tracking (SPT) amplification system. The modem 110 may process baseband signals transmitted to the wireless communication device 100 and baseband signals received from the wireless communication device 100. For example, modem 110 may generate a digital data signal and a digital symbol tracking signal corresponding to the digital data signal in response to an external data signal. In this case, the digital symbol tracking signal may be generated based on the amplitude (or amplitude component) of the digital data signal. Modem 110 may digital-to-analog convert (DAC) the digital data signal and the digital symbol tracking signal and provide a data signal TX and a symbol tracking signal ts_spt to RF block 150 and symbol tracking modulator 130, respectively. However, the symbol tracking signal ts_spt provided by the modem 110 to the symbol tracking modulator 130 is not limited to an analog signal and may be a digital signal.

The data signal TX may correspond to a predetermined frame and include a plurality of symbols. The frames will be described in more detail below with reference to fig. 8. The modem 110 according to an exemplary embodiment of the inventive concept may divide the data signal TX into a plurality of symbol groups based on symbol group units including at least one symbol, and generate a symbol tracking signal ts_spt based on the amplitude (or amplitude component) of the symbol included in each of the symbol groups. For example, when the symbol group unit includes only one symbol, the symbol group unit may be a symbol unit. Modem The generator 110 may generate a symbol tracking signal ts_spt based on the amplitude of each of the symbols of the data signal TX. The symbol tracking modulator 130 may be used to track the RF signal RF for each symbol portion based on the symbol tracking signal TS_SPT _IN Is provided to the power amplifier 170. In addition, the modem 110 may provide the Trigger signal trigger_spt corresponding to the symbol group unit to the symbol tracking modulator 130. The Trigger signal trigger_spt may be used to inform the symbol tracking modulator 130 of the point in time when the new symbol group portion begins. For example, when the symbol group unit includes only one symbol, the Trigger signal trigger_spt may inform the symbol tracking modulator 130 of a point in time at which each symbol of the data signal TX starts.

Modem 110 may variously determine (or change) the number of symbols included in the symbol group unit and generate a symbol tracking signal ts_spt and a Trigger signal trigger_spt corresponding to the symbol group unit. A method of determining the symbol group unit of the modem 110 will be described below with reference to fig. 7 to 9.

The symbol tracking signal ts_spt and Trigger signal trigger_spt may be implemented differently to control the symbol tracking modulator 130 to be used for tracking the RF signal RF for each symbol group portion corresponding to a symbol group unit _IN Is provided to the power amplifier 170. The symbol tracking modulator 130 may perform an SPT operation based on the symbol tracking signal ts_spt and the Trigger signal trigger_spt. For example, the SPT operation may modulate the voltage level of the select power supply voltage Vsel based on the amplitude of the maximum symbol of the data signal TX for each symbol group corresponding to the symbol group unit.

The symbol tracking modulator 130 may modulate the voltage level of the select power supply voltage Vsel provided to the power amplifier 170 based on the symbol tracking signal ts_spt. For example, the symbol tracking modulator 130 may include an SPT control circuit 131, a voltage supply 133, and a switching circuit 135. In an exemplary embodiment of the inventive concept, the SPT control circuit 131 may provide the first control signal spt_cs1 and the second control signal spt_cs2 to the voltage supplier 133 and the switching circuit 135, respectively, based on the symbol tracking signal ts_spt and the Trigger signal trigger_spt received from the modem 110.

The voltage supply 133 may use the supply voltage V _DD (or battery voltage) at least two power supply voltages are generated based on the first control signal spt_cs1. The voltage level of each of the power supply voltages may be changed in response to the first control signal spt_cs1, and the voltage level of the corresponding power supply voltage may be changed in different symbol group portions. The voltage supply 133 may include a plurality of output terminals configured to output power supply voltages, respectively, and the output terminals of the voltage supply 133 may be connected to the switching circuit 135.

The switching circuit 135 may include a plurality of switching elements, and selects any one of the power supply voltages generated by the voltage supply 133 for each symbol group portion corresponding to the symbol group unit based on the second control signal spt_cs2. For example, when the symbol group unit includes only one symbol, the switching circuit 135 may perform a switching operation of selecting any one of the power supply voltages for each symbol portion. The voltage supplier 133 may change a voltage level of the remaining power supply voltages except the power supply voltage selected by the switching circuit 135 based on the first control signal spt_cs1.

The RF block 150 may up-convert the data signal TX and generate an RF signal RF _IN . The power amplifier 170 may be driven and amplify the RF signal RF by selecting the power supply voltage Vsel _IN Generating an RF output signal RF _OUT . Can RF output signal RF _OUT Is provided to the antenna. As described above, the select supply voltage Vsel may have the data signal TX or the RF signal RF in the cells for tracking the symbol group _IN Voltage-level transition mode of (c).

The symbol tracking modulator 130 according to an exemplary embodiment of the inventive concept may perform an SPT operation and perform an amplifying operation of the power amplifier 170 to minimize an RF signal RF _IN Is a deformation of the signal pattern of (a). In other words, the power amplifier 170 may output the direct reflected RF signal RF using the selected supply voltage Vsel _IN RF output signal RF of the signal pattern of (a) _OUT Thereby improving communication performance between the wireless communication apparatus 100 and the base station.

Fig. 2A and 2B are diagrams illustrating average power tracking techniques. Hereinafter, it will be assumed that a frame of a data signal of a Long Term Evolution (LTE) system includes ten subframes, one subframe includes two slots, and one slot includes seven symbols.

Referring to fig. 2A, the average power tracking technique may modulate the supply voltage V based on the highest amplitude (or amplitude) of the data signal for each subframe portion _APT Is set in the above-described voltage level. FIG. 2B depicts RF signals RF corresponding to each of the first, second, and third sub-frame portions ITV1, ITV2, ITV3 of FIG. 2A in accordance with the average power tracking technique _IN Related supply voltage V _APT . Referring to FIG. 2B, the RF signal RF in the second subframe section ITV2 _IN May be combined with the RF signal RF in the third subframe section ITV3 _IN Has the same amplitude and corresponds to the supply voltage V of the second sub-frame part ITV2 _APT May be different from the supply voltage V corresponding to the third sub-frame portion ITV3 _APT Is set to a level of (2). Since the amplification gain of the actual power amplifier can be based on the supply voltage V _APT The amplitude of the signal output by the power amplifier after the first symbol s_sb1 is amplified may be different from the amplitude of the signal output by the power amplifier after the second symbol s_sb2 is amplified. In other words, when the power supply voltages V having different levels are to be supplied _APT When provided to a power amplifier, even the same symbol may be amplified with different amplification gains to produce different results. Therefore, communication reliability may be reduced. In particular, in the fifth generation (5G) system, communication of symbol units may be a precondition for high-speed data communication in a high-frequency bandwidth. Thus, a power tracking modulation technique with high data accuracy may be used instead of an average power tracking modulation technique. As depicted in fig. 2A, the subframe may be 1 millisecond, the slot may be 0.5 millisecond and the symbol may be 71 microseconds. In addition, the symbol may include a cyclic prefix.

Fig. 3A and 3B are diagrams illustrating SPT modulation techniques according to exemplary embodiments of the inventive concept.

Referring to fig. 3A, the modem 110 and symbol tracking modulator 130 of fig. 1 may be used to implement the general inventive conceptThe SPT modulation technique of the exemplary embodiment of the concept, and the supply voltage V may be modulated based on the amplitude (or amplitude) of the data signal of each symbol portion by using the SPT modulation technique _SPT Is set in the above-described voltage level. The supply voltage V may be applied in the Cyclic Prefix (CP) portion of the symbol _SPT Is a level transition of (a). However, the embodiment depicted in FIG. 3A may relate to the case where the symbol group unit includes only one symbol. When the symbol group unit includes a plurality of symbols, the power supply voltage V may be modulated based on the highest amplitude of the data signal of each symbol group portion including the plurality of symbols _SPT Is set in the above-described voltage level.

Referring to FIG. 3B, the symbol tracking modulator 130 of FIG. 1 may be used to track RF signals RF in symbol cells _IN Is set to the power supply voltage V of _SPT Is provided to the power amplifier 170. Accordingly, the SPT amplification system including the symbol tracking modulator 130 and the power amplifier 170 according to the exemplary embodiment of the inventive concept can accurately amplify the RF signal RF in the unit of the symbol unit _IN And outputs an amplified signal. Thus, the performance of communication with the base station can be improved.

Fig. 4A and 4B are block diagrams of a symbol tracking modulator 200 according to exemplary embodiments of the inventive concept.

Referring to fig. 4A, the symbol tracking modulator 200 may include an SPT control circuit 210, a first voltage supply circuit 220, a second voltage supply circuit 230, and a switching circuit 240. The SPT control circuit 210 may receive a symbol tracking signal ts_spt and a Trigger signal trigger_spt from the modem. The SPT control circuit 210 may generate a first voltage-level control signal VL_CS based on the symbol tracking signal TS_SPT _a And a second voltage-level control signal VL_CS _b And the first voltage-level control signal VL_CS _a And a second voltage-level control signal VL_CS _b Are provided to the first voltage supply circuit 220 and the second voltage supply circuit 230, respectively. In addition, the SPT control circuit 210 may generate the switch control signal sw_cs based on the Trigger signal trigger_spt and provide the switch control signal sw_cs to the switch circuit 240. The SPT control circuit 210 may further include a timer. When the SPT control circuit 210 receives the Trigger signal trigger_SPT once, it modulates When the demodulator receives additional information about the number of symbols included in the symbol group unit, the SPT control circuit 210 may count the duration corresponding to the symbol group unit using a timer and periodically generate the switch control signal sw_cs based on the count result.

The first voltage supply circuit 220 may be based on a first voltage-level control signal VL_CS _a Generating a first power supply voltage V _OUTa And the second voltage supply circuit 230 may be based on the second voltage-level control signal vl_cs _b Generating a second power supply voltage V _OUTb . The switching circuit 240 may alternately select the first voltage supply circuit 220 and the second voltage supply circuit 230 of each symbol group portion based on the switching control signal sw_cs and connect the selected voltage supply circuits to the power amplifier PA. The first voltage supply circuit 220 may be based on a first voltage-level control signal VL_CS in the symbol set portion in which the first voltage supply circuit 220 is selected _a To change the first power supply voltage V _OUTa Is set to a level of (2). In addition, the second voltage supply circuit 230 may be based on the second voltage-level control signal VL_CS in the symbol set portion in which the second voltage supply circuit 230 is selected _b To change the second power supply voltage V _OUTb Is set to a level of (2). By using the above method, the switching circuit 240 can supply the selected power supply voltage Vsel generated by the SPT modulation to the power amplifier PA.

Referring to fig. 4B, the symbol tracking signal ts_spt of fig. 4A may include a first symbol tracking signal ts_spt1 and a second symbol tracking signal ts_spt2. The first symbol tracking signal TS_SPT1 can control the first power voltage V _OUTa And the second symbol tracking signal TS_SPT2 can control the second power voltage V _OUTb Is set to a level of (2). In an exemplary embodiment of the present inventive concept, the SPT control circuit 210 may include a DAC circuit 212 and a DAC circuit 214. The first and second symbol tracking signals ts_spt1 and ts_spt2 may be converted into the first voltage-level control signal vl_cs by the DAC circuit 212 and the DAC circuit 214, respectively _a And a second voltage-level control signal VL_CS _b . However, in an exemplary embodiment of the inventive concept, when the first symbol tracking signal TS_SPT1 and the second symbol tracking signal TS\uWhen SPT2 is an analog signal, the first and second symbol tracking signals TS_SPT1 and TS_SPT2 may be respectively the same as the first voltage-level control signal VL_CS _a And a second voltage-level control signal VL_CS _b The same signal.

The SPT control circuit 210 may receive the first symbol tracking signal ts_spt1 via the first signal path SP1 and route the first symbol tracking signal ts_spt1 to the first voltage supply circuit 220. In addition, the SPT control circuit 210 may receive the second symbol tracking signal ts_spt2 via the second signal path SP2 and route the second symbol tracking signal ts_spt2 to the second voltage supply circuit 230.

The relationship between the first symbol tracking signal ts_spt1 and the second symbol tracking signal ts_spt2 implementing the SPT modulation technique will now be described. The point in time when the level of the first symbol tracking signal ts_spt1 changes may be different from the point in time when the level of the second symbol tracking signal ts_spt2 changes. In addition, a time interval between a point of time at which the level of the first symbol tracking signal ts_spt1 changes and a point of time at which the level of the second symbol tracking signal ts_spt2 changes may correspond to a length of the symbol group unit. In other words, the modem may provide a plurality of symbol tracking signals (e.g., symbol tracking signal ts_spt1 and symbol tracking signal ts_spt2) to the symbol tracking modulator 200 via a plurality of signal paths (e.g., signal path SP1 and signal path SP 2).

Fig. 5 is a circuit diagram of a symbol tracking modulator 300 according to an exemplary embodiment of the inventive concept.

Referring to fig. 5, the symbol tracking modulator 300 may include an SPT control circuit 310, a first Direct Current (DC) -DC converter 320, a second DC-DC converter 330, a switching circuit 340, and an output capacitor element C _SPT . The first DC-DC converter 320 and the second DC-DC converter 330 may support a dynamic voltage scaling (dynamic voltage scaling; DVS) function. The first DC-DC converter 320 may include a first conversion control circuit 322, a first comparator 324, a plurality of switching elements (e.g., switching element SW _c1 And a switching element SW _c2 ) Inductor element L _a Capacitor element C _a . The second DC-DC converter 330 may include a second converterControl circuit 332, second comparator 334, and multiple switching elements (e.g., switching element SW _c3 And a switching element SW _c4 ) Inductor element L _b Capacitor element C _b 。

The SPT control circuit 310 can respectively divide the first reference voltage V based on the symbol tracking signal TS_SPT _REFa And a second reference voltage V _REFb Is provided to the first comparator 324 and the second comparator 334. The first comparator 324 may receive the output node N of the first DC-DC converter 320 _a Is set to the first supply voltage V _OUTa Comparing the first reference voltage V _REFa With a first power supply voltage V _OUTa And provides the comparison result to the first conversion control circuit 322. The first conversion control circuit 322 can control the switching element SW based on the comparison result _c1 And a switching element SW _c2 And the first DC-DC converter 320 can generate a voltage corresponding to the first reference voltage V _REFa Is set to the first supply voltage V _OUTa . The second comparator 334 may receive the output node N of the second DC-DC converter 330 _b Is a second power supply voltage V of (2) _OUTb Comparing the second reference voltage V _REFb And a second power supply voltage V _OUTb And supplies the comparison result to the second conversion control circuit 332. The second conversion control circuit 332 can control the pair of switching elements SW based on the comparison result _c3 And a switching element SW _c4 And the second DC-DC converter 330 can generate a voltage corresponding to the second reference voltage V _REFb Is a second power supply voltage V of (2) _OUTb 。

The switching circuit 340 may include a plurality of switching elements (e.g., switching element SW _a And a switching element SW _b ). First switching element SW of switching circuit 340 _a Can be connected between the first DC-DC converter 320 and the output node N of the symbol tracking modulator 300 _OUT (or output terminals). Second switching element SW of switching circuit 340 _b Can be connected between the second DC-DC converter 330 and the output node N of the symbol tracking modulator 300 _OUT Between them. The SPT control circuit 310 may generate a first switch control signal SW_CS based on the Trigger signal trigger_SPT _a And a second switch control signal SW_CS _b And control the first switchNumber sw_cs _a And a second switch control signal SW_CS _b Respectively to the first switching elements SW _a And a second switching element SW _b . The switch circuit 340 may be based on the switch control signal SW_CS _a And a switch control signal SW_CS _b Alternately selecting a first supply voltage V _OUTa And a second power supply voltage V _OUTb And via the output node N _OUT The select power supply voltage Vsel is supplied to the power amplifier PA. Output capacitor element C _SPT Connectable to an output node N _OUT To prevent abrupt voltage blanking during switching operations using switching circuit 340.

Fig. 6 is a diagram of signals for operation of the symbol tracking modulator 300 of fig. 5. Hereinafter, it will be assumed that the symbol group unit contains only one symbol. Ground is represented by GND in the figure.

Referring to fig. 5 and 6, in the first symbol portion sb_0 (or the portion between the time point "t0" and the time point "t 1"), the SPT control circuit 310 may maintain the first reference voltage V at a constant level based on the symbol tracking signal ts_spt _REFa Is supplied to the first DC-DC converter 320 to have the first switch control signal sw_cs of a high level based on the Trigger signal trigger_spt received at the time point "t0 _a Is provided to the first switching element SW _a And the first power supply voltage V to be generated by the first DC-DC converter 320 _OUTa As an alternative to the supply voltage V _SPT Is provided to the power amplifier PA. In the first symbol portion SB_0, the SPT control circuit 310 may change the level of the second reference voltage V at the time point "ta" based on the symbol tracking signal TS_SPT _REFb Is supplied to the second DC-DC converter 330 to apply the second switching control signal sw_cs having a low level based on the Trigger signal trigger_spt received at the time point "t0 _b Is provided to the second switching element SW _b And changes the second power supply voltage V generated by the second DC-DC converter 330 _OUTb Is set to a level of (2). For example, the second supply voltage V may be increased _OUTb Is set to a level of (2).

In the second symbol portion SB_1 (or the portion between the time point "t1" and the time point "t 2"), the SPT control circuit 310 may be based onThe second reference voltage V is maintained at a constant level in the symbol tracking signal TS_SPT _REFb Is supplied to the second DC-DC converter 330 to apply the second switching control signal sw_cs having a high level based on the Trigger signal trigger_spt received at the time point "t1 _b Is provided to the second switching element SW _b And a second power supply voltage V to be generated by the second DC-DC converter 330 _OUTb As an alternative to the supply voltage V _SPT Is provided to the power amplifier PA. In the second symbol portion SB_1, the SPT control circuit 310 may change the level of the first reference voltage V at the time point "tb" based on the symbol tracking signal TS_SPT _REFa Is supplied to the first DC-DC converter 320 to have the first switch control signal sw_cs of a low level based on the Trigger signal trigger_spt received at the time point "t1 _a Is provided to the first switching element SW _a And changes the first power voltage V generated by the first DC-DC converter 320 _OUTa Is set to a level of (2). For example, the first supply voltage V may be increased _OUTa Is set to a level of (2).

In the third symbol portion SB_2 (or the portion between the time point "t2" and the time point "t 3"), the SPT control circuit 310 may maintain the first reference voltage V at a constant level based on the symbol tracking signal TS_SPT _REFa Is supplied to the first DC-DC converter 320 to have the first switch control signal sw_cs of a high level based on the Trigger signal trigger_spt received at the time point "t2 _a Is provided to the first switching element SW _a And the first power supply voltage V to be generated by the first DC-DC converter 320 _OUTa As an alternative to the supply voltage V _SPT Is provided to the power amplifier PA. In the third symbol portion SB_2, the SPT control circuit 310 may change the level of the second reference voltage V at the time point "tc" based on the symbol tracking signal TS_SPT _REFb Is supplied to the second DC-DC converter 330 to apply the second switching control signal sw_cs having a low level based on the Trigger signal trigger_spt received at the time point "t2 _b Is provided to the second switching element SW _b And changes the second power supply voltage V generated by the second DC-DC converter 330 _OUTb Is set to a level of (2). For example, the second supply voltage V may be increased _OUTb Level of (2)。

In the fourth symbol portion SB_3 (or the portion between the time point "t3" and the time point "t 4"), the SPT control circuit 310 may maintain the second reference voltage V at a constant level based on the symbol tracking signal TS_SPT _REFb Is supplied to the second DC-DC converter 330 to apply the second switching control signal sw_cs having a high level based on the Trigger signal trigger_spt received at the time point "t3 _b Is provided to the second switching element SW _b And a second power supply voltage V to be generated by the second DC-DC converter 330 _OUTb As an alternative to the supply voltage V _SPT Is provided to the power amplifier PA. In the fourth symbol portion SB_3, the SPT control circuit 310 may change the level of the first reference voltage V at the time point "td" based on the symbol tracking signal TS_SPT _REFa Is supplied to the first DC-DC converter 320 to have the first switch control signal sw_cs of a low level based on the Trigger signal trigger_spt received at the time point "t3 _a Is provided to the first switching element SW _a And changes the first power voltage V generated by the first DC-DC converter 320 _OUTa Is set to a level of (2). For example, the first supply voltage V may be reduced _OUTa Is set to a level of (2).

In the above method, the symbol tracking modulator 300 may alternatively select the first supply voltage V _OUTa And a second power supply voltage V _OUTb Select supply voltage V as part of each symbol _SPT And pre-changes the voltage level of the unselected power supply voltage for SPT modulation operation.

Fig. 7A is a circuit diagram of a symbol tracking modulator 300 'capable of fast charge control according to an embodiment, and fig. 7B is a block diagram illustrating the operation of a fast charge control circuit 350' configured to perform fast charge control.

Referring to fig. 7A, the symbol tracking modulator 300' may further include a first current source IS compared to the symbol tracking modulator 300 of fig. 5 ₁ A second current source IS ₂ First quick charge control switch SW _UP Second quick charge control switch SW _DN . In an embodiment, a first current source IS ₁ Can be switched on the first switching element SW _a Or a second switchElement SW _b Previously to output node N _OUT Fast charging is performed such that the output node N _OUT Voltage V of (2) _SPT The output node N near the first DC-DC converter 320' may be reached in advance _a Is set to the first supply voltage V _OUTa Or the output node N of the second DC-DC converter 330 _b Is a second power supply voltage V of (2) _OUTb . Second current source IS ₂ Can be switched on the first switching element SW _a Or a second switching element SW _b Previously to output node N _OUT Fast discharging is performed so that the output node N _OUT Voltage V of (2) _SPT The output node N near the first DC-DC converter 320' may be reached in advance _a Is set to the first supply voltage V _OUTa Or the output node N of the second DC-DC converter 330 _b Is a second power supply voltage V of (2) _OUTb . The first current source IS can be used ₁ And a second current source IS ₂ To output node N _OUT The control of charging and discharging is defined as a quick charge control. That IS, due to the first current source IS ₁ A second current source IS ₂ First quick charge control switch SW _UP Second quick charge control switch SW _DN Is configured of output node N _OUT Voltage V of (2) _SPT Can reach the first power voltage V quickly _OUTa Or a second power supply voltage V _OUTb . Therefore, the output node N can be reduced _OUT Voltage V of (2) _SPT The time it takes to transition to the target voltage. Further, when the first switching element SW is connected _a And a second switching element SW _b In this case, the output node N is prevented _OUT With other output nodes N _a And output node N _b A large voltage difference between them.

Referring to fig. 7B, the symbol tracking modulator 300 'may further include a fast charge control circuit 350' as compared to the symbol tracking modulator 300 of fig. 5. The fast charge control circuit 350' may be based on a target voltage (e.g., a first supply voltage V in response to a trigger signal dock for triggering a transition of the sign power _OUTa Or a second power supply voltage V _OUTb ) And output node N _OUT Voltage V of (2) _SPT Differences betweenTo generate either one of the first and second quick charge switch control signals UP and DN and to output the generated signal to the first quick charge control switch SW _UP And a second quick charge control switch SW _DN Any one of them. In addition, the fast charge control circuit 350' may detect the output node N _OUT Voltage V of (2) _SPT Whether it has been charged or discharged to near the target voltage. When the output node N is detected _OUT Voltage V of (2) _SPT When approaching the target voltage, the fast charge control circuit 350' may provide the enable signal swap_en to the SPT control circuit 310', so that the SPT control circuit 310' may generate a signal for controlling the first switching element SW _a Or a second switching element SW _b Switch control signal sw_cs for on/off operation of (a) _a And a switch control signal SW_CS _b 。

The configuration for the quick charge control depicted in fig. 7A and 7B is merely an example embodiment, and the inventive concept is not limited thereto. Voltage V useful for tracking rapid transitions of symbol power while preventing the occurrence of rush current _SPT May be applied to the embodiments. Fig. 8 is a block diagram of a modem 110 according to an exemplary embodiment of the inventive concept. To control the SPT control circuit 131 depicted in FIG. 1, the modem 110 may be implemented as depicted in FIG. 8.

Referring to fig. 8, the modem 110 may include a baseband processor 112 and an SPT control module 114. The SPT control module 114 may be software executed by the baseband processor 112 and stored in a predetermined memory area of the modem 110. Furthermore, the SPT control module 114 may be implemented as hardware and control the SPT modulation operation independently of the baseband processor 112.

In an exemplary embodiment of the inventive concept, the SPT control module 114 may include a 5G frame structure based control module 114a and a communication environment based control module 114b. Baseband processor 112 may execute control module 114a based on the 5G frame structure, determine (or change) the number of symbols included in the symbol group unit based on the frame structure of the 5G system, and generate a symbol tracking signal and a trigger signal based on the determined symbol group unit. In addition, the baseband processor 112 may execute the communication environment-based control module 114b, determine (or change) the number of symbols included in the symbol group unit based on at least one of the parameters indicating the communication environment between the base station and the wireless communication device, and generate the symbol tracking signal and the trigger signal based on the determined symbol group unit. In other words, the baseband processor 112 may generate the symbol tracking signal ts_spt and the Trigger signal trigger_spt using the 5G frame structure-based control module 114a or the communication environment-based control module 114b.

However, the inventive concept is not so limited. For example, baseband processor 112 may change symbol group elements differently periodically based on various parameters.

Fig. 9 is a diagram of a 5G-based frame structure that may be used to illustrate a method of determining symbol group units based on a 5G-based frame structure. Fig. 10 is a flowchart of a method of determining a symbol group unit based on a communication environment according to an exemplary embodiment of the inventive concept.

Referring to fig. 9, one subframe (or radio frame) may include a plurality of slots. For example, one subframe may include 10 slots (slot 0 through slot 9). One slot may contain multiple symbols. For example, one slot may include seven symbols. For example, slot 0 may include seven symbols 0 through 6. However, the inventive concept is not so limited. For example, one slot may include a different number of symbols according to a unit time interval between subcarriers of 5G wireless communication (in other words, a subcarrier interval size). In addition, at least one symbol included in one slot may be divided into micro slots, and the micro slots may be one unit of 5G-based low-latency communication. For example, a micro slot may include two symbols 0 and 1 as depicted in fig. 8. The baseband processor 112 of fig. 8 may determine (or change) symbol group elements based on the number of symbols contained in the minislot.

Referring to fig. 10, the baseband processor 112 of fig. 8 may obtain communication environment information based on at least one of parameters indicating a communication environment (step S100). In exemplary embodiments of the present inventive concept, the parameter indicating the communication environment may indicate a channel state between the base station and the wireless communication device. For example, a parameter indicative of the communication environment may be associated with a channel quality indication. Further, the baseband processor 112 may obtain communication environment information based on system information and control information received from the base station. The baseband processor 112 may determine (or change) the number of symbols included in the symbol group unit based on the obtained communication environment information (step S120). The baseband processor 112 may control the SPT modulation operation based on the determined symbol group unit (step S140).

Fig. 11 is a flow chart of signals for operation of the symbol tracking modulator 300 of fig. 5. Unlike in fig. 6, it is assumed that the symbol group unit includes two symbols in fig. 11. For example, the first symbol set portion SBG_0 includes a symbol SB_0 and a symbol SB_1, the second symbol set portion SBG_1 includes a symbol SB_2 and a symbol SB_3, the third symbol set portion SBG_2 includes a symbol SB_4 and a symbol SB_5, and the fourth symbol set portion SBG_3 includes a symbol SB_6 and a symbol SB_7.

Referring to fig. 5 and 11, in the first symbol group portion sbg_0 (a portion between the time point "t0" and the time point "t 2"), the SPT control circuit 310 may maintain the first reference voltage V at a constant level based on the symbol tracking signal ts_spt _REFa Is supplied to the first DC-DC converter 320 to have the first switch control signal sw_cs of a high level based on the Trigger signal trigger_spt received at the time point "t0 _a Is provided to the first switching element SW _a And the first power supply voltage V to be generated by the first DC-DC converter 320 _OUTa As an alternative to the supply voltage V _SPT Is provided to the power amplifier PA. In the first symbol group portion SBG_0, the SPT control circuit 310 may change the level of the second reference voltage V at the time point "t' a" based on the symbol tracking signal TS_SPT _REFb Is supplied to the second DC-DC converter 330 to apply the second switching control signal sw_cs having a low level based on the Trigger signal trigger_spt received at the time point "t0 _b Is provided to the second switching element SW _b And changes the second power supply voltage V generated by the second DC-DC converter 330 _OUTb Is set to a level of (2). For example, the second supply voltage V may be increased _OUTb Is set to a level of (2).

In the second symbol group portion SBG_1 (time point "t2"Part between time point "t 4"), the SPT control circuit 310 may maintain the second reference voltage V at a constant level based on the symbol tracking signal ts_spt _REFb Is supplied to the second DC-DC converter 330 to apply the second switching control signal sw_cs having a high level based on the Trigger signal trigger_spt received at the time point "t2 _b Is provided to the second switching element SW _b And a second power supply voltage V to be generated by the second DC-DC converter 330 _OUTb As an alternative to the supply voltage V _SPT Is provided to the power amplifier PA. In the second symbol group portion SBG_1, the SPT control circuit 310 may change the level of the first reference voltage V at the time point "t' b" based on the symbol tracking signal TS_SPT _REFa Is supplied to the first DC-DC converter 320 to have the first switch control signal sw_cs of a low level based on the Trigger signal trigger_spt received at the time point "t2 _a Is provided to the first switching element SW _a And changes the first power voltage V generated by the first DC-DC converter 320 _OUTa Is set to a level of (2). For example, the first supply voltage V may be increased _OUTa Is set to a level of (2).

Since the third symbol group portion sbg_2 and the fourth symbol group portion sbg_3 are substantially the same as the third symbol portion sb_2 and the fourth symbol portion sb_3 of fig. 6 described above, a description thereof will be omitted for the most part.

As depicted in fig. 11, in the third symbol group portion sbg_2, the SPT control circuit 310 may change the level of the second reference voltage V at the time point "t' c" based on the symbol tracking signal ts_spt _REFb The second switch control signal sw_cs having a low level is supplied to the second DC-DC converter 330 _b Is provided to the second switching element SW _b And changes the second power supply voltage V generated by the second DC-DC converter 330 _OUTb Is set to a level of (2). In the fourth symbol group portion SBG_3, the SPT control circuit 310 may change the level of the first reference voltage V at the time point "t'd" based on the symbol tracking signal TS_SPT _REFa The first switch control signal sw_cs having a low level is supplied to the first DC-DC converter 320 _a Is provided to the first switching element SW _a And changes the first electricity generated by the first DC-DC converter 320 Source voltage V _OUTa Is set to a level of (2).

Fig. 12 is a circuit diagram of a symbol tracking modulator 300 "according to an exemplary embodiment of the inventive concept.

Referring to fig. 12, the symbol tracking modulator 300 "may include an SPT control circuit 310", a first DC-DC converter 320", a second DC-DC converter 330", a switching circuit 340", and an output capacitor element C _SPT . The first DC-DC converter 320 "and the second DC-DC converter 330" may support a Dynamic Voltage Scaling (DVS) function. The first DC-DC converter 320″ may include a first conversion control circuit 322", a first comparator 324", a plurality of switching elements (e.g., switching element SW) _c1 And a switching element SW _c2 ) Inductor element L _a Capacitor element C' _a . The second DC-DC converter 330″ may include a second conversion control circuit 332", a second comparator 334", a plurality of switching elements (e.g., switching element SW) _c3 And a switching element SW _c4 ) Inductor element L _b Capacitor element C' _b . The switching circuit 340″ may include a plurality of switching elements (e.g., switching element SW _a1 Switching element SW _a2 Switching element SW _b1 Switching element SW _b2 )。

The switching circuit 340 "of fig. 12 may have a different connection configuration than the switching circuit 340 of fig. 5. In an exemplary embodiment of the inventive concept, the first switching element SW _a1 And a second switching element SW _a2 Can be connected in series with each other, and a third switching element SW _b1 And a fourth switching element SW _b2 Can be connected in series with each other. In addition, a first switching element SW _a1 And a second switching element SW _a2 Can be connected with a third switch element SW _b1 And a fourth switching element SW _b2 Connected in parallel. The SPT control circuit 310″ may generate a plurality of switch control signals SW_CS based on the Trigger signal trigger_SPT _a1 Switch control signal SW_CS _a2 Switch control signal SW_CS _b1 Switch control signal sw_cs _b2 And a plurality of switch control signals SW_CS _a1 Switch control signal SW_CS _a2 Switch control signal SW_CS _b1 Switch controlSignal producing SW_CS _b2 To the switching circuit 340). Since the operation of the symbol tracking modulator 300″ is similar to that described above with reference to fig. 5, a description thereof will be omitted.

Fig. 13 is a flow chart of signals for operation of the symbol tracking modulator 300 "of fig. 12. Hereinafter, it will be assumed that the symbol group unit contains only one symbol.

Referring to fig. 12 and 13, in the first symbol portion sb_0 (a portion between the time point "t0" and the time point "t 1"), the SPT control circuit 310 "may maintain the first reference voltage V at a constant level based on the symbol tracking signal ts_spt _REFa Is provided to the first DC-DC converter 320", and the first switch control signal sw_cs having a high level is provided based on the Trigger signal trigger_spt received at the time point" t0" _a1 Is provided to the first switching element SW _a1 The second switch control signal SW_CS having a low level _a2 Is provided to the second switching element SW _a2 And the first power supply voltage V to be generated by the first DC-DC converter 320' _OUTa As an alternative to the supply voltage V _SPT Is provided to the power amplifier PA. In the first symbol portion SB_0, the SPT control circuit 310' may change the level of the second reference voltage V at the time point "t" a "based on the symbol tracking signal TS_SPT _REFb Is provided to the second DC-DC converter 330", and the third switch control signal sw_cs having a low level is provided based on the Trigger signal trigger_spt received at the time point" t0 _b1 Is provided to the third switching element SW _b1 A fourth switch control signal SW_CS for changing from a low level to a high level at a time point "t" a _b2 Is provided to fourth switching element SW _b2 And changes the second power supply voltage V generated by the second DC-DC converter 330' _OUTb Is set to a level of (2). For example, the second supply voltage V may be increased _OUTb Is set to a level of (2).

In the second symbol portion SB_1 (the portion between the time point "t1" and the time point "t 2"), the SPT control circuit 310 "may change the level of the first reference voltage V at the time point" t1 "based on the symbol tracking signal TS_SPT _REFa Is provided to the first DC-DC converter 320 "based onThe Trigger signal trigger_spt received at the time point "t1" will have the first switch control signal sw_cs of low level _a1 Is provided to the first switching element SW _a1 A second switch control signal SW_CS for changing from a low level to a high level at a time point "t" b _a2 Is provided to the second switching element SW _a2 And changes the first power supply voltage V generated by the first DC-DC converter 320' _OUTa Is set to a level of (2). For example, the first supply voltage V may be increased _OUTa Is set to a level of (2). In the second symbol portion SB_1, the SPT control circuit 310' may change the level of the second reference voltage V at the time point "t" b "based on the symbol tracking signal TS_SPT _REFb Is provided to the second DC-DC converter 330", and the third switch control signal sw_cs having a high level is provided based on the Trigger signal trigger_spt received at the time point" t1 _b1 Is provided to the third switching element SW _b1 The fourth switch control signal SW_CS with low level _b2 Is provided to fourth switching element SW _b2 And a second power supply voltage V to be generated by the second DC-DC converter 330' _OUTb As an alternative to the supply voltage V _SPT Is provided to the power amplifier PA.

Since the third symbol portion sb_2 and the fourth symbol portion sb_3 are substantially the same as the third symbol portion sb_2 and the fourth symbol portion sb_3 of fig. 6 described above, a description thereof will be omitted for the most part.

As shown in fig. 13, in the third symbol portion sb_2, the SPT control circuit 310″ can change the level of the second reference voltage V at the time point "t" c _REFb Is provided to the second DC-DC converter 330". In the fourth symbol portion SB_3, the SPT control circuit 310' may change the level of the second reference voltage V at the time point "t" d _REFb Is provided to the second DC-DC converter 330".

Fig. 14 is a block diagram of a symbol tracking modulator 400 according to an exemplary embodiment of the inventive concept, and fig. 15 is a circuit diagram of a first single-inductor multiple-output (SIMO) converter of fig. 14.

Referring to fig. 14, the symbol tracking modulator 400 may include an SPT control circuit 410, a first SIMO converter 420, a second SIMO converter430 and a switching circuit 440. Referring to fig. 15, the first SIMO converter 420 may include a SIMO conversion control circuit 422, a plurality of comparators 424_1 to 424—n, a plurality of voltage generation circuits 426_1 to 426—n, an inductor L, and a switching element SW _c1 And a switching element SW _c2 . The first SIMO converter 420 may generate a plurality of voltages having different levels and pass through respective output nodes N of the voltage generation circuit 426_1 to the voltage generation circuit 426_n _a1 To output node N _an To output a plurality of voltages.

The voltage generating circuits 426_1 to 426_n may include switching elements SW respectively _a1 To the switching element SW _an Capacitor C ₁ To capacitor C _n . In exemplary embodiments of the present inventive concept, the voltage generating circuits 426_1 through 426—n may include capacitors having different capacitances and different loads, respectively. The comparators 424_1 to 424_n can respectively receive the reference voltage V _REF1 To reference voltage V _REFn And from the voltage generating circuit 426_1 to the output node N of the voltage generating circuit 426_n, respectively _a1 To output node N _an Receiving feedback signal V _OUTa1 To feedback signal V _OUTan A control signal is generated and provided to the SIMO conversion control circuit 422.

In an exemplary embodiment of the inventive concept, SIMO conversion control circuitry 422 may be based on a first voltage-level control signal VL_CS _a Generating a control switch element SW _a1 To the switching element SW _an Switch control signal of on/off operation of (a) to supply the switch control signal to the switch element SW _a1 To the switching element SW _an And changes the first power supply voltage V generated by the first SIMO converter 420 _OUTa Is set to a level of (2). In other words, the SPT modulation operation according to an exemplary embodiment of the inventive concept may be performed using the first SIMO converter 420 that does not support the DVS function.

Referring back to fig. 14, the SPT control circuit 410 may generate a switch control signal sw_cs based on the Trigger signal trigger_spt, provide the switch control signal sw_cs to the switch circuit 440, and alternately select the first SIMO conversionFirst supply voltage V of the transformer 420 _OUTa And a second supply voltage V of a second SIMO converter 430 _OUTb . Other operations of the symbol tracking modulator 420 have been described in detail with reference to fig. 4A, and thus a description thereof will be omitted.

Referring to fig. 16, the symbol tracking modulator 500 may include an SPT control circuit 510, a DC-DC converter 520, a linear amplifier 530, and a switching circuit 540. In other words, the first voltage supply circuit 220 and the second voltage supply circuit 230 of fig. 4A may be implemented as different kinds of circuits, and any one of the first voltage supply circuit 220 and the second voltage supply circuit 230 may be implemented as the linear amplifier 530.

Referring to fig. 17, the symbol tracking modulator 600 may include a large number of voltage supply circuits 620_1 to 620_m as compared to the symbol tracking modulator 200 of fig. 4A. The SPT control circuit 610 may sequentially select the power supply voltages V generated by the voltage supply circuits 620_1 to 620_m based on the Trigger signal trigger_SPT _OUT1 To supply voltage V _OUTm As the selected power supply voltage Vsel, and the level of the unselected power supply voltage is changed based on the sign tracking signal ts_spt.

Since the operations of the symbol tracking modulator 500 and the symbol tracking modulator 600 correspond to the symbol tracking modulator 400 described in detail with reference to fig. 4A, a description thereof will be omitted.

Fig. 18 is a block diagram of a wireless communication device 1000 according to an exemplary embodiment of the inventive concept.

Referring to fig. 18, a wireless communication device 1000, which is an example of a communication device, may include a symbol power tracking amplification system (100), an application specific integrated circuit (application specific integrated circuit; ASIC) 1010, a special instruction set processor (application specific instruction set processor; ASIP) 1030, a memory 1050, a main processor 1070, and a main memory 1090. The symbol power tracking amplification system (100) may support symbol power tracking modulation techniques applied by the embodiments described in the figures. At least two of ASIC 1010, ASIP 1030, and main processor 1070 may communicate with each other. In addition, at least two of ASIC 1010, ASIP 1030, memory 1050, main processor 1070, and main memory 1090 may be embedded in a single chip.

ASIP 1030 is a custom IC for a specific application and may support a specific instruction set for a specific application and execute instructions contained in the instruction set. Memory 1050 may be in communication with ASIP 1030 and act as non-transitory storage to store a plurality of instructions executed by ASIP 1030. In some embodiments of the inventive concept, the memory 1050 may store the SPT control module 114 of fig. 7. Memory 1050 may include any type of memory accessible by ASIP 1030, such as, but not limited to, random access memory (random access memory; RAM), read-only memory (ROM), magnetic tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and/or combinations thereof. ASIP 1030 or main processor 1070 may execute a series of instructions stored in memory 1050 and control SPT modulation operations.

A main processor 1070 can execute a plurality of instructions and control the wireless communication device 1000. For example, the main processor 1070 may control the ASIC 1010 and ASIP 1030, may process data received via a wireless communication network, or process user input of the wireless communication device 1000. The main memory 1090 may be in communication with the main processor 1070 and act as non-transitory storage to store a plurality of instructions for execution by the main processor 1070.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Fig. 19 is a block diagram of a phased array antenna module 2000 in accordance with an embodiment. Hereinafter, example embodiments will be described in which the phased array antenna module 2000 performs a Symbol Power Tracking (SPT) modulation operation suitable for fifth generation (5G) communications, but the present concepts are not limited thereto and may be applied to other power tracking schemes.

Referring to fig. 19, a phased array antenna module 2000 may include electricalA source management integrated circuit (power management integrated circuit; PMIC) 2100 and a phased array transceiver 2200. The PMIC 2100 may include two direct current-to-direct current (DC-DC) converters (hereinafter referred to as buck converters) 2110 and 2120, a 1.1 volt drop-out (LDO) linear regulator 2130, an auxiliary LDO 2140, a fast charge/discharge current source 2150, a reference voltage generator 2160, a controller 2170, a multiplexer 2180, a plurality of capacitors C _1.1V Capacitor C _1.3V Capacitor C _L1 Capacitor C _L2 A plurality of SPT switches SW _L1 Switch SW _L2 Switch SW _SD1 Switch SW _SD2 And a single-inductor dual-output (SIDO) switch SW _SIDO . The first buck converter 2110 may be implemented to perform the operations of the first voltage supply circuit 220 and the second voltage supply circuit 230 of fig. 4A. The second buck converter 2120 may be implemented to precharge or pre-discharge the load capacitor C according to the point in time of the SPT operation _L1 And a load capacitor C _L2 . At the same time, SPT switch SW _L1 SPT switch SW _L2 SPT switch SW _SD1 SPT switch SW _SD2 May also be implemented to convert the supply voltage V corresponding to SPT operation _SPT Provided to phased array transceiver 2200.

The controller 2170 may include a mobile industry processor interface (mobile industry processor interface; MIPI) slave 2172, a master controller 2174, a fixed frequency controller (Fixed Frequency Controller; FFC) 2176, and an internal clock source 2178. The phased array transceiver 2200 may include two transceiving circuits 2210_a and 2210_b, a microcontroller unit (microcontroller unit; MCU) 2220, an MIPI master 2230, and an internal LDO 2240. The transceiving circuits 2210_a and 2210_b may include a plurality of antennas Ants, a plurality of Radio Frequency (RF) circuits rf_ckts, mixers mix_a and mix_b, and Interface circuits interface_ckta. Each of the RF circuits rf_ckts may include a transceiver switch TRX SWa, a low noise amplifier LNA, a power amplifier PA, a plurality of mixers mix_a and mix_b, a plurality of filters ft_a and ft_b, and a plurality of phase shifters PS. The transceiving circuit 2210_a and the transceiving circuit 2210_b may be connected to an Intermediate Frequency (IF) circuit if_ckt_a and an intermediate frequency circuit if_ckt_b of the IF transceiver. The transceiving circuit 2210_a and the transceiving circuit 2210_b may receive RF signals through the antenna Ants, down-convert the RF signals into IF signals, and provide the IF signals to the IF transceiver.

Each of the IF circuits if_ckt_a and IF circuit if_ckt_b may include a transceiver switch TRX SWb, a low noise amplifier LNA, a power amplifier PA, a plurality of mixers mix_c and mix_d, a plurality of filters ft_c and ft_d, and an Interface circuit interface_cktb. Each of the IF circuits if_ckt_a and IF circuits if_ckt_b may down-convert the received IF signal to a baseband signal and provide the baseband signal to the 5G modem.

After the power-on reset signal is generated by the external digital power source, the digital communication channel caused by MIPI between the PMIC 2100 and the phased array transceiver 2200 may be ready. That is, the digital communication channel between the MIPI master 2230 and the MIPI slave 2172 may be ready.

The MCU 2220 may generate a timing signal Tick (or trigger signal) at each Cyclic Prefix (CP) start time to precisely synchronize with the transmit power update time point and the SPT transition time point. Meanwhile, the MCU 2220 may provide DATA, a clock signal CLK, and a timing signal tack required for the SPT operation of the PMIC 2100 to the MIPI slave 2172 and the master controller 2174 of the controller 2170 through the MIPI master device 2230.

The MIPI slave 2172 may receive the DATA and the clock signal CLK, and generate a signal based on the DATA and the clock signal CLK to the reference voltage generator 2160. The reference voltage generator 2160 may include a first digital-to-analog converter (DAC) DAC1 connected to the first buck converter 2110, and a second DAC2 selectively connected to either of the second buck converter 2120 and the auxiliary LDO2140 through a multiplexer 2180.

The master controller 2174 may receive an internal clock signal from an internal clock source 2178 and a supply voltage V _SPT And supply voltage V _o1.3V Load capacitor voltage V _C1 And a load capacitor voltage V _C2 May be fed back into the master controller 2174. Main controller 2174 may be based on the received voltage V _SPT Voltage V _o1.3V Voltage V _C1 And voltage V _C2 And an internal clock signal to generate an enable signal enable for the fast charge/discharge current source 2150, a Mode selection signal Mode sel for selecting a power tracking Mode using the first buck converter 2110 and the second buck converter 2120, a DAC selection signal DAC sel of the reference voltage generator 2160, and a switch control signal cap.

Meanwhile, the FFC 2176 may control the frequencies of the buck converter 2110, 2120 to be constant. That is, when operating in the hysteretic control mode, the buck converter 2110, the buck converter 2120 are not synchronized to the reference clock and therefore can change frequency according to PVT variations and operating conditions. To prevent such frequency variation, the FFC 2176 may supply a first Fixed Frequency Control (FFC) signal FFC1 and a second FFC signal FFC2 generated based on the internal clock signal to the buck converter 2110, 2120, respectively.

For SPT operation according to an embodiment, a load capacitor C may be used _L1 And a load capacitor C _L2 Capacitor switching operation and output capacitor C therebetween _SPT The two control schemes related to the rapid charge/discharge operation are applied to the PMIC 2100. Specifically, the capacitor swap operation may be controlling the second buck converter BK _SIDO And a load capacitor C _L1 And a load capacitor C _L2 To selectively connect the load capacitor C _L1 And a load capacitor C _L2 The operation of pre-charging or pre-discharging may be performed in the SPT operation according to the embodiment. In addition, a quick charge/discharge operation may be performed using the quick charge/discharge current source 2150. Since the rapid charge/discharge operation is described with reference to fig. 7A and 7B, a detailed description thereof will be omitted.

Since the phased array transceiver 2200 may consume a large supply current at 1.1 volts, the second buck converter 2120 may implement a 1.3 volt DC-DC buck conversion to enable efficient sub-regulation (sub-regulation) of the 1.1 volt LDO 2130 using SIDO operation.

Fig. 20A and 20B are diagrams illustrating an SPT operation using SIDO according to an embodiment. Since the configuration of the PMIC 2100 of fig. 20A is the same as that described with reference to fig. 19, a repetitive description thereof will be omitted.

Referring to fig. 20A, to enable SPT operation, a first buck converter 2110 may receive two data from a fifth generation (5G) modem. One data may be data on a power level of the next symbol, and the other data may be data on a CP start time. The second buck converter 2120 may precharge or pre-discharge the first load capacitor C based on power level data over a predetermined current symbol duration of, for example, 4.16 microseconds _L1 And a second load capacitor C _L2 . When the first buck converter 2110 performs the SPT operation and the second buck converter 2120 performs the precharge operation, the auxiliary LDO (referred to as auxiliary LDO 2140 in fig. 19) may start smoothly regulating the precharge or pre-discharge of the first load capacitor C instead of the power supply of the 1.3 volt supply voltage _L1 And a second load capacitor C _L2 The required 1.3 volt voltage and supply current in the feedback loop. When the first load capacitor C _L1 And a second load capacitor C _L2 Upon completion of the precharge operation above, the second buck converter 2120 may regulate the 1.3 volt DC output to enable sub-regulation of the 1.1 volt LDO (referred to as 1.1 volt LDO 2130 in fig. 19). The second buck converter 2120 may receive the CP start time signal, the first load capacitor C _L1 And a second load capacitor C _L2 Can be connected with V _SPT The output is disconnected and the fast charge/discharge current source 2150 may fast charge or discharge the output capacitor C under the control of the fast charge controller 2175 _SPT . As output capacitor C _SPT With a first load capacitor C _L1 Or a second load capacitor C _L2 When the voltage difference between them is within the threshold, the fast charge controller 2175 may generate the switch trigger signal SWAP_EN and output the capacitor C _SPT Can be connected to the first load capacitor C in response to the switch trigger signal SWAP_EN _L1 And a second load capacitor C _L2 Any one of them.

In SPT operation according to an embodiment, output capacitor C _SPT Can be charged or discharged rapidlyElectric, and a first load capacitor C _L1 And a second load capacitor C _L2 May be pre-charged or pre-discharged by the second buck converter 2120. As output capacitor C _SPT With a first load capacitor C _L1 Or a second load capacitor C _L2 When the voltage difference between the voltage difference is the threshold value or less, the capacitor swap operation can be performed at V _SPT Output and first load capacitor C _L1 And a second load capacitor C _L2 And between. It is ensured that the transition ends within a duration of about 290 nanoseconds (ns) and that high input rush currents are prevented.

Referring back to fig. 20B, the first buck converter BK _SPT May have a first level LV for a duration corresponding to a first uplink Symbol UL Symbol 1 in response to a first trigger signal Tick ₁ First load capacitor C of voltage _L1 Connected to V _SPT And outputting. Thus, in a duration corresponding to the first uplink symbol UL symbol 1, it will have a first level LV ₁ Is set to the power supply voltage V of _SPT To a Power Amplification (PA) array (array). In addition, the first buck converter BK _SPT Is responsive to PWL _S1 "Signal to generate signal having the second level LV ₂ Second load capacitor voltage V of (2) _C2 . In a duration corresponding to the first uplink symbol UL symbol 1, can pass through the first load capacitor C _L1 And output capacitor C _SPT To determine the output load capacitance of PMIC 2100.

Meanwhile, in response to the second trigger signal Tick, the fast charge controller 2175 may control the output capacitor C _SPT A fast linear charging operation to cause the supply voltage V to be _SPT Is charged to the second level LV ₂ . During the duration of the fast linear charge operation, the capacitor C can be output _SPT To determine the output load capacitance of PMIC 2100.

As output capacitor C _SPT And a second load capacitor C _L2 When the voltage difference between the two is the threshold value or less, the main controller 2174 can respond to the second trigger signal Tick by corresponding to the second uplink The duration of the path Symbol UL Symbol 2 will have a second level LV ₂ Second load capacitor C of voltage _L2 Connected to V _SPT And outputting. Thus, in a duration corresponding to the second uplink symbol UL symbol 2, it will have a second level LV ₂ Is set to the power supply voltage V of _SPT Is provided to the PA array. In addition, the first buck converter BK _SPT Is responsive to PWL _S2 "Signal to generate signal having third level LV ₃ First load capacitor voltage V of (2) _C1 And a second buck converter BK _SIDO The first load capacitor C can be precharged _L1 . In a duration corresponding to the second uplink symbol UL symbol 2, can pass through the second load capacitor C _L2 And output capacitor C _SPT To determine the output load capacitance of PMIC 2100.

Meanwhile, in response to the third trigger signal Tick, the fast charge controller 2175 may control the output capacitor C _SPT A rapid linear discharge operation to cause the supply voltage V to be _SPT Is discharged to the third level LV ₃ . During the duration of the rapid linear discharge operation, the capacitor C can be passed through _SPT To determine the output load capacitance of PMIC 2100.

As output capacitor C _SPT With a first load capacitor C _L1 When the voltage difference therebetween is a threshold or less, the master controller 2174 may have a third level LV for a duration corresponding to a third uplink Symbol UL Symbol 3 in response to a third trigger signal rack ₃ First load capacitor C of voltage _L1 Connected to V _SPT And outputting. Thus, in a duration corresponding to the third uplink symbol UL symbol 3, it will have a third level LV ₃ Is set to the power supply voltage V of _SPT Is provided to the PA array. In addition, the first buck converter BK _SPT Is responsive to PWL _S3 "Signal to generate signal having first level LV ₁ Second load capacitor voltage V of (2) _C2 And a second buck converter BK _SIDO The second load capacitor C can be precharged _L2 . Corresponding to the third uplink symbol UL symFor a duration of bol 3, can be passed through a first load capacitor C _L1 And output capacitor C _SPT To determine the output load capacitance of PMIC 2100.

Fig. 21 is a block diagram of a PMIC 3000 including two buck converters (e.g., a first buck converter 3100 and a second buck converter 3200) configured to support a ripple injection hysteresis control function, according to an embodiment.

Referring to fig. 21, a pmic 3000 may include a first buck converter 3100, a second buck converter 3200, an auxiliary LDO 3300, a plurality of switches SW _SIDO Switch SW _SD1 Switch SW _SD2 Switch SW _L1 Switch SW _L2 And a plurality of capacitors C _1.3V Capacitor C _L1 Capacitor C _L2 Capacitor C _SPT . The first buck converter 3100 may include M _P1 Transistor, M _N1 Transistor, gate driver, SPT inductor L _SPT Variable resistor R _r1 A plurality of resistors R _f1a 、R _f1b 、R _f1c R is as follows _f1d A plurality of capacitors C _ac1 、C _r1 C _f1 DAC, buffer BUF, and switch DPC for dynamic precharge control ₁ . The second buck converter 3200 may include M _P2 Transistor, M _N2 Transistor, gate driver, SIDO inductor L _SIDO Variable resistor R _r2 A plurality of resistors R _f2a Resistor R _f2b Resistor R _f2c Resistor R _f2d A plurality of capacitors C _ac2 Capacitor C _r2 Capacitor C _f2 DAC, comparator BUF, switch DPC for dynamic precharge control ₂ And is to be connected to a load capacitor C _1.3V Load capacitor C _L1 Load capacitor C _L2 Multiple feedback selector switches FSS of (a) _1.3V Feedback selector switch FSS _C1 Feedback selector switch FSS _C2 . Meanwhile, the auxiliary LDO 3300 may include a comparator COMP, a feedback block FB and M _P3 And a transistor.

As depicted in fig. 21, the configuration of the first buck converter 3100 and the second buck converter 3200 may be used to ensure stability of the loop and smooth transitions, and the target outputs of the first buck converter 3100 and the second buck converter 3200 may be stable even if there is a sharply changing feedback input. That is, the first buck converter 3100 and the second buck converter 3200 may smoothly perform the SPT operation and the SIDO operation, respectively.

In the first buck converter 3100 and the second buck converter 3200 according to the embodiment, the dynamic precharge control method may pass through some switches DPC ₁ And switch DPC ₂ Applied to the hysteresis feedback loop. Only the SPT or SIDO transition time is required to directly form the feed-forward path from the output to the internal compensation node. By using the dynamic precharge control method described above, the loop response time can be shortened to within a predetermined amount of time. According to the case of the SPT operation and the SIDO operation, the reference voltage generator included in the first buck converter 3100 and the second buck converter 3200 may generate an appropriate reference voltage so as to enable each buck regulation operation. The reference voltage generator may include two DACs, two buffers BUF, and tracking&A holding circuit.

The hysteresis controller may produce a change in the output switching frequency depending on the ratio of input to output. The variation of the output switching frequency can be modulated into the PA transmit signal and represented by an undesirable spurious (spurius) spectrum.

When there is a change in process, voltage, and temperature (PVT), the switching frequency controller may apply a simple frequency-locked loop to the hysteresis controller to ensure noise attenuation due to the selected inductor-capacitor (LC) filtering.

Claims

1. A symbol power tracking amplification system comprising:

a modem configured to generate a data signal and a symbol tracking signal in response to an external data signal;

a symbol tracking modulator comprising a control circuit, a first voltage supply circuit, a second voltage supply circuit, and a switching circuit, wherein the control circuit is configured to generate a first voltage level control signal and a second voltage level control signal in response to the symbol tracking signal, the first voltage supply circuit is configured to generate a first output voltage in response to the first voltage level control signal, the second voltage supply circuit is configured to generate a second output voltage in response to the second voltage level control signal, and the switching circuit is configured to output one of the first output voltage and the second output voltage as a power supply voltage in response to a switching control signal provided from the control circuit;

a radio frequency block configured to generate a radio frequency signal based on the data signal from the modem; and

a power amplifier configured to adjust a power level of the radio frequency signal based on the supply voltage output from the symbol tracking modulator,

Wherein the second voltage supply circuit generates the second output voltage when the first output voltage is output from the symbol tracking modulator,

wherein the symbol tracking modulator is configured to receive a trigger signal corresponding to a symbol group unit and alternately select the first output voltage and the second output voltage based on the trigger signal, an

Wherein the trigger signal informs the symbol tracking modulator of the point in time at which the symbol group unit starts.

2. The symbol power tracking amplification system of claim 1, wherein said first output voltage is output during a first symbol period.

3. The symbol power tracking amplification system of claim 1, wherein said control circuit comprises: a first digital-to-analog converter to generate the first voltage level control signal; and a second digital-to-analog converter to generate the second voltage level control signal.

4. The sign power tracking amplification system of claim 1, wherein the first voltage supply circuit has the first voltage level control signal as a first reference voltage from the control circuit to generate the first output voltage in a first symbol period, and the second voltage supply circuit has the second voltage level control signal as a second reference voltage to prepare the second output voltage in the first symbol period when the first output voltage is driven by the first voltage supply circuit.

5. The symbol power tracking amplification system of claim 4, wherein said second output voltage is output from said symbol tracking modulator in a second symbol period after said second output voltage has been prepared in said first symbol period.

6. The symbol power tracking amplification system of claim 4, wherein said second output voltage is prepared by charging a capacitor while said first output voltage is output from an output node of said symbol tracking modulator.

7. The sign power tracking amplification system of claim 1, wherein said first voltage supply circuit comprises a single-inductor multiple-output converter.

8. A symbol tracking modulator, comprising:

a control circuit configured to generate a first reference voltage and a second reference voltage in response to the sign-tracking signal;

a first voltage supply circuit configured to generate a first output voltage in response to the first reference voltage;

a second voltage supply circuit configured to generate a second output voltage in response to the second reference voltage; and

a switching circuit configured to output one of the first output voltage and the second output voltage as a power supply voltage in response to a switching control signal supplied from the control circuit,

Wherein the second voltage supply circuit prepares the second output voltage to be output as the power supply voltage in a second symbol period, which occurs after the first symbol period,

wherein the control circuit is configured to generate the switch control signal based on a trigger signal corresponding to a symbol group unit,

wherein the trigger signal is received from outside by the symbol tracking modulator, an

9. The symbol tracking modulator of claim 8 wherein the symbol tracking signal is provided from a modem.

10. The symbol tracking modulator of claim 8, wherein the supply voltage is provided to a power amplifier.

11. The symbol tracking modulator of claim 8, wherein the first output voltage is output as the supply voltage during a first symbol period and the second output voltage is output as the supply voltage during a second symbol period subsequent to the first symbol period.

12. The symbol tracking modulator of claim 8, wherein the first output voltage is output as the supply voltage during a first symbol group period and the second output voltage is output as the supply voltage during a second symbol group period subsequent to the first symbol group period.

13. The symbol tracking modulator of claim 8, further comprising:

a first capacitor selectively connected to an output node of the symbol tracking modulator; and

a second capacitor selectively connected to the output node of the symbol tracking modulator.

14. The symbol tracking modulator of claim 13, wherein the second capacitor is disconnected from the output node and charged by the second voltage supply circuit when the first capacitor is connected to the output node of the symbol tracking modulator in a first symbol period.

15. The symbol tracking modulator of claim 14, wherein in a second symbol period subsequent to the first symbol period, the second capacitor is connected to the output node of the symbol tracking modulator and the first capacitor is disconnected from the output node and charged by the first voltage supply circuit.

16. The symbol tracking modulator of claim 14, wherein the second capacitor is charged to the same level in the first symbol period as the supply voltage output from the symbol tracking modulator in the second symbol period.