US8085015B2 - Current balancing circuit and method - Google Patents

Abstract

A multi-phase power converter and a method for balancing a plurality of currents in the multi-phase power converter. The multi-phase power converter has a pulse width modulation circuit, a current ordering circuit, and a plurality of currents, wherein each current of the plurality of currents has an associated phase. The converter determines the phase associated with one or more currents of a plurality of currents and whether a phase associated with one or more currents of the plurality of currents is active. The current levels of the plurality of currents are determined and a phase associated with a current having one of a lowest current level or a highest current level is activated.

Description

TECHNICAL FIELD

This invention relates, in general, to power converters and, more particularly, to multi-phase power converters.

BACKGROUND

Power converters are used in a variety of electronic products including automotive, aviation, telecommunications, and consumer electronics. Power converters such as Direct Current to Direct Current (“DC-DC”) converters have become widely used in portable electronic products such as laptop computers, personal digital assistants, pagers, cellular phones, etc., which are typically powered by batteries. DC-DC converters are capable of delivering multiple voltages from a single voltage independent of the load current being drawn from the converter or from any changes in the power supply feeding the converter. One type of DC-DC converter that is used in portable electronic applications is a buck converter. This converter, also referred to as a switched mode power supply, is capable of switching an input voltage from one voltage level to a lower voltage level. A buck converter is typically controlled by a controller that can be configured to be a multi-phase controller having a plurality of output current channels that switch at different times. The output currents flowing in the output current channels are summed and delivered to the load. An advantage of this configuration is that each channel conducts a portion of the total load current. For example, in a 4-phase buck controller, each channel conducts 25% of the output current. This lowers the power dissipated by each output. A drawback with a multi-phase buck controller is that when the currents are not balanced, one of the current channels will conduct more current than the other current channels, which could lead to thermal failure. Another drawback is that a dynamic load coupled to the controller may have the same repetition rate as one of the outputs of the multi-phase buck converter. In this case, the currents in the channels become unbalanced causing the converter to suffer thermal failure.

Accordingly, it would be advantageous to have a multi-phase controller circuit and a method of operating the multi-phase converter circuit that maintains a balanced current at its outputs. In addition, it is desirable for the multi-phase controller circuit to be cost and time efficient to manufacture.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference characters designate like elements and in which:

FIG. 1 is a schematic diagram of a multi-phase converter circuit in accordance with an embodiment of the present invention;

FIG. 2 is a schematic diagram of a portion of the multi-phase converter circuit of FIG. 1; and

FIG. 3 is a timing diagram for a multi-phase converter circuit in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of a multi-phase power converter 10 manufactured in a semiconductor substrate in accordance with an embodiment of the present invention. FIG. 2 is a block diagram of an embodiment of an output stage 33 of multi-phase power converter 10. It should be noted that FIGS. 1 and 2 will be described together. What is shown in FIG. 1 is a Pulse Width Modulator (“PWM”) circuit 12 having “n” sets of inputs 12 ₁, 12 ₂, 12 ₃, . . . , 12 _n, where “n” is an integer. Each of the “n” sets of inputs comprises an error input 12 _nA and an oscillator input 12 _nB. It should be noted that the letters “A” and “B” are used in the reference characters to distinguish between error inputs and oscillator inputs, respectively. Thus, input 12 ₁ comprises an error input 12 _1A and an oscillator input 12 _1B; input 12 ₂ comprises an error input 12 _2A and an oscillator input 12 _2B; input 12 ₃ comprises an error input 12 _3A and an oscillator input 12 _3B; and input 12 _n comprises an error input 12 _nA and an oscillator input 12 _nB.

Multi-phase power converter 10 further includes an error amplifier 16 having an output 17 connected to error inputs 12 _1A, 12 _2A, 12 _3A, . . . , 12 _nA and an oscillator 18 having a plurality of outputs, wherein the plurality of outputs are connected to corresponding oscillator inputs 12 _1B, 12 _2B, 12 _3B, . . . , 12 _nB. In accordance with an embodiment of the present invention, error amplifier 16 comprises an operational amplifier 20 connected in a negative feedback configuration in which an impedance 22 is coupled between the output of operational amplifier 20 and its inverting input and an impedance 24 is connected to the inverting input of operational amplifier 20. By way of example, impedance 22 comprises a capacitor 26 coupled in parallel with a series connected resistor 28 and capacitor 30, and impedance 24 comprises a resistor. The non-inverting input of operational amplifier 20 is coupled for receiving a reference voltage level V_REF1. It should be understood that the feedback configuration of error amplifier 16 is not a limitation of the present invention and that it may be realized using other feedback configurations known to those skilled in the art.

PWM circuit 12 is coupled to an output stage 33 comprising power stages 34 ₁, 34 ₂, 34 ₃, . . . , 34 _n through a pulse assign circuit 60, which has PWM inputs 62 ₁, 62 ₂, 62 ₃, . . . , 62 _n, current ordering inputs 63 ₁, 63 ₂, 63 ₃, . . . , 63 _n, and PWM outputs 64 ₁, 64 ₂, 64 ₃, . . . , 64 _n. Outputs 14 ₁, 14 ₂, 14 ₃, . . . , 14 _n of PWM circuit 12 are connected to PWM inputs 62 ₁, 62 ₂, 62 ₃, . . . , 62 _n of pulse assign circuit 60, respectively. A current ordering circuit 65 having inputs 66 ₁, 66 ₂, 66 ₃, . . . , 66 _n and outputs 67 ₁, 67 ₂, 67 ₃, . . . , 67 _n is connected to pulse assign circuit 60, where inputs 66 ₁, 66 ₂, 66 ₃, . . . , 66 _n are connected to current ordering inputs 63 ₁, 63 ₂, 63 ₃, . . . , 63 _n of pulse assign circuit 60.

Power stages 34 ₁, 34 ₂, 34 ₃, . . . , 34 _n comprise driver circuits 54 ₁, 54 ₂, 54 ₃, . . . , 54 _n, respectively, having inputs that serve as the inputs of power stage 34 ₁, 34 ₂, 34 ₃, . . . , 34 _n, high-side driver outputs connected to the gates of the respective switching transistors 57 ₁, 57 ₂, 57 ₃, . . . , 57 _n, and low-side driver outputs connected to the gates of the respective switching transistors 59 ₁, 59 ₂, 59 ₃, . . . , 59 _n. The drains of high- side switching transistors 57 ₁, 57 ₂, 57 ₃, . . . , 57 _n are coupled for receiving a source of operating potential such as, for example, V_CC, and the sources of high- side switching transistors 57 ₁, 57 ₂, 57 ₃, . . . , 57 _n are connected to the respective drains of low- side switching transistors 59 ₁, 59 ₂, 59 ₃, . . . , 59 _n. The sources of low- side switching transistors 59 ₁, 59 ₂, 59 ₃, . . . , 59 _n are coupled for receiving a source of operating potential such as, for example, V_SS. The commonly connected sources and drains of transistors 57 ₁, 57 ₂, 57 ₃, . . . , 57 _n and transistors 59 ₁, 59 ₂, 59 ₃, . . . , 59 _n, respectively, are connected to a terminal of the respective energy storage elements 56 ₁, 56 ₂, 56 ₃, . . . , 56 _n. The other terminals of energy storage elements 56 ₁, 56 ₂, 56 ₃, . . . , 56 _n serve as outputs of power stages 34 ₁, 34 ₂, 34 ₃, . . . , 34 _n and are coupled together to form an output node 50. By way of example, energy storage elements 56 ₁, 56 ₂, 56 ₃, . . . , 56 _n are inductors.

PWM outputs 64 ₁, 64 ₂, 64 ₃, . . . , 64 _n of pulse assign circuit 60 are connected to corresponding inputs of power stages 34 ₁, 34 ₂, 34 ₃, . . . , 34 _n, respectively. Outputs of power stages 34 ₁, 34 ₂, 34 ₃, . . . , 34 _n are connected to an output node 50. Power stages 34 ₁, 34 ₂, 34 ₃, . . . , 34 _n have current sense modules 35 ₁, 35 ₂, 35 ₃, . . . , 35 _n, respectively, that generate feedback currents I_FEED1, I_FEED2, I_FEED3, . . . , I_FEEDn that are proportional to the currents flowing through energy storage elements 56 ₁, 56 ₂, 56 ₃, . . . , 56 _n. Feedback current signals I_FEED1, I_FEED2, I_FEED3, . . . , I_FEEDn, are fed back to PWM circuit 12 through feedback interconnects 37 ₁, 37 ₂, 37 ₃, . . . , 37 _n, respectively and to inputs 66 ₁, 66 ₂, 66 ₃, . . . , 66 _n of current ordering circuit 65. Alternatively, current sense modules 35 ₁, 35 ₂, 35 ₃, . . . , 35 _n can be configured to generate feedback signals that are voltages. Circuit configurations for current sense modules are known to those skilled in the art.

A load 80 is coupled between output node 50 and a source of operating potential such as, for example, V_SS. An output capacitor 82 is connected in parallel with load 80. Output node 50 is connected in a feedback configuration to impedance 24 of error amplifier 16.

FIG. 3 is a timing diagram 100 illustrating the temporal relationship among signals OSC1, OSC2, OSC3, and OSC4 from oscillator 18, pulse width modulated signals PWM₁, PWM₂, PWM₃, and PWM₄ from PWM circuit 12 that are input into pulse assign circuit 60, assigned PWM signals APWM₁, APWM₂, APWM₃, and APWM₄ from pulse assign circuit 60, and parameters such as, for example, inductor currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄. Timing diagram 100 is a timing diagram for a four-phase power converter, i.e., a power converter for which n=4, however, the number of phases is not a limitation of the present invention. Power converter 10 can be a two-phase power converter (n=2), a three-phase power converter (n=3), a four-phase power converter (n=4), etc. It should be noted that pulse assign circuit 60 receives pulse width modulated signals from PWM 12, i.e., signals PWM₁, PWM₂, PWM₃, and PWM₄, and uses these signals as turn-on or turn-off signals for the inductor current phases. In other words, outputs 64 ₁, 64 ₂, 64 ₃, . . . , 64 ₄ of pulse assign circuit 60 are enabled or disabled by signals PWM₁, PWM₂, PWM₃, and PWM₄ from PWM circuit 12, the current levels of inductor currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄, and whether one or more of outputs 64 ₁, 64 ₂, 64 ₃, . . . , 64 ₄ is enabled and conducting an output signal in accordance with one or more of the inductor current phases. If an output signal containing information from one or more of inductor currents IL56 ₁, IL56 ₂, IL56 ₃, . . . , IL56 ₄ is being transmitted through one of outputs 64 ₁, 64 ₂, 64 ₃, . . . , 64 ₄ in accordance with one or more of signals PWM₁, PWM₂, PWM₃, and PWM₄, the inductor phase current is turned on. For example, pulse assign circuit 60 may receive signal PWM₁ at its input 62 ₁ that corresponds to inductor current IL56 ₁; however, pulse assign circuit 60 may enable output 64 ₄, thereby transmitting the output signal associated with current IL56 ₄. In this case, the inductor current phase of signal PWM₄, or alternatively current IL56 ₄, is said to be turned-on, enabled, active, or activated. Changing the enabled output changes the output PWM signal that is transmitted and is therefore referred to as swapping the ramp signal or assigning the ramp signal. When a signal at outputs 64 ₁, 64 ₂, 64 ₃, . . . , 64 _n is at a logic low level, the inductor current phase is said to be turned-off or inactive.

As discussed before, timing diagram 100 illustrates triangular waveforms or ramp signals generated by oscillator 18 for a 4-phase power converter. What is shown in FIG. 3 is a triangular waveform OSC₁ having an amplitude ranging from voltage level V_LOSC1 to voltage level V_HOSC1, a triangular waveform OSC₂ having an amplitude ranging from voltage level V_LOSC2 to voltage level V_HOSC2, a triangular waveform OSC₃ having an amplitude ranging from voltage level V_LOSC3 to voltage level V_HOSC3, and a triangular waveform OSC₄ having an amplitude ranging from voltage level V_LOSC4 to voltage level V_HOSC4. Triangular waveforms OSC₁ and OSC₂ have phase angles that are separated by 90 degrees; triangular waveforms OSC₂ and OSC₃ have phase angles that are separated by 90 degrees; triangular waveforms OSC₃ and OSC₄ have phase angles that are separated by 90 degrees; and triangular waveforms OSC₄ and OSC₁ have phase angles that are separated by 90 degrees. Waveform OSC₁ lags waveform OSC₂ by 90 degrees; waveform OSC₁ lags waveform OSC₃ by 180 degrees; waveform OSC₁ lags waveform OSC₄ by 270 degrees. Waveforms OSC₁-OSC₄ have been shown as separate plots for the sake of clarity.

In response to signals OSC₁, OSC₂, OSC₃, and OSC₄ from oscillator 18, an error signal from error amplifier 16, and feedback signals from power stages 34 ₁, 34 ₂, 34 ₃, and 34 ₄, PWM circuit 12 generates pulse width modulated signals PWM₁, PWM₂, PWM₃, and PWM₄ at outputs 14 ₁, 14 ₂, 14 ₃, and 14 ₄, respectively. Signals PWM₁, PWM₂, PWM₃, and PWM₄ are transmitted to pulse assign circuit 60 and serve as turn-on or turn-off signals as described above. In the example shown in FIG. 3, the turn-on operation is described with reference to times t₀-t₃, a turn-on turn-off operation is described with reference to times t₄ and t₅, and the turn-off operation is described with reference to times t₆-t₉. At time to, signals PWM₁, PWM₂, PWM₃, and PWM₄ have been transmitted from PWM circuit 12 to PWM inputs 62 ₁, 62 ₂, 62 ₃, and 62 ₄ of pulse assign circuit 60, respectively. At time t₀, signal PWM₁ transitions to a logic high level and signals PWM₂, PWM₃, and PWM₄ remain at logic low levels. It should be noted that a logic low level is also referred to as a logic zero level and a logic high level is also referred to as a logic one level.

Current ordering circuit 65 compares the levels of currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ at time t₀ with each other and transmits the current level information to pulse assign circuit 60. At time t₀, current IL56 ₄ has the lowest current level, current IL56 ₃ the second lowest current level, current IL56 ₂ the third lowest current level, and current IL56 ₁ the highest current level. In other words, current IL56 ₁ has the highest current level, current IL56 ₂ the second highest current level, current IL56 ₃ the third highest current level, and current IL56 ₄ the lowest current level. In response to signal PWM1 being at a logic high level, pulse assign circuit 60 determines whether any of the inductor current phases have been turned on. If none of the inductor current phases have been turned on, pulse assign circuit 60 enables output 64 ₄ which then transmits the inductor current phase associated with the lowest inductor current level to output 64 ₄ of pulse assign circuit 60. If one or more of the inductor current phases has been turned on, pulse assign circuit 60 enables the output of the inductor current phase associated with the current having the lowest level from among the inductor current phases that have been turned off, i.e., pulse assign circuit 60 swaps which output is enabled to an output associated with an inductor having the lowest inductor current. Pulse assign circuit 60 enables an output for an inductor current associated with an inductor current phase that has been turned-off.

In this example, all of the inductor current phases are turned-off at time t₀, thus pulse assign circuit 60 enables an output associated with an inductor having the lowest current level and where the associated inductor current phase is turned-off. Accordingly, pulse assign circuit 60 enables its output that is associated with the inductor current having the lowest current level, i.e., output 64 ₄. In response to signal PWM₁ turning-on the inductor current phase that is associated with signal PWM₄, pulse assign circuit 60 enables output 64 ₄ which conducts a PWM signal in accordance with the inductor current phase associated with inductor current IL56 ₄ rather than enabling output 64 ₁ and conducting a PWM signal in accordance with the inductor current phase associated with current IL56 ₁, i.e., rather than turning on the inductor current phase associated with current IL56 ₁. Pulse assign circuit 60 stores information indicating that the inductor current phase associated with inductor current IL56 ₄ has been turned-on. The inductor current phases associated with signals PWM1, PWM2, and PWM3 remain off.

At time t₁, signal PWM₂ transitions to a logic high level, therefore, signal PWM1 remains at a logic high level, signals PWM₃ and PWM₄ remain at logic low levels and signal PWM₂ is now at a logic high level. Current ordering circuit 65 compares the current levels of currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ at time t₁ with each other and transmits the current level information to pulse assign circuit 60. At time t₁, current IL56 ₄ still has the lowest current level, current IL56 ₃ the second lowest current level, current IL56 ₂ the third lowest current level, and current IL56 ₁ the highest current level. In other words, current IL56 ₁ has the highest current level, current IL56 ₂ the second highest current level, current IL56 ₃ the third highest current level, and current IL56 ₄ the lowest current level. In response to signal PWM₂ being at a logic high level, pulse assign circuit 60 determines whether any of the inductor current phases have been turned on, selects the inductor current having the lowest current level from the inductor current phases that are turned off, i.e., the inductor current phases associated with inductor currents IL56 ₁, IL56 ₂, and IL56 ₃, and enables a corresponding output 64 ₁, 64 ₂, 64 ₃, and 64 ₄ to conduct a PWM signal in accordance with the inductor current phase associated with the inductor current. In this example, the inductor current phase associated with inductor current IL56 ₄ has been turned on as described above. Thus, pulse assign circuit 60 enables an output associated with an inductor current phase selected from the inductor current phases associated with inductor currents IL56 ₁, IL56 ₂, and IL56 ₃. Because inductor current IL56 ₃ is the lowest inductor current and the inductor current phase associated with inductor current IL56 ₃ is turned-off, pulse assign circuit 60 enables output 64 ₃. Thus, in response to signal PWM₂ enabling output 64 ₃, i.e., the output that conducts the inductor current phase associated with signal PWM₃, pulse assign circuit 60 swaps the inductor current phase associated with signal PWM₂ for the inductor current phase associated with signal PWM₃, i.e., pulse assign circuit 60 re-assigns the inductor current phase that is transmitted from pulse assign circuit 64 which re-assigns the PWM signal that is transmitted to output stage 33. In addition, pulse assign circuit 60 stores information indicating that the inductor current phase associated with inductor current IL56 ₃ has been turned on and that the inductor current phase associated with inductor current IL56 ₄ remains on. The inductor current phases associated with signals PWM₁ and PWM₂ remain off.

At time t₂, signal PWM₃ transitions to a logic high level, therefore signals PWM₁ and PWM₂ remain at a logic high level, signal PWM₄ remains at a logic low level, and signal PWM₃ is now at a logic high level. Current ordering circuit 65 compares the current levels of currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ at time t₂ with each other and transmits the current level information to pulse assign circuit 60. Current IL56 ₄ still has the lowest current level and current IL56 ₁ still has the highest current level, but current IL56 ₂ now has the second lowest current level and current IL56 ₃ now has the third lowest current level. In other words, current IL56 ₁ has the highest current level, current IL56 ₃ the second highest current level, current IL56 ₂ the third highest current level, and current IL56 ₄ the lowest current level. In response to signal PWM₃ being at a logic high level, pulse assign circuit 60 again determines whether any of the inductor current phases have been turned on, selects the inductor current having the lowest current level from the inductor current phases that are turned-off, i.e., the inductor current phases associated with inductor currents IL56 ₁ and IL56 ₂, and enables a corresponding output 64 ₁, 64 ₂, 64 ₃, and 64 ₄ to conduct a PWM signal in accordance with the inductor current phase associated with the inductor current. Because the inductor current phase associated with inductor currents IL56 ₃ and IL56 ₄ have been turned on, pulse assign circuit 60 selects an inductor current phase from the inductor current phases associated with inductor currents IL56 ₁ and IL56 ₂. Here, inductor current IL56 ₂ is the lowest inductor current hence pulse assign circuit 60 enables output 64 ₂. Thus, in response to signal PWM₃ enabling output 64 ₂, i.e., the output that conducts a PWM signal in accordance with the inductor current phase associated with signal PWM₂, pulse assign circuit 60 swaps the inductor current phase associated with signal PWM₃ for the inductor current phase associated with signal PWM₂, i.e., pulse assign circuit 60 re-assigns the inductor current phase that is transmitted from pulse assign circuit 64. In addition, pulse assign circuit 60 stores information indicating that the inductor current phase associated with inductor current IL56 ₂ has been turned on and that the inductor current phases associated with inductor current IL56 ₃ and IL56 ₄ remain on. The inductor current phase associated with signal PWM1 remains off.

At time t₃, signal PWM₄ transitions to a logic high level, therefore, signals PWM₁, PWM₂, and PWM₃ remain at a logic high level and signal PWM₄ is now also at a logic high level. Current ordering circuit 65 compares the current levels of currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ at time t₃ with each other and transmits the current level information to pulse assign circuit 60. At time t₃, current IL56 ₄ now has the second lowest current level, current IL56 ₃ now has the highest current level, current IL56 ₂ now has the third lowest current level, and current IL56 ₁ now has the lowest current level. In other words, current IL56 ₃ has the highest current level, current IL56 ₂ the second highest current level, current IL56 ₄ the third highest current level, and current IL56 ₁ the lowest current level. In response to signal PWM₄ being at a logic high level, pulse assign circuit 60 again determines whether any of the inductor current phases have been turned on, selects the inductor current having the lowest current level from the inductor current phases that are turned-off, i.e., the inductor current phases associated with inductor current IL56 ₁, and enables a corresponding output 64 ₁, 64 ₂, 64 ₃, and 64 ₄ to conduct a PWM signal in accordance with the inductor current phase associated with the inductor current. Because the inductor current phase associated with inductor currents IL56 ₂, IL56 ₃ and IL56 ₄ have been turned on, pulse assign circuit 60 selects the inductor current phase associated with inductor current IL56 ₁ because it is the one that is not turned on, i.e., it is turned off. Thus pulse assign circuit 60 enables output 64 ₁. In response to signal PWM₄ enabling output 64 ₁, i.e., the output that conducts a PWM signal in accordance with the inductor current phase associated with signal PWM₁, pulse assign circuit 60 swaps the PWM signal that is in accordance with the inductor current phase associated with signal PWM₄ for the PWM signal that is in accordance with the inductor current phase associated with signal PWM₁, i.e., pulse assign circuit 60 re-assigns the inductor current phase that it transmits. In addition, pulse assign circuit 60 stores information indicating that the inductor current phase associated with inductor current IL56 ₁ has been turned on and that the inductor current phases associated with inductor currents IL56 ₂, IL56 ₃, and IL56 ₄ remain on. The inductor current phases associated with signals PWM₂, PWM₃, and PWM₄ remain on.

At time t₄, signal PWM₁ transitions to a logic low level, therefore, signals PWM₂, PWM₃, and PWM₄ remain at a logic high level, whereas signal PWM₁ is now at a logic low level. Current ordering circuit 65 compares the current levels of currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ at time t₄ with each other and transmits the current level information to pulse assign circuit 60. At time t₄, current IL56 ₄ still has the second lowest current level, current IL56 ₃ still has the highest current level, current IL56 ₂ still has the third lowest current level, and current IL56 ₁ still has the lowest current level. In other words, current IL56 ₃ has the highest current level, current IL56 ₂ the second highest current level, current IL56 ₄ the third highest current level, and current IL56 ₁ the lowest current level. In response to signal PWM₁ being at a logic low level, pulse assign circuit 60 determines whether any of the inductor current phases have been turned off. If none of the inductor current phases have been turned off, pulse assign circuit 60 enables output 64 ₃ which then transmits a PWM signal in accordance with the inductor current phase associated with the highest inductor current level to output 64 ₃ of pulse assign circuit 60. If one or more of the inductor current phases has been turned off, pulse assign circuit 60 enables the output to conduct a PWM in accordance with the inductor current phase associated with the current having the highest current level from among the inductor current phases that have been turned on, i.e., pulse assign circuit 60 swaps which output is enabled to an output associated with an inductor having the highest inductor current. Pulse assign circuit 60 enables an output for an inductor current associated with an inductor current phase that has been turned-on.

In this example, all of the inductor current phases are turned-on at time t₄, thus pulse assign circuit 60 enables an output associated with an inductor current having the highest current level and where the associated inductor current phase is turned-on. Accordingly, pulse assign circuit 60 enables its output that is associated with the inductor current having the highest current level, i.e., output 64 ₃. In response to signal PWM₁ transitioning to a logic low level and turning off the inductor current phase associated with current IL56 ₁, pulse assign circuit 60 enables output 64 ₃ which conducts a PWM signal in accordance with inductor current IL56 ₃ rather than enabling output 64 ₁ and conducting a PWM signal in accordance with the inductor current phase associated with current IL56 ₁, i.e., pulse assign circuit 60 turns-off the inductor current phase associated with current IL56 ₃. Pulse assign circuit 60 stores information indicating that the inductor current phase associated with inductor current IL56 ₃ has been turned-off. The inductor current phases associated with signals PWM₁, PWM₂, and PWM₄ remain on.

At time t₅, signal PWM₁ transitions to a logic high level, therefore signals PWM₁, PWM₂, PWM₃, and PWM₄ are at a logic high level. Current ordering circuit 65 compares the current levels of currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ at time t₅ with each other and transmits the current level information to pulse assign circuit 60. At time t₅, current IL56 ₄ has the third lowest current level, current IL56 ₃ has the second lowest current level, current IL56 ₂ has the highest current level, and current IL56 ₁ still has the lowest current level. In other words, current IL56 ₂ has the highest current level, current IL56 ₄ the second highest current level, current IL56 ₃ the third highest current level, and current IL56 ₁ the lowest current level. In response to signal PWM₁ being at a logic high level, pulse assign circuit 60 again determines which of the inductor current phases have been turned off, selects the inductor current having the lowest current level from the inductor current phases that are turned-off, i.e., the inductor current phases associated with inductor current IL56 ₃, and enables a corresponding output 64 ₁, 64 ₂, 64 ₃, and 64 ₄ to conduct a PWM signal in accordance with the inductor current phase associated with the inductor current. Because the inductor current phase associated with inductor current IL56 ₁, IL56 ₂, and IL56 ₄ have been turned on, pulse assign circuit 60 selects the inductor current phase associated with inductor current IL56 ₃. Here, inductor current IL56 ₃ is the lowest inductor current hence pulse assign circuit 60 enables output 64 ₃. In response to signal PWM₁ enabling output 64 ₃ i.e., the output that conducts a PWM signal in accordance with the inductor current phase associated with signal PWM₃, pulse assign circuit 60 swaps the PWM signal that is in accordance with the inductor current phase associated with signal PWM₁ for the PWM signal that is in accordance with the inductor current phase associated with signal PWM₃, i.e., pulse assign circuit 60 re-assigns the PWM signal in accordance with the inductor current phase associated with the current having the lowest current level of the inductor current phases that are off. In addition, pulse assign circuit 60 stores information indicating that the inductor current phase associated with inductor current IL56 ₃ has been turned on and that the inductor current phases associated with inductor currents IL56 ₁, IL56 ₂, and IL56 ₄ remain on. The inductor current phases associated with signals PWM₁, PWM₂, PWM₃, and PWM₄ are on.

At time t₆, signal PWM₂ transitions to a logic low level, therefore signals PWM₁, PWM₃, and PWM₄ remain at a logic high level and signal PWM₂ is now at a logic low level. Current ordering circuit 65 compares the current levels of currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ at time t₆ with each other and transmits the current level information to pulse assign circuit 60. At time t₆, current IL56 ₄ still has the third lowest current level, current IL56 ₃ still has the second lowest current level, current IL56 ₂ still has the highest current level, and current IL56 ₁ still has the lowest current level. In other words, current IL56 ₂ has the highest current level, current IL56 ₄ the second highest current level, current IL56 ₃ the third highest current level, and current IL56 ₁ the lowest current level. In response to signal PWM₂ being at a logic low level, pulse assign circuit 60 determines whether any of the inductor current phases have been turned off. If none of the inductor current phases have been turned off, pulse assign circuit 60 enables output 64 ₂ which then transmits the inductor current phase associated with the highest inductor current level to output 64 ₂ of pulse assign circuit 60. If one or more of the inductor current phases has been turned off, pulse assign circuit 60 enables the output of the inductor current phase associated with the current having the highest current level from among the inductor current phases that have been turned on, i.e., pulse assign circuit 60 swaps which output is enabled to conduct a PWM signal associated with an inductor having the highest inductor current. Pulse assign circuit 60 enables an output for an inductor current associated with an inductor current phase that has been turned-on.

In this example, all of the inductor current phases are turned on at time t₆, thus pulse assign circuit 60 enables an output associated with an inductor current having the highest current level and where the associated inductor current phase is turned on. Accordingly, pulse assign circuit 60 enables its output that is associated with the inductor current having the highest current level, i.e., output 64 ₂, to conduct a PWM signal in accordance with the inductor current phase associated with the current having the highest current level for the inductor current phases that are turned on. In response to signal PWM₂ transitioning to a logic low level and turning off the inductor current phase associated with current IL56 ₂, pulse assign circuit 60 enables output 64 ₂ which conducts inductor current IL56 ₂. Pulse assign circuit 60 stores information indicating that the inductor current phase associated with inductor current IL56 ₂ has been turned-off. The inductor current phases associated with signals PWM₁, PWM₃, and PWM₄ remain on.

At time t₇, signal PWM₃ transitions to a logic low level, therefore signals PWM₁ and PWM₄ remain at logic high levels and signal PWM₂ and PWM₃ are at logic low levels. Current ordering circuit 65 compares the current levels of currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ at time t₇ with each other and transmits the current level information to pulse assign circuit 60. At time t₇, current IL56 ₄ now has the highest current level, current IL56 ₃ still has the third lowest current level, current IL56 ₂ now has the lowest current level, and current IL56 ₁ now has the second lowest current level. In other words, current IL56 ₄ has the highest current level, current IL56 ₃ the second highest current level, current IL56 ₁ the third highest current level, and current IL56 ₂ the lowest current level. In response to signal PWM₃ being at a logic low level, pulse assign circuit 60 determines whether any of the inductor current phases have been turned off. If none of the inductor current phases have been turned off, pulse assign circuit 60 enables output 64 ₄ which then transmits a PWM signal in accordance with the inductor current phase associated with the highest inductor current level to output 64 ₄ of pulse assign circuit 60. If one or more of the inductor current phases has been turned off, pulse assign circuit 60 enables the output to transmit a PWM signal in accordance with the inductor current phase associated with the current having the highest current level from among the inductor current phases that have been turned on, i.e., pulse assign circuit 60 swaps which output is enabled to an output associated with an inductor current phase that is associated with the highest inductor current. Pulse assign circuit 60 enables an output for an inductor current associated with an inductor current phase that has been turned-on.

In this example, the inductor current phase associated with inductor currents IL56 ₁, IL56 ₃, and IL56 ₄ are turned on. Thus, pulse assign circuit 60 selects an inductor current phase from the inductor current phases associated with inductor currents IL56 ₁, IL56 ₃, and IL56 ₄. Because inductor current IL56 ₄ has the highest current level, pulse assign circuit 60 enables output 64 ₄ in response to signal PWM₃ transitioning to a logic low level. Accordingly, pulse assign circuit 60 enables a corresponding output 64 ₁, 64 ₂, 64 ₃, and 64 ₄ to conduct a PWM signal in accordance with an inductor current phase that is associated with the inductor current having the highest current level, i.e., inductor current IL56 ₄, rather than enabling output 64 ₃ to conduct a PWM signal in accordance with an inductor current phase associated with current IL56 ₃, i.e., pulse assign circuit 60 turns-off the inductor current phase associated with current IL56 ₄. Pulse assign circuit 60 stores information indicating that the inductor current phase associated with inductor current IL56 ₄ has been turned-off. The inductor current phases associated with signals PWM₁ and PWM₃ remain on.

At time t₈, signal PWM₄ transitions to a logic low level, therefore signal PWM1 remains at a logic high level and signals PWM₂, PWM₃, and PWM₄ are at logic low levels. Current ordering circuit 65 compares the current levels of currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ at time t₈ with each other and transmits the current level information to pulse assign circuit 60. At time t₈, current IL56 ₄ now has the second lowest current level, current IL56 ₃ has the highest current level, current IL56 ₂ has the lowest current level, and current IL56 ₁ has the third lowest current level. In other words, current IL56 ₃ has the highest current level, current IL56 ₁ the second highest current level, current IL56 ₄ the third highest current level, and current IL56 ₂ the lowest current level. In response to signal PWM₄ being at a logic low level, pulse assign circuit 60 determines whether any of the inductor current phases have been turned off. If none of the inductor current phases have been turned off, pulse assign circuit 60 enables its output 64 ₃ to conduct a PWM signal in accordance with the inductor current phase associated with the highest inductor current level. If one or more of the inductor current phases has been turned off, pulse assign circuit 60 enables the output to transmit a PWM signal in accordance with the inductor current phase associated with the current having the highest current level from among the inductor current phases that have been turned on, i.e., pulse assign circuit 60 swaps which output is enabled to an output associated with a PWM signal in accordance with an inductor current phase associated with the highest inductor current for an inductor current phase that is on. Pulse assign circuit 60 enables an output for an inductor current associated with an inductor current phase that has been turned-on.

In this example, the inductor current phase associated with inductor currents IL56 ₁ and IL56 ₃ are turned on. Thus, pulse assign circuit 60 selects an inductor current phase from the inductor current phases associated with inductor currents IL56 ₁ and IL56 ₃. Because inductor current IL56 ₃ has the highest current level, pulse assign circuit 60 enables a corresponding output 64 ₁, 64 ₂, 64 ₃, and 64 ₄ to conduct a PWM signal in response to signal PWM₄ transitioning to a logic low level. Accordingly, pulse assign circuit 60 enables output 64 ₃ to conduct a PWM signal in accordance with the inductor current phase associated with the inductor current having the highest current level, i.e., pulse assign circuit 60 turns-off the inductor current phase associated with current IL56 ₃. Pulse assign circuit 60 stores information indicating that the inductor current phase associated with inductor current IL56 ₃ has been turned-off. The inductor current phase associated with signal PWM1 remains on.

At time t₉, signal PWM₁ transitions to a logic low level, therefore signals PWM₁, PWM₂, PWM₃, and PWM₄ are at a logic low level. Current ordering circuit 65 compares the current levels of currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ at time t₉ with each other and transmits the current level information to pulse assign circuit 60. At time t₉, current IL56 ₄ has the second lowest current level, current IL56 ₃ has the third lowest current level, current IL56 ₂ has the lowest current level, and current IL56 ₁ still has the highest current level. In other words, current IL56 ₁ has the highest current level, current IL56 ₃ the second highest current level, current IL56 ₄ the third highest current level, and current IL56 ₂ the lowest current level. In response to signal PWM₁ being at a logic low level, pulse assign circuit 60 determines whether any of the inductor current phases have been turned off. If none of the inductor current phases have been turned off, pulse assign circuit 60 enables its output 64 ₁ to transmit a PWM signal in accordance with the inductor current phase associated with the highest inductor current level. If one or more of the inductor current phases has been turned off, pulse assign circuit 60 enables the output to transmit a PWM signal in accordance with the inductor current phase associated with the current having the highest current level from among the inductor current phases that have been turned on, i.e., pulse assign circuit 60 swaps which output is enabled to an output associated with a PWM signal that is in accordance with the inductor current phase associated with the highest inductor current for inductor current phases that are on.

In this example, the inductor current phase associated with inductor current IL56 ₁ is turned on. Thus, pulse assign circuit 60 selects the inductor current phase from the inductor current phases associated with inductor currents IL56 ₁. Because inductor current IL56 ₁ has the highest current level, pulse assign circuit 60 enables output 64 ₁ to transmit a PWM signal in accordance with the inductor current phase associated with inductor current IL56 ₁ in response to signal PWM₁ transitioning to a logic low level, i.e., pulse assign circuit 60 turns-off the inductor current phase associated with current IL56 ₁. Pulse assign circuit 60 stores information indicating that the inductor current phase associated with inductor current IL56 ₁ has been turned-off. The inductor current phases associated with signals PWM₁, PWM₂, PWM₃, and PWM₄ are off. In other words, the inductor current phases associated with inductor currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ have been turned off.

FIG. 3 further illustrates that swapping inductor current phases in accordance with embodiments of the present invention decreases the difference between the highest and lowest inductor current levels. More particularly, FIG. 3 illustrates inductor currents IL56 ₁, IL56 ₂, IL56 ₃, and IL56 ₄ that have been swapped as solid lines and currents ILW56 ₁, ILW56 ₂, ILW56 ₃, and ILW56 ₄ that have not been swapped as broken lines. The difference between the lowest and highest currents that have been swapped is identified by reference character ΔL_S and the difference between the lowest and highest currents that have not been swapped is identified by reference character ΔL_N. Current difference ΔL_S is less than current difference ΔL_N illustrating that a multi-phase power module operating in accordance with embodiments of the present invention balances currents. Another advantage of embodiments of the present invention is conservation of current and power.

By now it should be appreciated that a multi-phase power converter and a method for balancing a plurality of currents in the multi-phase power converter have been provided. In accordance with embodiments of the present invention, current balancing is accomplished by distributing the turn-on and turn-off signals based on a comparison of the phases of inductor currents. By distributing the turn-on and turn-off signals, the total duty cycle delivered to the output is not impacted and current sharing balance can be maintained during dynamic loading. Preferably, the turn-on signal is assigned to the lowest inductor current phase among the turned-off phases and assigning the turn-off signal to the highest inductor current phase among the turned-on phases. An advantage of embodiments in accordance with the present invention is that when the duty cycles of the output signal do not overlap, the turn-on signals control the current sharing; when the duty cycles overlap, both the turn-on and turn-off signals control the current sharing; and when the duty cycles overlap most of the time, the turn-off signals control the current sharing. Assigning the turn-on signal to the lowest inductor current phase results in a larger duty cycle being assigned to the lowest inductor current phase and assigning the turn-off signal to the highest inductor current phase results in a smaller duty cycle being assigned to the highest inductor current phase. This results in a multi-phase system that can rapidly balance the inductor currents on a cycle-by-cycle basis during dynamic loading.

In addition, embodiments of the present invention include a method for balancing current in a multi-phase power converter that uses a plurality of current sharing loops, wherein a first current sharing loop of the plurality of current sharing loops is accurate at a low frequency or DC and a second current sharing loop of the plurality of current sharing loops is accurate under conditions at which a load operates at high frequency, i.e., at a frequency greater than the loop bandwidth of the first current sharing loop. Preferably, the first current sharing loop uses the average value of the currents for balancing current and the second current sharing loop uses the instantaneous current for balancing current. The first current sharing loop, also referred to as a conventional current sharing loop, is capable handling frequencies that are under or within its loop bandwidth. Because the conventional current sharing loop uses the average current to achieve current balancing and the currents are substantially equally distributed at DC there is substantially no error in the currents. The second current sharing loop, also referred to as a switching current sharing loop, is non-linear, regulates current when there is a pulse or switching instance, is capable of handling frequencies that are higher than those that can be handled by the conventional current sharing loop, and is very fast. The switching current loop uses a pulse assign method, thus there can be error within a single switching period. An advantage of including a plurality of current sharing loops is that the conventional current sharing current loop is accurate at frequencies within its current sharing loop bandwidth and the pulse assign or switching current loop is accurate at frequencies greater than the current sharing loop bandwidth of the conventional current sharing current loop. Therefore, the use of a plurality of current sharing loops increases the accuracy of current sharing over a greater frequency range. In accordance with an embodiment of the present invention, the conventional current sharing loop may include output node 50 coupled to PWM circuit 12 through error amplifier 16, whereas the switching current sharing loop may include power stages 34 ₁, . . . , 34 _n, current ordering circuit 65, and pulse assign circuit 60.

Although certain preferred embodiments and methods have been disclosed herein, it will be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of applicable law.

Claims (17)

1. A method for balancing a plurality of currents in a multi-phase power converter having a plurality of outputs, comprising:

providing a plurality of currents, wherein each current of the plurality of currents has an associated phase;

determining whether a phase associated with one or more currents of the plurality of currents is active or inactive;

determining current levels of the plurality of currents, wherein determining the current levels of the plurality of currents includes:

determining which current of the plurality of currents has the lowest current level and further including activating the phase of the current of the plurality of currents that has the lowest current level; and

determining that a first current of the plurality of currents with an associated phase that is inactive has the lowest current level and activating the phase of the first current; and

determining a second current of the plurality of currents with associated phases that are inactive that has the lowest current level and activating the phase of the second current.

2. The method of claim 1, wherein determining whether a phase associated with one or more currents of the plurality of currents is active includes determining that each phase associated with the one or more currents of the plurality of currents is inactive.

3. The method of claim 1, wherein activating the phase associated with the current that has the lowest level includes changing a logic state of a first output of the plurality of outputs.

4. The method of claim 1, wherein activating the phase of the first current that has the lowest current level of the plurality of currents with associated phases that are inactive includes changing a logic state of a second output of the plurality of outputs.

5. The method of claim 1, wherein determining the current levels of the plurality of currents includes determining a third current of the plurality of currents with associated phases that are active that has the highest current level and activating the phase of the first current.

6. The method of claim 5, wherein activating the phase of the third current that has the highest current level of the plurality of currents with associated phases that are active includes changing a logic state of a first output of the plurality of outputs.

7. A method for balancing a plurality of currents in a multi-phase power converter having a plurality of outputs, comprising:

providing a plurality of currents, wherein each current of the plurality of currents has an associated phase;

determining whether a phase associated with one or more currents of the plurality of currents is active or inactive;

determining current levels of the plurality of currents, wherein determining the current levels of the plurality of currents includes:

determining which current of the plurality of currents has the lowest current level and further including activating the phase of the current of the plurality of currents that has the lowest current level; and

determining a first current of the plurality of currents with associated phases that are active that has the highest current level and activating the phase of the first current.

8. The method of claim 7, wherein activating the phase of the first current that has the highest current level of the plurality of currents with associated phases that are active includes changing a logic state of a first output of the plurality of outputs.

9. The method of claim 7, wherein determining whether a phase associated with one or more currents of the plurality of currents is active or inactive includes determining that each phase associated with the one or more currents of the plurality of currents is active.

10. The method of claim 9, wherein determining the current levels of the plurality of currents includes determining which current of the plurality of currents has the highest current level and further including inactivating the phase of the current of the plurality of currents that has the highest current level.

11. The method of claim 10, wherein inactivating the phase of the current that has the lowest level includes changing a logic state of a first output of the plurality of outputs.

12. A method for balancing current in a multi-phase power converter, comprising:

providing the multi-phase power converter having a pulse assign circuit that receives one or more pulse width modulated signals, wherein the pulse assign circuit has one or more outputs;

assigning a first pulse width modulated signal of the one or more pulse width modulated signals to a first output of the one or more outputs of the pulse assign circuit, wherein the first pulse width modulated signal is associated with a first parameter;

providing a second pulse width modulated signal of the one or more pulse width modulated signals, wherein the second pulse width modulated signal is associated with a second parameter;

comparing the first parameter to the second parameter; and

assigning the first pulse width modulated signal to the first output if the first parameter is greater than the second parameter.

13. The method of claim 12, wherein the first parameter is a first current and the second parameter is a second current.

14. A method for balancing current in a multi-phase power converter, comprising balancing the current in the multi-phase power converter by using a plurality of current sharing loops, a first current sharing loop of the plurality of current sharing loops for operating at a frequency less than its current sharing loop bandwidth and a second current sharing loop of the plurality of current sharing loops for operating at a frequency greater than the current sharing loop bandwidth of the first current sharing loop.

15. The method of claim 14, wherein:

the second current sharing loop comprises the multi-phase power converter having a pulse assign circuit that receives one or more pulse width modulated signals, and wherein the pulse assign circuit has one or more outputs; and further including:

assigning a first pulse width modulated signal of the one or more pulse width modulated signals to a first output of the one or more outputs of the pulse assign circuit, wherein the first pulse width modulated signal is associated with a first current level of a first current.

16. The method of claim 15, further including:

providing a second pulse width modulated signal of the one or more pulse width modulated signals, wherein the second pulse width modulated signal is associated with a second current level of a second current;

comparing the first current level to the second current level; and

assigning the first pulse width modulated signal to the first output if the first current level is less than the second current level.

17. The method of claim 15, further including:

providing a second pulse width modulated signal of the one or more pulse width modulated signals, wherein the second pulse width modulated signal is associated with a second current level of a second current;

comparing the first current level to the second current level; and

assigning the first pulse width modulated signal to the first output if the first current level is greater than the second current level.

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