CN109980056A - Gallium nitride based LED epitaxial slice and its manufacturing method - Google Patents

Abstract

The invention discloses a gallium nitride-based light-emitting diode epitaxial wafer and a manufacturing method thereof, belonging to the technical field of semiconductors. The gallium nitride-based light-emitting diode epitaxial wafer includes a substrate, and a low-temperature buffer layer, a three-dimensional nucleation layer, a two-dimensional recovery layer, an undoped GaN layer, an N-type layer, a stress release layer, a multi-layered The quantum well layer, the electron blocking layer, the P-type layer and the P-type contact layer, and the stress release layer includes a plurality of alternately grown first superlattice structures and second superlattice structures, and the first superlattice structure is low-temperature InGaN/ GaN superlattice structure, the second superlattice structure is a high temperature InGaN/GaN superlattice structure. The light-emitting diode epitaxial wafer provided by the invention can optimize the opening size of the V-shaped pit, improve the internal quantum luminous efficiency of the LED, and at the same time improve the crystal quality of the epitaxial layer.

Description

Gallium nitride-based light-emitting diode epitaxial wafer and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductors, in particular to a gallium nitride-based light emitting diode epitaxial wafer and a manufacturing method thereof.

Background technique

LED (Light Emitting Diode, light-emitting diode) is a semiconductor electronic component that can emit light. As a high-efficiency, environmentally friendly and green new solid-state lighting source, LED is being rapidly and widely used in fields such as traffic lights, interior and exterior lights of automobiles, urban landscape lighting, and mobile phone backlights.

Epitaxial wafers are the main components of LEDs. Existing GaN-based LED epitaxial wafers include a sapphire substrate, a low-temperature buffer layer, a three-dimensional nucleation layer, a two-dimensional recovery layer, and an undoped sapphire substrate sequentially stacked on the sapphire substrate. GaN layer, N-type layer, multiple quantum well layer, electron blocking layer, P-type layer and P-type contact layer. Due to the large lattice mismatch between the sapphire substrate and the GaN epitaxial layer, stress will be generated in the epitaxial layer, and then a large number of threading dislocations will be generated. The stress and threading dislocations extend along the stacking direction of the epitaxial wafer to In the multiple quantum well layer, the luminescence of the LED will be seriously affected. In order to improve the luminous efficiency of the LED, a stress release layer is usually arranged between the N-type layer and the multiple quantum well layer to release the underlying stress and reduce the generation of dislocations.

In the process of realizing the present invention, the inventor found that the prior art has at least the following problems:

Because the stress release layer in the prior art is usually grown at a low temperature and constant temperature to ensure its stress release effect. Threading dislocations will lead to the formation of V-type pits at low temperature, and under low temperature conditions, the lateral epitaxy capability of GaN will deteriorate, and the opening of V-type pits will gradually increase. When the opening of the V-shaped pit is too large, the potential barrier height of the inclined surface of the V-shaped pit is reduced, and the carrier confinement ability is weakened, which will lead to non-radiative recombination between electrons and holes, which reduces the internal quantum luminous efficiency of the LED. At the same time, under low temperature conditions, the density of the formed V-shaped pits will gradually increase, resulting in a decrease in the crystal quality of the epitaxial layer.

SUMMARY OF THE INVENTION

The embodiments of the present invention provide a gallium nitride-based light emitting diode epitaxial wafer and a manufacturing method thereof, which can optimize the opening size of the V-shaped pit, improve the internal quantum luminous efficiency of the LED, and simultaneously improve the crystal quality of the epitaxial layer. The technical solution is as follows:

In one aspect, the present invention provides a gallium nitride-based light-emitting diode epitaxial wafer, the gallium nitride-based light-emitting diode epitaxial wafer includes a substrate, and a low-temperature buffer layer and a three-dimensional nucleation layer sequentially grown on the substrate , 2D recovery layer, undoped GaN layer, N-type layer, stress release layer, multiple quantum well layer, electron blocking layer, P-type layer and P-type contact layer,

The stress release layer includes a plurality of alternately grown first superlattice structures and second superlattice structures, the first superlattice structure is a low-temperature InGaN/GaN superlattice structure, and the second superlattice structure is The structure is a high temperature InGaN/GaN superlattice structure.

Further, the thickness of the stress release layer is 100-150 nm.

Further, the multiple quantum well layer includes a first type multiple quantum well layer close to the N-type layer, a third type multiple quantum well layer close to the P type layer, and a first type multiple quantum well layer located at the a second type of multiple quantum well layer between the layer and the third type of multiple quantum well layer;

The first type of multiple quantum well layer is composed of multiple periods of In _a Ga _1-a N/Al _c Ga _1-c N superlattice, and the second type of multiple quantum well layer is composed of multiple periods of In _a Ga _1-a N/GaN superlattice, the third type of multiple quantum well layer is composed of multiple periods of In _a Ga _1-a N/In _b Ga _1-b N superlattice, 0.1<a< 1, 0<b<0.3, b<a, 0<c<0.2.

Further, the thicknesses of the In _a Ga _1-a N layers in the first type quantum well layer, the second type quantum well layer and the third type quantum well layer are all equal.

Further, the Al _c Ga _1-c N layer in the first type of quantum well layer, the GaN layer in the second type of quantum well layer, and the In _b Ga _1- in the third type of quantum well layer _b The thicknesses of the N layers are all equal.

In another aspect, the present invention provides a method for manufacturing a gallium nitride-based light-emitting diode epitaxial wafer, the manufacturing method comprising:

providing a substrate;

growing a low-temperature buffer layer, a three-dimensional nucleation layer, a two-dimensional recovery layer, an undoped GaN layer, and an N-type layer in sequence on the substrate;

A stress release layer is grown on the N-type layer, the stress release layer includes a plurality of alternately grown first superlattice structures and second superlattice structures, and the first superlattice structure is low temperature InGaN/GaN a superlattice structure, wherein the second superlattice structure is a high-temperature InGaN/GaN superlattice structure;

A multiple quantum well layer, an electron blocking layer, a P-type layer and a P-type contact layer are sequentially grown on the stress release layer.

Further, growing a stress release layer on the N-type layer includes:

growing the first superlattice structure at a temperature of 780°C to 880°C;

The second superlattice structure is grown at a temperature of 830°C to 930°C.

Further, the multiple quantum well layer includes a first type multiple quantum well layer close to the N-type layer, a third type multiple quantum well layer close to the P type layer, and a first type multiple quantum well layer located at the a second type of multiple quantum well layer between the layer and the third type of multiple quantum well layer;

The first type of multiple quantum well layer is composed of multiple periods of In _a Ga _1-a N/Al _c Ga _1-c N superlattice, and the second type of multiple quantum well layer is composed of multiple periods of In _a Ga _1-a N/GaN superlattice, the third type of multiple quantum well layer is composed of multiple periods of In _a Ga _1-a N/In _b Ga _1-b N superlattice, 0.1<a< 1, 0<b<0.3, b<a, 0<c<0.2.

Further, the thicknesses of the In _a Ga _1-a N layers in the first type quantum well layer, the second type quantum well layer and the third type quantum well layer are all equal.

Further, the Al _c Ga _1-c N layer in the first type of quantum well layer, the GaN layer in the second type of quantum well layer, and the In _b Ga _1- in the third type of quantum well layer _b The thicknesses of the N layers are all equal.

The beneficial effects brought by the technical solutions provided in the embodiments of the present invention are:

By disposing the stress release layer to include a plurality of alternately grown first superlattice structures and second superlattice structures. The first superlattice structure is a low-temperature InGaN/GaN superlattice structure, and the first superlattice structure is grown at a low temperature, which can ensure that the stress release layer has a good stress release effect. However, when the first superlattice structure is grown at a low temperature, the formation of V-type pits will be induced. Therefore, in the present invention, the second superlattice structure is grown after the first superlattice structure, and the second superlattice structure is high temperature InGaN/ GaN superlattice structure, under high temperature conditions, the lateral epitaxy capability of GaN is enhanced, which can restrain the opening of the V-shaped pit from continuing to increase, so as to control the opening of the V-shaped pit within a suitable range and avoid the excessive opening of the V-shaped pit. large, resulting in a decrease in the internal quantum luminous efficiency of the LED. At the same time, under high temperature conditions, the density of the formed V-shaped pits will gradually decrease, so that the crystal quality of the epitaxial layer can be improved. And the stress release layer in the present invention includes a plurality of alternately grown low-temperature InGaN/GaN superlattice structures and high-temperature InGaN/GaN superlattice structures, and the stress release layer of a single-layer structure (that is, only comprising a low-temperature InGaN/GaN superlattice structure) Compared with a high temperature InGaN/GaN superlattice structure), the opening control effect of the V-type pit is better.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a schematic diagram of an opening structure of a V-type pit in a multiple quantum well layer provided by an embodiment of the present invention;

2 is a schematic structural diagram of a gallium nitride-based light-emitting diode epitaxial wafer provided by an embodiment of the present invention;

3 is a schematic structural diagram of a multiple quantum well layer provided by an embodiment of the present invention;

FIG. 4 is a flowchart of a method for manufacturing a gallium nitride-based light-emitting diode epitaxial wafer according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

1 is a schematic diagram of an opening structure of a V-type pit in a multiple quantum well layer provided by an embodiment of the present invention. As shown in FIG. 1 , ΔL in FIG. 1 represents the distance from the center of the threading dislocation to the edge of the V-type pit. Diffusion distance, ΔE represents the barrier height of the quantum well on the inclined surface of the V-type pit. Due to the large lattice mismatch between the sapphire substrate and the GaN epitaxial layer, a large number of threading dislocations will be generated, and threading dislocations will become the leakage channels of carriers, thereby capturing a small part of the carriers. A non-radiative recombination center is formed, resulting in a decrease in the luminous efficiency of the LED. Threading dislocations can induce the formation of V-shaped pits at low temperature.

When the opening of the V-shaped pit is too small, the ΔL is small, and the diffusion distance from the center of the threading dislocation to the edge of the V-shaped pit will be relatively short, making it easier for carriers to be captured into the center of the threading dislocation; The inclined surface of the V-shaped pit has a higher potential barrier, which has a strong ability to confine carriers and can effectively passivate the non-radiative center of threading dislocations.

When the opening of the V-shaped pit is too large, the △L is large, and the diffusion distance from the center of the threading dislocation to the edge of the V-shaped pit will be relatively long, which can inhibit the carriers from entering the non-radiative recombination center; when the △E is small, the V The potential barrier height of the inclined surface of the pit is reduced, and the confinement ability of carriers is weakened. The threading dislocations will still become the leakage channels of the carriers, and then capture a small part of the carriers to form a non-radiative recombination center, resulting in the LED's degradation. Luminous efficiency decreases.

Therefore, if the opening of the V-shaped pit is too large or too small, the luminous efficiency of the LED will be affected. The embodiments of the present invention provide a gallium nitride-based light emitting diode epitaxial wafer and a manufacturing method thereof, which can optimize the opening size of the V-shaped pit, improve the internal quantum luminous efficiency of the LED, and simultaneously improve the crystal quality of the epitaxial layer.

FIG. 2 is a schematic structural diagram of a GaN-based light-emitting diode epitaxial wafer provided by an embodiment of the present invention. As shown in FIG. 2 , the GaN-based light-emitting diode epitaxial wafer includes a substrate 1 and is sequentially grown on the substrate 1 low temperature buffer layer 2, three-dimensional nucleation layer 3, two-dimensional recovery layer 4, undoped GaN layer 5, N-type layer 6, stress release layer 7, multiple quantum well layer 8, electron blocking layer 9, P-type layer 10 and P-type contact layer 11.

The stress release layer 7 includes a plurality of alternately grown first superlattice structures 71 and second superlattice structures 72 , the first superlattice structure 71 is a low-temperature InGaN/GaN superlattice structure, and the second superlattice structure 72 It is a high temperature InGaN/GaN superlattice structure.

In the embodiment of the present invention, the stress release layer is configured to include a plurality of alternately grown first superlattice structures and second superlattice structures. The first superlattice structure is a low-temperature InGaN/GaN superlattice structure, and the first superlattice structure is grown at a low temperature, which can ensure that the stress release layer has a good stress release effect. However, when the first superlattice structure is grown at a low temperature, the formation of V-type pits will be induced. Therefore, in the present invention, the second superlattice structure is grown after the first superlattice structure, and the second superlattice structure is high temperature InGaN/ GaN superlattice structure, under high temperature conditions, the lateral epitaxy capability of GaN is enhanced, which can restrain the opening of the V-shaped pit from continuing to increase, so as to control the opening of the V-shaped pit within a suitable range and avoid the excessive opening of the V-shaped pit. large, resulting in a decrease in the internal quantum luminous efficiency of the LED. At the same time, under high temperature conditions, the density of the formed V-shaped pits will gradually decrease, so that the crystal quality of the epitaxial layer can be improved. And the stress release layer in the present invention includes a plurality of alternately grown low-temperature InGaN/GaN superlattice structures and high-temperature InGaN/GaN superlattice structures, and the stress release layer of a single-layer structure (that is, only comprising a low-temperature InGaN/GaN superlattice structure) Compared with a high temperature InGaN/GaN superlattice structure), the opening control effect of the V-type pit is better.

It should be noted that, in this embodiment, a better opening size of the V-shaped pit can be deduced from the level of luminous efficiency, wherein the opening diameter of the V-shaped pit is controlled to be between 200 and 300 nm.

Optionally, the stress release layer 7 includes N alternately grown first superlattice structures 71 and second superlattice structures 72 , where 2≦N≦12. If the number of N is too large, the number of switching between low temperature and high temperature will be large, and if the number of N is too small, the opening of the V-shaped pit cannot be effectively controlled.

Illustratively, N=8. At this time, the opening of the V-shaped pit can be effectively controlled, and the growth process of the stress release layer will not be too complicated.

Further, the low temperature InGaN layer 71a in the first superlattice structure 71 and the high temperature InGaN layer 72a in the second superlattice structure 72 are both InxGa1 _{- xN} layers, 0.05<x<0.4. When the content of In is within this value range, the stress-releasing layer has the best effect of stress-releasing.

Optionally, the thicknesses of the first superlattice structure 71 and the second superlattice structure 72 are equal, so as to periodically control the growth of the stress relief layer, so that the opening of the V-shaped pits and the density of the V-shaped pits vary uniformly.

Exemplarily, the thicknesses of the low temperature InGaN layer 71 a in the first superlattice structure 71 and the high temperature InGaN layer 72 a in the second superlattice structure 72 are both 1-2 nm. The thicknesses of the GaN layer 71b in the first superlattice structure 71 and the GaN layer 72b in the second superlattice structure 72 are both 10 to 40 nm.

In other implementations, the thicknesses of the first superlattice structure 71 and the second superlattice structure 72 may also be unequal.

Further, the thickness of the stress release layer 7 is 100-150 nm. If the thickness of the stress relief layer 7 is too thick, the crystal quality of the stress relief layer 7 will decrease, and if the thickness of the stress relief layer 7 is too thick, the effect of stress relief will not be achieved. Setting the thickness of the stress release layer 7 to 100-150 nm can better release the underlying stress while ensuring the crystal quality of the stress release layer 7 .

FIG. 3 is a schematic structural diagram of a multi-quantum well layer provided by an embodiment of the present invention. As shown in FIG. 3 , the multi-quantum well layer 8 includes a first-type multi-quantum well layer 81 close to the N-type layer 6 and a P-type layer close to the The third-type multi-quantum well layer 83 of 10, and the second-type multi-quantum well layer 82 located between the first-type multi-quantum well layer 81 and the third-type multi-quantum well layer 83.

The first type of multiple quantum well layer 81 is composed of multiple periods of In _a Ga _1-a N/Al _c Ga _1-c N superlattices, and the second type of multiple quantum well layer 82 is composed of multiple periods of In _a Ga _{1 -a} N/GaN superlattice, the third type of multiple quantum well layer 83 is composed of multiple periods of In _a Ga _{1- a} N/In _b Ga _1-b N superlattice, 0.1<a<1,0 <b<0.3, b<a, 0<c<0.2.

The relationship between the forbidden band widths of the three materials, AlGaN, GaN, and InbGa1 _{- bN} , is: InGaN<GaN<AlGaN. Therefore, the growth rate of the V-type pits formed in the stress relief layer 7 gradually decreases in the three materials of InGaN, GaN, and AlGaN. Therefore, when AlGaN is used as the barrier layer in the first-type multiple quantum well layer 81 close to the N-type layer 6, the growth rate of the V-type pit is relatively slow, and the opening of the V-type pit can be suppressed from becoming too fast and enlarged from the initial stage, so as to avoid the V-type pit. When the pit extends to the multiple quantum well layer 8 close to the P-type layer 10, the opening becomes too large, and then GaN and InGaN are used as the barrier layers in the second type multiple quantum well layer 82 and the third type multiple quantum well layer 83 in turn. Prevent the opening of the V-shaped pit from being too small. When the opening of the V-shaped pit is too small, the diffusion distance of the threading dislocation to the edge of the V-shaped pit will be shorter, making it easier for carriers to be trapped into the center of the threading dislocation.

Further, the thicknesses of the In _a Ga _1-a N layers in the first type quantum well layer 81 , the second type quantum well layer 82 and the third type quantum well layer 83 are all equal, so that the uniformity of the emission wavelength can be ensured.

Optionally, the In _a Ga _1-a N layer 81a in the first type quantum well layer 81, the In _a Ga _1-a N layer 82a in the second type quantum well layer 82, and the third type quantum well layer 83 The thickness of the In _a Ga _1-a N layers are all 3-4 nm.

Further, the _{AlcGa1 -} cN layer 81b in the first type quantum well layer 81, the GaN layer 82b in the second type quantum well layer 82, and the InbGa1 _{-b in} the third type quantum well layer 83 The thicknesses of the N layers 83b are all equal to facilitate growth and control the opening size of the V-shaped pit.

In other implementations, the _{AlcGa1 -} cN layer 81b in the first type of quantum well layer 81, the GaN layer 82b in the second type of quantum well layer 82, and the _InbGa in the third type of quantum well layer 83 The thickness of the _1-b N layer 83b may also be unequal.

Optionally, the _{AlcGa1 -} cN layer 81b in the first type quantum well layer 81, the GaN layer 82b in the second type quantum well layer 82, and the InbGa1 _{- cN} in the third type quantum well layer 83 _b The thicknesses of the N layers 83b are all 9 to 20 nm.

Alternatively, the substrate 1 may be a sapphire substrate.

Optionally, the low temperature buffer layer 2 may be an AlN buffer layer or a GaN buffer layer.

Optionally, the three-dimensional nucleation layer 3 may be a GaN layer with a thickness of 400-600 nm.

Optionally, the two-dimensional recovery layer 4 may be a GaN layer with a thickness of 500-800 nm.

Optionally, the thickness of the undoped GaN layer 5 is 1˜2 μm.

Optionally, the N-type layer 6 may be a Si-doped GaN layer with a thickness of 1˜2 μm.

Optionally, the thickness of the electron blocking layer 9 may be 20˜100 nm.

Optionally, the P-type layer 10 may be a GaN layer with a thickness of 100-300 nm.

Optionally, the light emitting diode epitaxial wafer may further include a P-type contact layer 11 disposed on the P-type layer 10 . The P-type contact layer 11 can be a heavily Mg-doped GaN layer with a thickness of 50-100 nm.

FIG. 4 is a flowchart of a method for manufacturing a GaN-based light-emitting diode epitaxial wafer provided by an embodiment of the present invention. As shown in FIG. 4 , the manufacturing method includes:

Step 401, providing a substrate.

Wherein, the substrate can be an Al ₂ O ₃ sapphire substrate with [0001] crystal orientation.

Further, step 401 may also include:

The substrate is annealed in a hydrogen atmosphere for 1-10 minutes to clean the surface of the substrate, and then the substrate is subjected to nitridation treatment, and the temperature during the nitridation treatment is controlled at 1000-1200° C.

The manner in which the substrate is annealed depends on the growth manner of the low temperature buffer layer.

When the low temperature buffer layer is deposited by PVD (Physical Vapor Deposition) method, annealing the substrate includes: placing the substrate in the reaction chamber of the PVD equipment, and evacuating the reaction chamber. At the same time, the heating and heating of the substrate is started. When the pressure in the reaction chamber is pumped to less than 1*10 ^-7 torr, the heating temperature is stabilized at 350-750° C., and the substrate is baked for 2-12 minutes.

When the low temperature buffer layer is deposited by MOCVD (Metal-organic Chemical Vapor Deposition) method, the annealing treatment of the substrate includes: placing the substrate in the reaction chamber of the MOCVD equipment, and then in a hydrogen atmosphere The annealing treatment is performed for 10 minutes to clean the surface of the substrate. The annealing temperature is between 1000° C. and 1100° C. and the pressure is between 200torr and 500torr.

Step 402, growing a low temperature buffer layer on the substrate.

The low temperature buffer layer may be a GaN buffer layer or an AlN buffer layer.

When the low-temperature buffer layer is a GaN buffer layer, the MOCVD method can be used to grow the low-temperature buffer layer, including: first, adjusting the temperature in the reaction chamber of the MOCVD equipment to 400-600°C, adjusting the pressure to 200-600torr, and growing 15-35nm Thick GaN buffer layer.

When the low temperature buffer layer is an AlN buffer layer, the low temperature buffer layer can be grown by PVD method, including: adjusting the temperature in the reaction chamber of the PVD equipment to 400-700°C, adjusting the sputtering power to 3000-5000W, and adjusting the pressure to 1 ~10mtorr, grow 15~35nm thick AlN buffer layer.

It should be noted that the undoped GaN layer, N-type layer, stress release layer, multiple quantum well layer, electron blocking layer, P-type layer and P-type contact layer in the epitaxial layer can all be grown by MOCVD. In the specific implementation, the substrate is usually placed on a graphite tray and sent to the reaction chamber of the MOCVD equipment for the growth of the epitaxial material. Therefore, the temperature and pressure controlled in the above growth process actually refer to the temperature and pressure in the reaction chamber. . Specifically, using trimethyl gallium or trimethyl ethyl as the gallium source, triethyl boron as the boron source, high-purity nitrogen as the nitrogen source, trimethyl indium as the indium source, trimethyl aluminum as the aluminum source, N-type The dopant is selected from silane, and the P-type dopant is selected from magnesium locene.

Step 403 , growing a three-dimensional nucleation layer on the low temperature buffer layer.

In this embodiment, the three-dimensional nucleation layer may be a GaN layer.

Exemplarily, the temperature of the reaction chamber is adjusted to 1000-1050° C., the pressure of the reaction chamber is controlled to be 300-600 torr, a three-dimensional nucleation layer with a thickness of 400-600 nm is grown, and the growth time is 10-20 min.

Step 404 , growing a two-dimensional buffer layer on the three-dimensional nucleation layer.

In this embodiment, the two-dimensional buffer layer may be a GaN layer.

Exemplarily, the temperature of the reaction chamber is adjusted to 1050-1150° C., the pressure of the reaction chamber is controlled to be 100-300 torr, a two-dimensional buffer layer with a thickness of 500-800 nm is grown, and the growth time is 20-40 min.

Step 405 , growing an undoped GaN layer on the two-dimensional buffer layer.

Exemplarily, the temperature of the reaction chamber is adjusted to 1050˜1200° C., the pressure of the reaction chamber is controlled to be 100˜300 torr, and an undoped GaN layer with a thickness of 1˜2 μm is grown.

Step 406 , growing an N-type layer on the undoped GaN layer.

In this embodiment, the N-type layer may be a Si-doped GaN layer, and the Si doping concentration may be 10 ¹⁸ cm ^-3 to 10 ²⁰ cm ^-3 .

Exemplarily, the temperature of the reaction chamber is adjusted to 1050-1200° C., the pressure of the reaction chamber is controlled to be 100-300 torr, and an N-type layer with a thickness of 1-2 um is grown.

Step 407 , growing a stress release layer on the N-type layer.

In this embodiment, the stress release layer includes a plurality of alternately grown first superlattice structures and second superlattice structures, the first superlattice structure is a low-temperature InGaN/GaN superlattice structure, and the second superlattice structure is a low-temperature InGaN/GaN superlattice structure. The structure is a high temperature InGaN/GaN superlattice structure.

Optionally, the stress release layer includes N alternately grown first superlattice structures and second superlattice structures, 2≤N≤12.

Further, the low temperature InGaN layer in the first superlattice structure and the high temperature InGaN layer in the second superlattice structure are both InxGa1 _{- xN} layers, 0.05<x<0.4.

Optionally, the thicknesses of the first superlattice structure 71 and the second superlattice structure 72 are equal, so as to periodically control the growth of the stress relief layer, so that the opening of the V-shaped pits and the density of the V-shaped pits vary uniformly.

Exemplarily, the thicknesses of the low temperature InGaN layer in the first superlattice structure and the high temperature InGaN layer in the second superlattice structure are both 1-2 nm. The thicknesses of the GaN layer in the first superlattice structure and the GaN layer in the second superlattice structure are both 10 to 40 nm.

In other implementations, the thicknesses of the first superlattice structure 71 and the second superlattice structure 72 may also be unequal.

Further, the thickness of the stress release layer is 100-150 nm.

Exemplarily, step 407 may include:

At a temperature of 780°C to 880°C, the first superlattice structure is grown.

At a temperature of 830°C to 930°C, the second superlattice structure is grown.

Exemplarily, the pressure of the reaction chamber is controlled at 100-500 torr, and the stress release layer is grown.

Step 408 , growing a multiple quantum well layer on the stress release layer.

The multi-quantum well layer includes a first-type multi-quantum well layer near the N-type layer, a third-type multi-quantum well layer near the P-type layer, and the first-type multi-quantum well layer and the third-type multi-quantum well layer The second type of multiple quantum well layers in between.

The first type of multiple quantum well layer is composed of multiple periods of In _a Ga _1-a N/Al _c Ga _1-c N superlattice, and the second type of multiple quantum well layer is composed of multiple periods of In _a Ga _1-a N/GaN superlattice, the third type of multiple quantum well layer is composed of multiple periods of In _a Ga _1-a N/In _b Ga _1-b N superlattice, 0.1<a<1, 0<b< 0.3, b<a, 0<c<0.2.

Further, the thicknesses of the In _a Ga _1-a N layers in the first type quantum well layer, the second type quantum well layer and the third type quantum well layer are all equal, so that the uniformity of the emission wavelength can be ensured.

Exemplarily, the In a Ga 1-a N layer in the first type of quantum well layer, the In _a Ga _{1-a N} layer in the second type of quantum well layer, and the In _a Ga ₁ in the third type _of quantum well layer _-a The thickness of the N layer is all 3 to 4 nm.

Further, the thicknesses of the _{AlcGa1 -} cN layer in the first type quantum well layer, the GaN layer in the second type quantum well layer and the InbGa1 _{- bN} layer in the third type quantum well layer are all uniform. equal.

Optionally, the thickness of the _{AlcGa1 -} cN layer in the first type of quantum well layer, the GaN layer in the second type of quantum well layer and the InbGa1 _{- bN} layer in the third type of quantum well layer Both are 9 to 20 nm.

In other implementations, an _{AlcGa1 -} cN layer in the first type of quantum well layer, a GaN layer in the second type of quantum well layer, and an InbGa1 _{- bN} layer in the third type of quantum well layer The thicknesses can also be unequal.

Optionally, the In a Ga 1-a N layer in the first type of quantum well layer, the In _a Ga _{1-a N} layer in the second type of quantum well layer, and the In _a Ga ₁ in the third type _of quantum well layer _-a The growth temperature and growth pressure of the N layer are both equal.

Optionally, the growth temperature and growth pressure of the AlGaN layer in the first type quantum well layer, the GaN layer in the second type quantum well layer and the InbGa1 _{- bN} layer in the third type quantum well layer are all equal. .

Illustratively, step 408 may include:

The temperature of the reaction chamber is controlled to be 750-830°C, the pressure of the reaction chamber is 100-500torr, and the In _a Ga _1-a N layer in the first type of quantum well layer and the In _a Ga ₁ -a in the second type of quantum well layer are grown The In _a Ga _1-a N layer in the N layer and the third type of quantum well layer;

The temperature of the reaction chamber is controlled to be 850-900°C, and the pressure of the reaction chamber is 100-500torr, and the _{AlcGa1 -} cN layer in the first type of quantum well layer, the GaN layer in the second type of quantum well layer and the third type of quantum well layer are grown The InbGa1 _{- bN} layer in the quantum well layer.

Step 409 , growing an electron blocking layer on the multiple quantum well layer.

In this embodiment, the electron blocking layer may be a P-type AlGaN layer

Exemplarily, the temperature of the reaction chamber is adjusted to 800-1000° C., the pressure of the reaction chamber is controlled to be 50-500 torr, and an electron blocking layer with a thickness of 20-100 nm is grown.

Step 410, growing a P-type layer on the electron blocking layer.

In this embodiment, the P-type layer is a Mg-doped GaN layer, and the doping concentration of Mg may be 1×10 ¹⁹ to 1×10 ²⁰ cm ⁻³ .

Exemplarily, the temperature of the reaction chamber is adjusted to 850-950° C., the pressure of the reaction chamber is controlled to be 100-300 torr, and a P-type layer with a thickness of 100-300 nm is grown.

Step 411 , growing a P-type contact layer on the P-type layer.

In this embodiment, the P-type contact layer may be a heavily Mg-doped GaN layer.

Exemplarily, the temperature of the reaction chamber is adjusted to 850-1000° C., the pressure of the reaction chamber is controlled to be 100-300 torr, and a P-type contact layer with a thickness of 50-100 nm is grown.

After the above steps are completed, the temperature of the reaction chamber is lowered to 650-850° C., annealed in a nitrogen atmosphere for 5-15 minutes, and then gradually lowered to room temperature to complete the epitaxial growth of the light-emitting diode.

In the embodiment of the present invention, the stress release layer is configured to include a plurality of alternately grown first superlattice structures and second superlattice structures. The first superlattice structure is a low-temperature InGaN/GaN superlattice structure, and the first superlattice structure is grown at a low temperature, which can ensure that the stress release layer has a good stress release effect. However, when the first superlattice structure is grown at a low temperature, the formation of V-type pits will be induced. Therefore, in the present invention, the second superlattice structure is grown after the first superlattice structure, and the second superlattice structure is high temperature InGaN/ GaN superlattice structure, under high temperature conditions, the lateral epitaxy capability of GaN is enhanced, which can restrain the opening of the V-shaped pit from continuing to increase, so as to control the opening of the V-shaped pit within a suitable range and avoid the excessive opening of the V-shaped pit. large, resulting in a decrease in the internal quantum luminous efficiency of the LED. At the same time, under high temperature conditions, the density of the formed V-shaped pits will gradually decrease, so that the crystal quality of the epitaxial layer can be improved. And the stress release layer in the present invention includes a plurality of alternately grown low-temperature InGaN/GaN superlattice structures and high-temperature InGaN/GaN superlattice structures, and the stress release layer of a single-layer structure (that is, only comprising a low-temperature InGaN/GaN superlattice structure) Compared with a high temperature InGaN/GaN superlattice structure), the opening control effect of the V-type pit is better.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention. Inside.

Claims (10)

1. a kind of gallium nitride based LED epitaxial slice, the gallium nitride based LED epitaxial slice include substrate and It successively grows low temperature buffer layer over the substrate, three-dimensional nucleating layer, two-dimentional retrieving layer, undoped GaN layer, N-type layer, answer Power releasing layer, multiple quantum well layer, electronic barrier layer, P-type layer and p-type contact layer, which is characterized in that

The stress release layer includes the first superlattice structure and the second superlattice structure of multiple alternating growths, described the first to surpass Lattice structure is low temperature InGaN/GaN superlattice structure, and second superlattice structure is high temperature InGaN/GaN superlattices knot Structure.

2. gallium nitride based LED epitaxial slice according to claim 1, which is characterized in that the stress release layer With a thickness of 100~150nm.

3. gallium nitride based LED epitaxial slice according to claim 1, which is characterized in that the multiple quantum well layer packet It includes the first kind multiple quantum well layer close to the N-type layer, the third class multiple quantum well layer close to the P-type layer and is located at institute State the second class multiple quantum well layer between first kind multiple quantum well layer and the third class multiple quantum well layer；

The first kind multiple quantum well layer by multiple periods In_aGa_1-aN/Al_cGa_1-cN superlattices composition, the second class volume Sub- well layer by multiple periods In_aGa_1-aN/GaN superlattices composition, the third class multiple quantum well layer is by multiple periods In_aGa_1-aN/In_bGa_1-bN superlattices composition, 0.1 < a < 1,0 <b < 0.3, b < a, 0 < c < 0.2.

4. gallium nitride based LED epitaxial slice according to claim 3, which is characterized in that the first kind Quantum Well In in layer, the second class quantum well layer and the third class quantum well layer_aGa_1-aN layers of thickness is equal.

5. gallium nitride based LED epitaxial slice according to claim 3, which is characterized in that the first kind Quantum Well Al in layer_cGa_1-cN layers, the GaN layer in the second class quantum well layer and the In in the third class quantum well layer_bGa_1-bN layers Thickness be equal.

6. a kind of manufacturing method of gallium nitride based LED epitaxial slice, which is characterized in that the manufacturing method includes:

One substrate is provided；

Successively growing low temperature buffer layer, three-dimensional nucleating layer, two-dimentional retrieving layer, undoped GaN layer, N-type layer over the substrate；

The growth stress releasing layer in the N-type layer, the stress release layer include the first superlattices knot of multiple alternating growths Structure and the second superlattice structure, first superlattice structure are low temperature InGaN/GaN superlattice structure, second superlattices Structure is high temperature InGaN/GaN superlattice structure；

Multiple quantum well layer, electronic barrier layer, P-type layer and p-type contact layer are successively grown on the stress release layer.

7. manufacturing method according to claim 6, which is characterized in that the growth stress releasing layer in the N-type layer, packet It includes:

780 DEG C~880 DEG C at a temperature of, grow first superlattice structure；

830 DEG C~930 DEG C at a temperature of, grow second superlattice structure.

8. manufacturing method according to claim 6, which is characterized in that the multiple quantum well layer includes close to the N-type layer First kind multiple quantum well layer, close to the P-type layer third class multiple quantum well layer and be located at the first kind multiple quantum wells The second class multiple quantum well layer between layer and the third class multiple quantum well layer；

The first kind multiple quantum well layer by multiple periods In_aGa_1-aN/Al_cGa_1-cN superlattices composition, the second class volume Sub- well layer by multiple periods In_aGa_1-aN/GaN superlattices composition, the third class multiple quantum well layer is by multiple periods In_aGa_1-aN/In_bGa_1-bN superlattices composition, 0.1 < a < 1,0 <b < 0.3, b < a, 0 < c < 0.2.

9. manufacturing method according to claim 8, which is characterized in that the first kind quantum well layer, the second class amount In in sub- well layer and the third class quantum well layer_aGa_1-aN layers of thickness is equal.

10. manufacturing method according to claim 8, which is characterized in that the Al in the first kind quantum well layer_cGa_1-cN Layer, the GaN layer in the second class quantum well layer and the In in the third class quantum well layer_bGa_1-bN layers of thickness is equal.