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CN117410409A - Light-emitting diode - Google Patents

Light-emitting diode Download PDF

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Publication number
CN117410409A
CN117410409A CN202311390860.6A CN202311390860A CN117410409A CN 117410409 A CN117410409 A CN 117410409A CN 202311390860 A CN202311390860 A CN 202311390860A CN 117410409 A CN117410409 A CN 117410409A
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layer
sub
impurity
doped
emitting diode
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CN117410409B (en
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朱涛
程志青
芦玲
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Huaian Aucksun Optoelectronics Technology Co Ltd
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Huaian Aucksun Optoelectronics Technology Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/815Bodies having stress relaxation structures, e.g. buffer layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/811Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/822Materials of the light-emitting regions
    • H10H20/824Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
    • H10H20/8252Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN characterised by the dopants

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  • Led Devices (AREA)

Abstract

The invention relates to the technical field of semiconductors, in particular to a light-emitting diode. The light-emitting diode comprises a substrate, a buffer layer, an N-type semiconductor layer, a stress release layer, a multi-quantum well light-emitting layer and a P-type semiconductor layer; the stress release layer comprises a first sub-layer and a second sub-layer which are arranged on the N-type semiconductor layer in a stacking way at least one period; the first sub-layer comprises at least two of a GaN layer doped with a first impurity, an undoped GaN layer and an InGaN layer; the second sub-layer is an AlGaN layer. According to the invention, the AlGaN layer is arranged, so that the forbidden bandwidth of the stress release layer can be increased, the potential barrier is increased, and the probability of holes penetrating from the bottom of the V-shaped pit to the stress release layer under high current density is greatly reduced; the existence of the high potential barrier enables the current distribution to be more uniform when electrons enter the multi-quantum well luminous layer; and the higher potential barrier also increases the effect of dislocation shielding, reduces the non-radiative recombination probability and improves the light efficiency.

Description

一种发光二极管a light emitting diode

本发明申请是申请日为2022年02月17日、申请号为2022101466319、发明名称为“一种发光二极管”的分案申请。The application for this invention is a divisional application with a filing date of February 17, 2022, an application number of 2022101466319, and an invention title of “A Light-Emitting Diode”.

技术领域Technical field

本发明涉及半导体技术领域,具体而言,涉及一种发光二极管。The present invention relates to the field of semiconductor technology, and specifically to a light-emitting diode.

背景技术Background technique

发光二极管((Light Emitting Diode,简为LED),可高效地将电能转化为光能,是一种发光器件,通过电子与空穴复合释放能量发光,其在照明、显示器等领域应用广泛。Light Emitting Diode (LED) can efficiently convert electrical energy into light energy. It is a light-emitting device that releases energy to emit light through the recombination of electrons and holes. It is widely used in lighting, displays and other fields.

外延片作为LED的核心部分,近年来受到越来越多的关注和研究。目前常用的外延片的结构包括:衬底、N型GaN半导体层、应力释放层、多量子阱多量子阱发光层和P型GaN半导体层。As the core part of LED, epitaxial wafer has received more and more attention and research in recent years. The structures of currently commonly used epitaxial wafers include: substrate, N-type GaN semiconductor layer, stress relief layer, multi-quantum well multi-quantum well light-emitting layer and P-type GaN semiconductor layer.

其中,在GaN低温生长时Ga原子的横向迁移能力较弱,从而容易引发穿透位错形成V型缺陷。V型凹坑作为空穴传输通道,有利于提高空穴电子复合效率。Among them, when GaN is grown at low temperature, the lateral migration ability of Ga atoms is weak, which easily causes threading dislocations to form V-type defects. The V-shaped pits serve as hole transmission channels, which are beneficial to improving the hole and electron recombination efficiency.

但是,借助V型凹坑空穴传输的作用,在大电流密度下,空穴会从V型坑底部穿透到应力释放层,在应力释放层中与电子发生复合。应力释放层中的禁带宽度与多量子阱发光层的禁带宽度不同,导致此处的发光波长与多量子阱不一致,会导致器件发光集中性变差,发光光谱的半宽变大,光效下降。However, with the help of V-shaped pit hole transport, under high current density, holes will penetrate from the bottom of the V-shaped pit to the stress release layer and recombine with electrons in the stress release layer. The bandgap width in the stress release layer is different from the bandgap width of the multi-quantum well light-emitting layer, which results in the emission wavelength here being inconsistent with the multi-quantum well. This will lead to poor luminescence concentration of the device, and the half-width of the luminescence spectrum will become larger. Effectiveness decreases.

有鉴于此,特提出本发明。In view of this, the present invention is proposed.

发明内容Contents of the invention

本发明的第一目的在于提供一种发光二极管,通过在应力释放层中设置AlGaN层,能够提高应力释放层的禁带宽度,提高势垒,极大的降低在大电流密度下空穴从V型坑底部穿透到应力释放层的概率;高势垒的存在使得电子进入多量子阱发光层时,电流分布更加均匀;同时,更高的势垒还增加了对位错屏蔽的效果,降低非辐射复合概率,提高光效。The first object of the present invention is to provide a light-emitting diode. By arranging an AlGaN layer in the stress release layer, the bandgap width of the stress release layer can be increased, the potential barrier can be increased, and the holes can be greatly reduced from V under high current density. The probability of the bottom of the pit penetrating into the stress release layer; the existence of a high potential barrier makes the current distribution more uniform when electrons enter the multi-quantum well light-emitting layer; at the same time, a higher potential barrier also increases the dislocation shielding effect and reduces Non-radiative recombination probability to improve light efficiency.

为了实现本发明的上述目的,特采用以下技术方案:In order to achieve the above objects of the present invention, the following technical solutions are adopted:

本发明提供了一种发光二极管,包括衬底,以及在所述衬底表面依次层叠设置的缓冲层、N型半导体层、应力释放层、多量子阱发光层和P型半导体层;The invention provides a light-emitting diode, which includes a substrate, a buffer layer, an N-type semiconductor layer, a stress release layer, a multi-quantum well light-emitting layer and a P-type semiconductor layer that are sequentially stacked on the surface of the substrate;

其中,所述应力释放层包括在所述N型半导体层上至少一个周期层叠设置的第一子层和第二子层;Wherein, the stress relief layer includes a first sub-layer and a second sub-layer arranged in at least one periodic stack on the N-type semiconductor layer;

所述第一子层包括掺杂第一杂质的GaN层、未掺杂的GaN层和InGaN层中的至少两种;The first sub-layer includes at least two of a GaN layer doped with a first impurity, an undoped GaN layer and an InGaN layer;

所述第二子层为AlGaN层。The second sub-layer is an AlGaN layer.

优选地,所述应力释放层包括在所述N型半导体层上2~5个周期层叠设置的第一子层和第二子层。Preferably, the stress relief layer includes a first sub-layer and a second sub-layer stacked on the N-type semiconductor layer for 2 to 5 periods.

优选地,所述应力释放层包括依次层叠设置在所述N型半导体层上呈周期性交替生长的掺杂第一杂质的GaN层、未掺杂的GaN层、InGaN层和AlGaN层;Preferably, the stress relief layer includes a first impurity-doped GaN layer, an undoped GaN layer, an InGaN layer and an AlGaN layer that are sequentially stacked on the N-type semiconductor layer and grown periodically alternately;

或者,所述应力释放层包括依次层叠设置在所述N型半导体层上呈周期性交替生长的掺杂第一杂质的GaN层、InGaN层和AlGaN层;Alternatively, the stress relief layer includes a first impurity-doped GaN layer, an InGaN layer and an AlGaN layer that are sequentially stacked on the N-type semiconductor layer and grow periodically alternately;

或者,所述应力释放层包括依次层叠设置在所述N型半导体层上呈周期性交替生长的未掺杂的GaN层、InGaN层和AlGaN层;Alternatively, the stress relief layer includes an undoped GaN layer, an InGaN layer and an AlGaN layer that are sequentially stacked on the N-type semiconductor layer and grow periodically alternately;

或者,所述应力释放层包括依次层叠设置在所述N型半导体层上呈周期性交替生长的掺杂第一杂质的GaN层、未掺杂的GaN层和AlGaN层。Alternatively, the stress relief layer includes a first impurity-doped GaN layer, an undoped GaN layer and an AlGaN layer that are sequentially stacked on the N-type semiconductor layer and grow periodically alternately.

优选地,所述掺杂第一杂质的GaN层的厚度为 Preferably, the thickness of the GaN layer doped with the first impurity is

和/或,所述未掺杂的GaN层的厚度为 And/or, the thickness of the undoped GaN layer is

和/或,所述InGaN层的厚度为 And/or, the thickness of the InGaN layer is

和/或,所述AlGaN层的厚度为 And/or, the thickness of the AlGaN layer is

优选地,所述掺杂第一杂质的GaN层中的所述第一杂质包括碳和/或硅;Preferably, the first impurity in the first impurity-doped GaN layer includes carbon and/or silicon;

优选地,所述碳的掺杂浓度为1×1017~5×1017atoms/cm3Preferably, the carbon doping concentration is 1×10 17 to 5×10 17 atoms/cm 3 ;

优选地,所述硅的掺杂浓度为1×1018~5×1018atoms/cm3Preferably, the doping concentration of silicon is 1×10 18 to 5×10 18 atoms/cm 3 .

优选地,所述第一子层为周期性结构,所述第一子层包括2~5个周期交替层叠设置的掺杂第一杂质的GaN层和未掺杂GaN层;Preferably, the first sub-layer has a periodic structure, and the first sub-layer includes 2 to 5 cycles of alternately stacked GaN layers doped with the first impurity and undoped GaN layers;

或者,所述第一子层包括交替层叠设置的掺杂第一杂质的GaN层和InGaN层;Alternatively, the first sub-layer includes alternately stacked GaN layers and InGaN layers doped with the first impurity;

或者,所述第一子层包括交替层叠设置的未掺杂的GaN层和InGaN层;Alternatively, the first sub-layer includes undoped GaN layers and InGaN layers that are alternately stacked;

或者,所述第一子层包括交替层叠设置的掺杂第一杂质的GaN层、未掺杂的GaN层和InGaN层。Alternatively, the first sub-layer includes an alternately stacked GaN layer doped with the first impurity, an undoped GaN layer and an InGaN layer.

优选地,所述应力释放层包括第一子层和第二子层,其中,所述第一子层为周期性结构,所述第二子层为单层结构,所述第二子层设置在所述第一子层和所述多量子阱发光层之间。Preferably, the stress relief layer includes a first sub-layer and a second sub-layer, wherein the first sub-layer has a periodic structure, the second sub-layer has a single-layer structure, and the second sub-layer is provided between the first sub-layer and the multi-quantum well light-emitting layer.

优选地,所述AlGaN层中还掺杂有硅;Preferably, the AlGaN layer is also doped with silicon;

优选地,所述硅的掺杂浓度为1×1018~5×1018atoms/cm3Preferably, the doping concentration of silicon is 1×10 18 to 5×10 18 atoms/cm 3 .

优选地,所述N型半导体层包括非掺杂GaN层和/或掺杂第二杂质的N型GaN层;Preferably, the N-type semiconductor layer includes an undoped GaN layer and/or an N-type GaN layer doped with a second impurity;

优选地,所述第二杂质包括Si;Preferably, the second impurity includes Si;

优选地,所述第二杂质的掺杂浓度为1×1019~5×1019atoms/cm3Preferably, the doping concentration of the second impurity is 1×10 19 to 5×10 19 atoms/cm 3 .

优选地,所述P型半导体层包括掺杂第三杂质的P型GaN层;Preferably, the P-type semiconductor layer includes a P-type GaN layer doped with a third impurity;

优选地,所述第三杂质包括Mg;Preferably, the third impurity includes Mg;

优选地,所述第三杂质的掺杂浓度为1×1019~1×1021atoms/cm3Preferably, the doping concentration of the third impurity is 1×10 19 to 1×10 21 atoms/cm 3 .

与现有技术相比,本发明的有益效果为:Compared with the prior art, the beneficial effects of the present invention are:

(1)本发明所提供的发光二极管,通过在应力释放层中设置AlGaN层,增加了应力释放层处的禁带宽度,提高了势垒,极大地降低了在大电流密度下空穴从V型坑底部穿透到应力释放层的概率,降低发光光谱半宽。高势垒的存在使得电子进入多量子阱发光层时,电流分布更加均匀;同时,更高的势垒还增加了对位错屏蔽的效果,降低了非辐射复合概率,提高了发光效率。(1) The light-emitting diode provided by the present invention, by arranging an AlGaN layer in the stress release layer, increases the bandgap width at the stress release layer, improves the potential barrier, and greatly reduces the hole flow from V under high current density. The probability that the bottom of the pit penetrates into the stress release layer reduces the half-width of the luminescence spectrum. The existence of a high potential barrier makes the current distribution more uniform when electrons enter the multi-quantum well light-emitting layer; at the same time, a higher potential barrier also increases the dislocation shielding effect, reduces the probability of non-radiative recombination, and improves the luminous efficiency.

(2)本发明所提供的发光二极管,通过设置InGaN层,该层中的In作为V-pits(V形坑)的起始点,有利于生成V-pits,增加V-pits密度。(2) In the light-emitting diode provided by the present invention, by providing an InGaN layer, In in this layer serves as the starting point of V-pits (V-shaped pits), which is beneficial to the generation of V-pits and increases the density of V-pits.

(3)本发明所提供的发光二极管,通过设置掺杂第一杂质的GaN层,能充分释放底层应力,为AlGaN层的生长提供低应力的生长基础,提高AlGaN层的长晶质量。(3) The light-emitting diode provided by the present invention can fully release the underlying stress by arranging the GaN layer doped with the first impurity, provide a low-stress growth foundation for the growth of the AlGaN layer, and improve the crystal growth quality of the AlGaN layer.

附图说明Description of the drawings

为了更清楚地说明本发明具体实施方式或现有技术中的技术方案,下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施方式,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly explain the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description The drawings illustrate some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting any creative effort.

图1为本发明提供的发光二极管的结构示意图;Figure 1 is a schematic structural diagram of a light-emitting diode provided by the present invention;

图2为本发明提供的发光二极管产生V型缺陷的结构示意图;Figure 2 is a schematic structural diagram of a V-shaped defect generated by the light-emitting diode provided by the present invention;

图3为本发明提供的另一发光二极管产生V型缺陷的结构示意图;Figure 3 is a schematic structural diagram of another light-emitting diode provided by the present invention that generates V-shaped defects;

图4为本发明实施例1提供的发光二极管的结构示意图;Figure 4 is a schematic structural diagram of a light-emitting diode provided in Embodiment 1 of the present invention;

图5为本发明实施例1提供的发光二极管的应力释放层的结构示意图;Figure 5 is a schematic structural diagram of the stress release layer of the light-emitting diode provided in Embodiment 1 of the present invention;

图6为本发明实施例2提供的发光二极管的应力释放层的结构示意图;Figure 6 is a schematic structural diagram of the stress release layer of the light-emitting diode provided in Embodiment 2 of the present invention;

图7为本发明实施例3提供的发光二极管的应力释放层的结构示意图;Figure 7 is a schematic structural diagram of the stress release layer of the light-emitting diode provided in Embodiment 3 of the present invention;

图8为本发明实施例4提供的发光二极管的应力释放层的结构示意图;Figure 8 is a schematic structural diagram of the stress release layer of the light-emitting diode provided in Embodiment 4 of the present invention;

图9为本发明实施例5提供的发光二极管的局部结构示意图;Figure 9 is a partial structural schematic diagram of a light-emitting diode provided in Embodiment 5 of the present invention;

图10为本发明实施例6提供的发光二极管的局部结构示意图;Figure 10 is a partial structural diagram of a light-emitting diode provided in Embodiment 6 of the present invention;

图11为本发明实施例7提供的发光二极管的局部结构示意图;Figure 11 is a partial structural diagram of a light-emitting diode provided in Embodiment 7 of the present invention;

图12为本发明实施例8提供的发光二极管的局部结构示意图。FIG. 12 is a partial structural diagram of a light-emitting diode provided in Embodiment 8 of the present invention.

附图标记:Reference signs:

10-衬底; 20-缓冲层; 30-N型半导体层;10-Substrate; 20-Buffer layer; 30-N-type semiconductor layer;

301-非掺杂GaN层; 302-掺杂Si的N型GaN层; 40-应力释放层;301-Non-doped GaN layer; 302-Si-doped N-type GaN layer; 40-Stress release layer;

401-掺杂第一杂质的GaN层; 402-未掺杂的GaN层; 403-InGaN层;401-GaN layer doped with the first impurity; 402-Undoped GaN layer; 403-InGaN layer;

404-AlGaN层; 50-多量子阱发光层; 60-P型半导体层;404-AlGaN layer; 50-multiple quantum well light-emitting layer; 60-P-type semiconductor layer;

601-P型AlGaN电子阻挡层; 602-掺杂Mg的P型GaN层。601-P-type AlGaN electron blocking layer; 602-Mg-doped P-type GaN layer.

具体实施方式Detailed ways

下面将结合附图和具体实施方式对本发明的技术方案进行清楚、完整地描述,但是本领域技术人员将会理解,下列所描述的实施例是本发明一部分实施例,而不是全部的实施例,仅用于说明本发明,而不应视为限制本发明的范围。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。实施例中未注明具体条件者,按照常规条件或制造商建议的条件进行。所用试剂或仪器未注明生产厂商者,均为可以通过市售购买获得的常规产品。The technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings and specific implementation modes. However, those skilled in the art will understand that the following described embodiments are some of the embodiments of the present invention, rather than all of them. They are only used to illustrate the invention and should not be construed as limiting the scope of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention. If the specific conditions are not specified in the examples, the conditions should be carried out according to the conventional conditions or the conditions recommended by the manufacturer. If the manufacturer of the reagents or instruments used is not indicated, they are all conventional products that can be purchased commercially.

本发明提供了一种发光二极管,如图1所示,所述发光二极管包括衬底10,以及在所述衬底10表面依次层叠设置的缓冲层20、N型半导体层30、应力释放层40、多量子阱发光层50和P型半导体层60;The present invention provides a light-emitting diode. As shown in Figure 1, the light-emitting diode includes a substrate 10, and a buffer layer 20, an N-type semiconductor layer 30, and a stress relief layer 40 that are sequentially stacked on the surface of the substrate 10. , multi-quantum well light-emitting layer 50 and P-type semiconductor layer 60;

其中,所述应力释放层40包括在所述N型半导体层30上至少一个周期层叠设置的第一子层和第二子层;Wherein, the stress relief layer 40 includes a first sub-layer and a second sub-layer arranged in at least one periodic stack on the N-type semiconductor layer 30;

所述第一子层包括掺杂第一杂质的GaN层、未掺杂的GaN层和InGaN层中的至少两种;The first sub-layer includes at least two of a GaN layer doped with a first impurity, an undoped GaN layer and an InGaN layer;

所述第二子层为AlGaN层。The second sub-layer is an AlGaN layer.

在GaN低温生长时,Ga原子的横向迁移能力较弱,从而容易引发穿透位错形成V型缺陷。V型缺陷提供了空穴传输通道,P型层产生的空穴,可以通过V型缺陷传输到多量子阱发光层,如图2中C1所示。但是,大电流密度下,空穴有一定概率通过V型缺陷传输到应力释放层中,与应力释放层中的电子发生复合,如图2中C2所示;而传输到应力释放层中的空穴与电子发生复合所产生的发光波长与多量子阱发光层中产生的发光波长不一致,会导致器件发光集中性变差,发光光谱的半宽变大,光效下降。When GaN is grown at low temperature, the lateral migration ability of Ga atoms is weak, which easily causes threading dislocations to form V-type defects. The V-type defect provides a hole transmission channel, and the holes generated in the P-type layer can be transported to the multi-quantum well light-emitting layer through the V-type defect, as shown in C1 in Figure 2. However, under high current density, holes have a certain probability of being transmitted to the stress release layer through V-shaped defects and recombination with electrons in the stress release layer, as shown in C2 in Figure 2; while holes transmitted to the stress release layer The luminescence wavelength produced by the recombination of holes and electrons is inconsistent with the luminescence wavelength produced in the multi-quantum well luminescent layer, which will cause the device's luminescence concentration to become worse, the half-width of the luminescence spectrum to become larger, and the light efficiency to decrease.

为了解决上述问题,本发明通过在应力释放层40中设置第二子层,即AlGaN层,增加了应力释放层40处的禁带宽度,提高了势垒,极大地降低了在大电流密度下空穴从V型坑底部穿透到应力释放层40的概率,降低发光光谱半宽,如图3所示,高势垒的存在使得电子进入多量子阱发光层时,电流分布更加均匀;同时,更高的势垒还增加了对位错屏蔽的效果,降低了非辐射复合概率,提高了发光效率。In order to solve the above problems, the present invention increases the bandgap width at the stress release layer 40 by arranging a second sub-layer, that is, the AlGaN layer, in the stress release layer 40, improves the potential barrier, and greatly reduces the energy consumption under high current density. The probability of holes penetrating from the bottom of the V-shaped pit to the stress release layer 40 reduces the half-width of the luminescence spectrum. As shown in Figure 3, the existence of a high potential barrier makes the current distribution more uniform when electrons enter the multi-quantum well luminescent layer; at the same time , a higher potential barrier also increases the effect of dislocation shielding, reduces the probability of non-radiative recombination, and improves luminous efficiency.

可见,本申请解决了现有技术中存在的大电流密度下光效低的技术问题。It can be seen that this application solves the technical problem of low light efficiency under high current density existing in the prior art.

此外,所述InGaN层中的In作为V-pits(V形坑)的起始点,有利于生成V-pits,增加V-pits密度。In addition, In in the InGaN layer serves as the starting point of V-pits (V-shaped pits), which is beneficial to the generation of V-pits and increases the density of V-pits.

所述掺杂第一杂质的GaN层能充分释放底层应力,为所述第二子层的生长提供低应力的生长基础,提高AlGaN层的长晶质量。The GaN layer doped with the first impurity can fully release the underlying stress, provide a low-stress growth foundation for the growth of the second sub-layer, and improve the crystal growth quality of the AlGaN layer.

在本发明一些具体的实施例中,所述应力释放层40包括在所述N型半导体层30上2~5个周期(还可以选择3个周期或4个周期)层叠设置的第一子层和第二子层。In some specific embodiments of the present invention, the stress relief layer 40 includes a first sub-layer stacked on the N-type semiconductor layer 30 for 2 to 5 cycles (3 cycles or 4 cycles can also be selected). and the second sub-layer.

在本发明一些具体的实施例中,所述应力释放层40包括依次层叠设置在所述N型半导体层30上呈周期性交替生长的掺杂第一杂质的GaN层401、未掺杂的GaN层402、InGaN层403和AlGaN层404。In some specific embodiments of the present invention, the stress relief layer 40 includes GaN layers 401 doped with first impurities and undoped GaN layers that are sequentially stacked on the N-type semiconductor layer 30 to grow periodically and alternately. layer 402, InGaN layer 403 and AlGaN layer 404.

其中,通过预先生长掺杂第一杂质的GaN层401,能够充分释放底层应力,为后续所述第二子层(即AlGaN层404)的生长提供低应力的生长基础,提高AlGaN层404的长晶质量。Among them, by pre-growing the GaN layer 401 doped with the first impurity, the underlying stress can be fully released, providing a low-stress growth foundation for the subsequent growth of the second sub-layer (i.e., the AlGaN layer 404), and improving the length of the AlGaN layer 404. crystal quality.

所述InGaN层403中的In作为V-pits的起始点,有利于生成V-pits,增加V-pits(V形坑)密度。In in the InGaN layer 403 serves as the starting point of V-pits, which is beneficial to the generation of V-pits and increases the density of V-pits (V-shaped pits).

而未掺杂的GaN层402作为所述掺杂第一杂质的GaN层401和所述InGaN层403的过渡层,其能够防止缺陷穿透延伸到InGaN层403,提高InGaN层403的生长质量。The undoped GaN layer 402 serves as a transition layer between the first impurity-doped GaN layer 401 and the InGaN layer 403, which can prevent defects from penetrating and extending to the InGaN layer 403, thereby improving the growth quality of the InGaN layer 403.

或者,所述应力释放层40包括依次层叠设置在所述N型半导体层30上呈周期性交替生长的掺杂第一杂质的GaN层401、InGaN层403和AlGaN层404。Alternatively, the stress relief layer 40 includes a first impurity-doped GaN layer 401 , an InGaN layer 403 and an AlGaN layer 404 that are sequentially stacked on the N-type semiconductor layer 30 and grow periodically alternately.

或者,所述应力释放层40包括依次层叠设置在所述N型半导体层30上呈周期性交替生长的未掺杂的GaN层402、InGaN层403和AlGaN层404。Alternatively, the stress relief layer 40 includes an undoped GaN layer 402 , an InGaN layer 403 and an AlGaN layer 404 that are sequentially stacked on the N-type semiconductor layer 30 and grow periodically alternately.

或者,所述应力释放层40包括依次层叠设置在所述N型半导体层30上呈周期性交替生长的掺杂第一杂质的GaN层401、未掺杂的GaN层402和AlGaN层404。Alternatively, the stress relief layer 40 includes a GaN layer 401 doped with a first impurity, an undoped GaN layer 402 and an AlGaN layer 404 that are sequentially stacked on the N-type semiconductor layer 30 and grow periodically alternately.

在本发明一些具体的实施例中,所述掺杂第一杂质的GaN层401的厚度为包括但不限于/> 中的任意一者的点值或任意两者之间的范围值。In some specific embodiments of the present invention, the thickness of the GaN layer 401 doped with the first impurity is Including but not limited to/> A pip value of either or a range of values between any two.

和/或,所述未掺杂的GaN层402的厚度为包括但不限于 And/or, the thickness of the undoped GaN layer 402 is including but not limited to

中的任意一者的点值或任意两者之间的范围值。 A pip value of either or a range of values between any two.

和/或,所述InGaN层403的厚度为包括但不限于/> 中的任意一者的点值或任意两者之间的范围值。And/or, the thickness of the InGaN layer 403 is Including but not limited to/> A pip value of either or a range of values between any two.

和/或,所述AlGaN层404的厚度为包括但不限于/> 中的任意一者的点值或任意两者之间的范围值。And/or, the thickness of the AlGaN layer 404 is Including but not limited to/> A pip value of either or a range of values between any two.

在本发明一些具体的实施例中,所述掺杂第一杂质的GaN层401中的所述第一杂质包括碳和/或硅。In some specific embodiments of the present invention, the first impurity in the first impurity-doped GaN layer 401 includes carbon and/or silicon.

优选地,所述第一杂质选自碳,或者,所述第一杂质选自碳和硅的混合。其中,碳元素所起到的作用是:GaN层中掺杂C会降低该层的生长质量,有利于底层应力的释放。同时,C掺杂不会对能带结构产生影响。Preferably, the first impurity is selected from carbon, or the first impurity is selected from a mixture of carbon and silicon. Among them, the role of the carbon element is: doping C in the GaN layer will reduce the growth quality of the layer, which is beneficial to the release of underlying stress. At the same time, C doping will not affect the energy band structure.

优选地,所述碳的掺杂浓度为1×1017~5×1017atoms/cm3;包括但不限于2×1017atoms/cm3、3×1017atoms/cm3、4×1017atoms/cm3中的任意一者的点值或任意两者之间的范围值。Preferably, the doping concentration of the carbon is 1×10 17 to 5×10 17 atoms/cm 3 ; including but not limited to 2×10 17 atoms/cm 3 , 3×10 17 atoms/cm 3 , and 4×10 17 atoms/cm A point value of any one of 3 or any range value in between.

优选地,所述硅的掺杂浓度为1×1018~5×1018atoms/cm3,包括但不限于2×1018atoms/cm3、3×1018atoms/cm3、4×1018atoms/cm3中的任意一者的点值或任意两者之间的范围值。Preferably, the doping concentration of the silicon is 1×10 18 to 5×10 18 atoms/cm 3 , including but not limited to 2×10 18 atoms/cm 3 , 3×10 18 atoms/cm 3 , and 4×10 18 atoms/cm A point value of any one of 3 or any range value in between.

在本发明一些具体的实施例中,采用离子注入的方法生长所述掺杂第一杂质的GaN层401。In some specific embodiments of the present invention, an ion implantation method is used to grow the GaN layer 401 doped with the first impurity.

其中,离子注入技术是指将所注元素的气体或蒸气通入电离室电离后形成正离子,然后将正离子从电离室引出进入高压电场中加速,使其得到很高速度而打入半导体中的物理过程。离子注入具有以下优点:能够保证掺杂离子具有极高的纯度、注入离子的浓度和深度分布精确可控、可实现大面积均匀注入、注入离子时衬底温度可自由选择以及离子注入掺杂深度小。Among them, ion implantation technology refers to passing the gas or vapor of the injected element into an ionization chamber to ionize it to form positive ions, and then lead the positive ions from the ionization chamber into a high-voltage electric field to accelerate, so that they can reach a very high speed and be driven into the semiconductor. physical process. Ion implantation has the following advantages: it can ensure extremely high purity of doped ions, the concentration and depth distribution of implanted ions can be precisely controlled, uniform implantation can be achieved over a large area, the substrate temperature can be freely selected during ion implantation, and the ion implantation doping depth can be freely selected. Small.

优选地,所述第一子层为周期性结构,所述第一子层包括2~5个周期交替层叠设置的掺杂第一杂质的GaN层和未掺杂GaN层;Preferably, the first sub-layer has a periodic structure, and the first sub-layer includes 2 to 5 cycles of alternately stacked GaN layers doped with the first impurity and undoped GaN layers;

或者,所述第一子层包括交替层叠设置的掺杂第一杂质的GaN层和InGaN层;Alternatively, the first sub-layer includes alternately stacked GaN layers and InGaN layers doped with the first impurity;

或者,所述第一子层包括交替层叠设置的未掺杂的GaN层和InGaN层;Alternatively, the first sub-layer includes undoped GaN layers and InGaN layers that are alternately stacked;

或者,所述第一子层包括交替层叠设置的掺杂第一杂质的GaN层、未掺杂的GaN层和InGaN层。Alternatively, the first sub-layer includes an alternately stacked GaN layer doped with the first impurity, an undoped GaN layer and an InGaN layer.

优选地,所述应力释放层包括第一子层和第二子层,其中,所述第一子层为周期性结构,所述第二子层为单层结构,所述第二子层设置在所述第一子层和所述多量子阱发光层之间。Preferably, the stress relief layer includes a first sub-layer and a second sub-layer, wherein the first sub-layer has a periodic structure, the second sub-layer has a single-layer structure, and the second sub-layer is provided between the first sub-layer and the multi-quantum well light-emitting layer.

在本发明一些具体的实施例中,所述AlGaN层中还掺杂有硅;In some specific embodiments of the present invention, the AlGaN layer is also doped with silicon;

优选地,所述硅的掺杂浓度为1×1018~5×1018atoms/cm3,包括但不限于2×1018atoms/cm3、3×1018atoms/cm3、4×1018atoms/cm3中的任意一者的点值或任意两者之间的范围值。Preferably, the doping concentration of the silicon is 1×10 18 to 5×10 18 atoms/cm 3 , including but not limited to 2×10 18 atoms/cm 3 , 3×10 18 atoms/cm 3 , and 4×10 18 atoms/cm A point value of any one of 3 or any range value in between.

在本发明一些具体的实施例中,所述N型半导体层30包括非掺杂GaN层和/或掺杂第二杂质的N型GaN层。In some specific embodiments of the present invention, the N-type semiconductor layer 30 includes an undoped GaN layer and/or an N-type GaN layer doped with a second impurity.

优选地,所述第二杂质包括Si。Preferably, the second impurity includes Si.

优选地,所述第二杂质的掺杂浓度为1×1019~5×1019atoms/cm3,包括但不限于2×1019atoms/cm3、3×1019atoms/cm3、4×1019atoms/cm3中的任意一者的点值或任意两者之间的范围值。Preferably, the doping concentration of the second impurity is 1×10 19 to 5×10 19 atoms/cm 3 , including but not limited to 2×10 19 atoms/cm 3 , 3×10 19 atoms/cm 3 , 4 The point value of any one of ×10 19 atoms/cm 3 or the range value between any two.

在本发明一些具体的实施例中,所述非掺杂GaN层的厚度为1~5μm(还可以选择2μm、3μm或4μm)。In some specific embodiments of the present invention, the thickness of the non-doped GaN layer is 1 to 5 μm (2 μm, 3 μm or 4 μm can also be selected).

和/或,所述掺杂第二杂质的N型GaN层的厚度为1~5μm(还可以选择2μm、3μm或4μm)。And/or, the thickness of the N-type GaN layer doped with the second impurity is 1 to 5 μm (2 μm, 3 μm or 4 μm can also be selected).

在本发明一些具体的实施例中,所述P型半导体层60包括掺杂第三杂质的P型GaN层。In some specific embodiments of the present invention, the P-type semiconductor layer 60 includes a P-type GaN layer doped with a third impurity.

优选地,所述第三杂质包括Mg。Preferably, the third impurity includes Mg.

优选地,所述第三杂质的掺杂浓度为1×1019~1×1021atoms/cm3,包括但不限于2×1019atoms/cm3、5×1019atoms/cm3、8×1019atoms/cm3、1×1020atoms/cm3、5×1020atoms/cm3、8×1020atoms/cm3、1×1021atoms/cm3中的任意一者的点值或任意两者之间的范围值。Preferably, the doping concentration of the third impurity is 1×10 19 to 1×10 21 atoms/cm 3 , including but not limited to 2×10 19 atoms/cm 3 , 5×10 19 atoms/cm 3 , 8 Any one of ×10 19 atoms/cm 3 , 1×10 20 atoms/cm 3 , 5×10 20 atoms/cm 3 , 8×10 20 atoms/cm 3 , and 1×10 21 atoms/cm 3 value or any range of values in between.

优选地,所述掺杂第三杂质的P型GaN层的厚度为包括但不限于中的任意一者的点值或任意两者之间的范围值。Preferably, the thickness of the P-type GaN layer doped with the third impurity is including but not limited to A pip value of either or a range of values between any two.

在本发明一些具体的实施例中,所述N型半导体层30还包括三维成核层,所述三维成核层设置在所述缓冲层20和所述非掺杂GaN层之间。In some specific embodiments of the present invention, the N-type semiconductor layer 30 further includes a three-dimensional nucleation layer, and the three-dimensional nucleation layer is disposed between the buffer layer 20 and the non-doped GaN layer.

优选地,所述三维成核层的厚度为0.5~2μm,包括但不限于0.7μm、0.9μm、1.0μm、1.2μm、1.5μm、1.7μm、1.9μm中的任意一者的点值或任意两者之间的范围值。Preferably, the thickness of the three-dimensional nucleation layer is 0.5-2 μm, including but not limited to any point value or any point value of 0.7 μm, 0.9 μm, 1.0 μm, 1.2 μm, 1.5 μm, 1.7 μm, and 1.9 μm. The range of values between the two.

优选地,所述三维成核层的材料为AlGaN。Preferably, the material of the three-dimensional nucleation layer is AlGaN.

在本发明一些具体的实施例中,所述缓冲层20的材料为AlGaN。In some specific embodiments of the present invention, the material of the buffer layer 20 is AlGaN.

优选地,所述缓冲层20的厚度为包括但不限于/> 中的任意一者的点值或任意两者之间的范围值。Preferably, the thickness of the buffer layer 20 is Including but not limited to/> A pip value of either or a range of values between any two.

在本发明一些具体的实施例中,所述P型半导体层60还包括电子阻挡层,所述电子阻挡层设置在所述多量子阱发光层50和所述掺杂第三杂质的P型GaN层之间。In some specific embodiments of the present invention, the P-type semiconductor layer 60 further includes an electron blocking layer, which is disposed between the multi-quantum well light-emitting layer 50 and the P-type GaN doped with a third impurity. between layers.

在本发明一些具体的实施例中,所述电子阻挡层和所述掺杂第三杂质的P型GaN层统称为P型半导体层。In some specific embodiments of the present invention, the electron blocking layer and the P-type GaN layer doped with the third impurity are collectively referred to as a P-type semiconductor layer.

优选地,所述电子阻挡层的材料为AlGaN。Preferably, the electron blocking layer is made of AlGaN.

优选地,所述电子阻挡层的厚度为包括但不限于/> 中的任意一者的点值或任意两者之间的范围值。Preferably, the thickness of the electron blocking layer is Including but not limited to/> A pip value of either or a range of values between any two.

在本发明一些具体的实施方式中,所述衬底10为生长基板,其材质可以采用任意地、常规的材质,也可根据具体需求而设置。优选地,所述衬底10包括蓝宝石透明性基板、复合图形化基板(如蓝宝石+SiO2复合衬底)、GaN基板和SiC基板中的至少一种。In some specific embodiments of the present invention, the substrate 10 is a growth substrate, and its material can be any conventional material, or can be set according to specific needs. Preferably, the substrate 10 includes at least one of a sapphire transparent substrate, a composite patterned substrate (such as a sapphire + SiO 2 composite substrate), a GaN substrate and a SiC substrate.

在本发明一些具体的实施方式中,所述缓冲层20的晶格常数介于N型半导体层30与衬底10之间,这样可提高外延品质及降低晶格缺陷。优选地,所述缓冲层20包括AlN缓冲层、GaN缓冲层、AlGaN缓冲层和AlInGaN缓冲层中的至少一种。In some specific embodiments of the present invention, the lattice constant of the buffer layer 20 is between the N-type semiconductor layer 30 and the substrate 10 , which can improve epitaxial quality and reduce lattice defects. Preferably, the buffer layer 20 includes at least one of an AlN buffer layer, a GaN buffer layer, an AlGaN buffer layer and an AlInGaN buffer layer.

在本发明一些具体的实施例中,所述发光二极管的制备方法包括如下步骤:In some specific embodiments of the present invention, the method for preparing a light-emitting diode includes the following steps:

在衬底的表面依次生长缓冲层20、N型半导体层30、应力释放层40、多量子阱发光层50和P型半导体层60,得到所述发光二极管。The buffer layer 20, the N-type semiconductor layer 30, the stress relief layer 40, the multi-quantum well light-emitting layer 50 and the P-type semiconductor layer 60 are sequentially grown on the surface of the substrate to obtain the light-emitting diode.

在本发明一些具体的实施例中,所述应力释放层40的生长温度为850~900℃,包括但不限于860℃、870℃、880℃、890℃中的任意一者的点值或任意两者之间的范围值。In some specific embodiments of the present invention, the growth temperature of the stress relief layer 40 is 850-900°C, including but not limited to any one of 860°C, 870°C, 880°C, 890°C or any point value. The range of values between the two.

和/或,所述应力释放层40的生长压力为200~300mbar,包括但不限于210mbar、230mbar、250mbar、270mbar、290mbar中的任意一者的点值或任意两者之间的范围值。And/or, the growth pressure of the stress relief layer 40 is 200-300 mbar, including but not limited to any one point value of 210 mbar, 230 mbar, 250 mbar, 270 mbar, 290 mbar or any range value between the two.

下面将结合实施例对本发明的实施方案进行详细描述,但是本领域技术人员将会理解,下列实施例仅用于说明本发明,而不应视为限制本发明的范围。实施例中未注明具体条件者,按照常规条件或制造商建议的条件进行。所用试剂或仪器未注明生产厂商者,均为可以通过市购获得的常规产品。The embodiments of the present invention will be described in detail below with reference to examples, but those skilled in the art will understand that the following examples are only used to illustrate the present invention and should not be regarded as limiting the scope of the present invention. If the specific conditions are not specified in the examples, the conditions should be carried out according to the conventional conditions or the conditions recommended by the manufacturer. If the manufacturer of the reagents or instruments used is not indicated, they are all conventional products that can be purchased commercially.

实施例1Example 1

本实施例提供的发光二极管的结构示意图如图4所示,该发光二极管包括在蓝宝石衬底10表面依次层叠设置的AlGaN缓冲层20、N型半导体层30(包括非掺杂GaN层301和掺杂Si的N型GaN层302)、应力释放层40、InGaN/GaN多量子阱发光层50、P型半导体层60(包括P型AlGaN电子阻挡层601和掺杂Mg的P型GaN层602);The structural schematic diagram of the light-emitting diode provided in this embodiment is shown in Figure 4. The light-emitting diode includes an AlGaN buffer layer 20 and an N-type semiconductor layer 30 (including an undoped GaN layer 301 and a doped GaN layer) sequentially stacked on the surface of a sapphire substrate 10. Si-doped N-type GaN layer 302), stress relief layer 40, InGaN/GaN multiple quantum well light-emitting layer 50, P-type semiconductor layer 60 (including P-type AlGaN electron blocking layer 601 and Mg-doped P-type GaN layer 602) ;

其中,所述应力释放层40如图5所示,包括:依次层叠设置在所述掺杂Si的N型GaN层302表面的掺杂第一杂质的GaN层(第一杂质为碳)401、未掺杂的GaN层402、InGaN层403、AlGaN层404,以上各层呈周期性交替生长,循环周期为2个周期。Wherein, as shown in FIG. 5 , the stress relief layer 40 includes: a first impurity-doped GaN layer (the first impurity is carbon) 401 sequentially stacked on the surface of the Si-doped N-type GaN layer 302 , The undoped GaN layer 402, the InGaN layer 403, and the AlGaN layer 404 grow periodically and alternately, and the cycle period is two cycles.

本实施例提供的发光二极管的制备方法包括如下步骤:The method for preparing a light-emitting diode provided in this embodiment includes the following steps:

(1)在蓝宝石衬底10表面于550℃下生长厚度为的AlGaN缓冲层20。(1) The growth thickness on the surface of the sapphire substrate 10 at 550°C is AlGaN buffer layer 20.

(2)在NH3氛围下进行退火处理,升温至1110℃,让低温AlGaN重结晶成岛状晶种。(2) Perform annealing treatment in an NH 3 atmosphere, raise the temperature to 1110°C, and allow low-temperature AlGaN to recrystallize into island-shaped seed crystals.

(3)通入TMGa(三甲基镓),在800mbar压力下,生长一层1μm厚的三维层。(3) Pass in TMGa (trimethylgallium) and grow a 1 μm thick three-dimensional layer under a pressure of 800mbar.

(4)温度升至1150℃,压力降低到600mbar,生长一层非掺杂GaN层301,厚度为2μm。(4) The temperature is raised to 1150°C, the pressure is reduced to 600mbar, and a layer of non-doped GaN layer 301 is grown with a thickness of 2 μm.

(5)在相同条件下(与步骤(4)条件相同),生长2μm厚的掺杂Si的N型GaN层302,其中,Si掺杂浓度为3×1019atoms/cm3(5) Under the same conditions (the same conditions as step (4)), grow a 2 μm thick Si-doped N-type GaN layer 302, where the Si doping concentration is 3×10 19 atoms/cm 3 .

(6)生长应力释放层40:降温至900℃,在300mbar压力下,首先通过离子注入的方法生长一层掺杂第一杂质的GaN层(第一杂质为碳)401;然后,关闭碳注入,生长未掺杂的GaN层402;接着再生长InGaN层403和AlGaN层404;(6) Grow the stress release layer 40: Cool to 900°C, and under a pressure of 300 mbar, first grow a GaN layer doped with the first impurity (the first impurity is carbon) 401 through ion implantation; then, turn off the carbon injection. , grow an undoped GaN layer 402; then grow an InGaN layer 403 and an AlGaN layer 404;

其中,掺杂第一杂质的GaN层(第一杂质为碳)401、未掺杂的GaN层402、InGaN层403和AlGaN层404呈周期性生长,循环数量为2;且单个掺杂第一杂质的GaN层(第一杂质为碳)401的厚度为单个未掺杂的GaN层402的厚度为/>单个InGaN层403的厚度为单个AlGaN层404的厚度为/>掺杂第一杂质的GaN层(第一杂质为碳)401中碳的掺杂浓度为2×1017atoms/cm3Among them, the GaN layer doped with the first impurity (the first impurity is carbon) 401, the undoped GaN layer 402, the InGaN layer 403 and the AlGaN layer 404 grow periodically, and the number of cycles is 2; and a single doped first The thickness of the impurity GaN layer (the first impurity is carbon) 401 is The thickness of a single undoped GaN layer 402 is /> The thickness of a single InGaN layer 403 is The thickness of a single AlGaN layer 404 is/> The doping concentration of carbon in the GaN layer doped with the first impurity (the first impurity is carbon) 401 is 2×10 17 atoms/cm 3 .

(7)生长InGaN/GaN多量子阱发光层50,其为10对总厚度为的InGaN/>/GaN/>多量子阱发光层,其中,GaN垒层的生长温度为870℃,InGaN阱层的生长温度为790℃;InGaN阱层和GaN垒层使用的镓源均为TEGa(三乙基镓)。(7) Grow the InGaN/GaN multiple quantum well light-emitting layer 50, which is 10 pairs with a total thickness of InGaN/> /GaN/> For the multi-quantum well light-emitting layer, the growth temperature of the GaN barrier layer is 870°C, and the growth temperature of the InGaN well layer is 790°C; the gallium source used in the InGaN well layer and the GaN barrier layer is TEGa (triethylgallium).

(8)升温至1000℃,在200mbar压力条件下,生长P型AlGaN电子阻挡层601。(8) Raise the temperature to 1000°C and grow the P-type AlGaN electron blocking layer 601 under a pressure of 200 mbar.

(9)关闭铝源,保持条件与步骤(8)相同,继续生长掺杂Mg的P型GaN层602。其中,掺杂Mg的P型GaN层602中Mg的掺杂浓度为1×1020atoms/cm3(9) Turn off the aluminum source, keep the conditions the same as step (8), and continue to grow the Mg-doped P-type GaN layer 602. The doping concentration of Mg in the Mg-doped P-type GaN layer 602 is 1×10 20 atoms/cm 3 .

P型AlGaN电子阻挡层601和掺杂Mg的P型GaN层602的总厚度为 The total thickness of the P-type AlGaN electron blocking layer 601 and the Mg-doped P-type GaN layer 602 is

实施例2Example 2

本实施例提供的发光二极管的结构与实施例1基本相同,区别在于:所述应力释放层40如图6所示,包括:依次层叠设置在所述掺杂Si的N型GaN层302表面的掺杂第一杂质的GaN层(第一杂质为碳)401、InGaN层403、AlGaN层404,以上各层呈周期性交替生长,循环周期为3个周期。The structure of the light-emitting diode provided in this embodiment is basically the same as that in Embodiment 1. The difference is that the stress relief layer 40 is shown in FIG. 6 and includes: sequentially stacked on the surface of the Si-doped N-type GaN layer 302. The GaN layer 401 doped with the first impurity (the first impurity is carbon), the InGaN layer 403, and the AlGaN layer 404 are grown periodically and alternately, and the cycle period is three cycles.

本实施例提供的发光二极管的制备方法与实施例1基本相同,区别在于:步骤(6)中,应力释放层40的生长温度为850℃,生长压力为200mbar。The preparation method of the light-emitting diode provided in this embodiment is basically the same as that of Embodiment 1, except that in step (6), the growth temperature of the stress release layer 40 is 850°C and the growth pressure is 200 mbar.

实施例3Example 3

本实施例提供的发光二极管的结构与实施例1基本相同,区别仅在于,所述应力释放层40如图7所示,包括:依次层叠设置在所述掺杂Si的N型GaN层302表面的未掺杂的GaN层402、InGaN层403、AlGaN层404,以上各层呈周期性交替生长,循环周期为3个周期。The structure of the light-emitting diode provided in this embodiment is basically the same as that in Embodiment 1. The only difference is that the stress relief layer 40 is shown in FIG. 7 and includes: sequentially stacked on the surface of the Si-doped N-type GaN layer 302 The undoped GaN layer 402, the InGaN layer 403, and the AlGaN layer 404 are grown periodically and alternately, and the cycle period is three cycles.

本实施例提供的发光二极管的制备方法与实施例1基本相同,区别在于:步骤(6)中,单个未掺杂的GaN层402的厚度为单个InGaN层403的厚度为/>单个AlGaN层404的厚度为/> The preparation method of the light-emitting diode provided in this embodiment is basically the same as that of Embodiment 1. The difference is that in step (6), the thickness of the single undoped GaN layer 402 is The thickness of a single InGaN layer 403 is/> The thickness of a single AlGaN layer 404 is/>

实施例4Example 4

本实施例提供的发光二极管的结构与实施例1基本相同,区别仅在于,所述应力释放层40如图8所示,包括:依次层叠设置在所述掺杂Si的N型GaN层302表面的掺杂第一杂质的GaN层(第一杂质为碳)401、未掺杂的GaN层402、AlGaN层404,以上各层呈周期性交替生长,循环周期为4个周期。The structure of the light-emitting diode provided in this embodiment is basically the same as that in Embodiment 1. The only difference is that the stress relief layer 40 is shown in FIG. 8 and includes: sequentially stacked on the surface of the Si-doped N-type GaN layer 302 The GaN layer doped with the first impurity (the first impurity is carbon) 401, the undoped GaN layer 402, and the AlGaN layer 404 are formed. The above layers grow periodically and alternately, and the cycle period is four cycles.

本实施例提供的发光二极管的制备方法与实施例1基本相同,区别在于:步骤(6)中,单个掺杂第一杂质的GaN层(第一杂质为碳)401的厚度为单个未掺杂的GaN层402的厚度为/>单个AlGaN层404的厚度为/>且掺杂第一杂质的GaN层(第一杂质为碳)401中碳的掺杂浓度为5×1017atoms/cm3The preparation method of the light-emitting diode provided in this embodiment is basically the same as that in Embodiment 1. The difference is that in step (6), the thickness of a single GaN layer doped with the first impurity (the first impurity is carbon) 401 is The thickness of a single undoped GaN layer 402 is /> The thickness of a single AlGaN layer 404 is/> And the carbon doping concentration in the GaN layer doped with the first impurity (the first impurity is carbon) 401 is 5×10 17 atoms/cm 3 .

实施例5Example 5

本实施例所提供的发光二极管包括:衬底10,以及在衬底10表面依次层叠设置的AlGaN缓冲层20、N型半导体层30(包括非掺杂GaN层301和掺杂Si的N型GaN层302)、应力释放层40、InGaN/GaN多量子阱发光层50、P型半导体层60(包括P型AlGaN电子阻挡层601和掺杂Mg的P型GaN层602)。The light-emitting diode provided in this embodiment includes: a substrate 10, and an AlGaN buffer layer 20 and an N-type semiconductor layer 30 (including an undoped GaN layer 301 and a Si-doped N-type GaN layer) sequentially stacked on the surface of the substrate 10. layer 302), stress relief layer 40, InGaN/GaN multiple quantum well light-emitting layer 50, and P-type semiconductor layer 60 (including P-type AlGaN electron blocking layer 601 and Mg-doped P-type GaN layer 602).

本实施例中的应力释放层包括第一子层和第二子层,其中所述第一子层为周期性结构,周期数为5,第二子层位于第一子层和多量子阱发光层50之间。The stress relief layer in this embodiment includes a first sub-layer and a second sub-layer, wherein the first sub-layer is a periodic structure with a period number of 5, and the second sub-layer is located between the first sub-layer and the multi-quantum well to emit light. between layers 50.

如图9所示,应力释放层40中的第一子层包括交替层叠设置的掺杂第一杂质的GaN层401和未掺杂的GaN层402;第二子层即AlGaN层404(为单层结构)位于未掺杂的GaN层402和多量子阱发光层50之间。As shown in FIG. 9 , the first sub-layer in the stress relief layer 40 includes alternately stacked GaN layers 401 doped with the first impurity and undoped GaN layers 402 ; the second sub-layer, namely the AlGaN layer 404 (is a single layer structure) is located between the undoped GaN layer 402 and the multi-quantum well light emitting layer 50 .

本实施例中,所述掺杂第一杂质的GaN层401中的第一杂质为碳杂质,碳掺杂浓度为3×1017atoms/cm3In this embodiment, the first impurity in the GaN layer 401 doped with the first impurity is a carbon impurity, and the carbon doping concentration is 3×10 17 atoms/cm 3 .

实施例6Example 6

本实施例提供的发光二极管的结构与实施例5基本相同,区别仅在于,所述应力释放层40中的第一子层如图10所示,包括交替层叠设置的掺杂第一杂质的GaN层401和InGaN层403;第二子层即AlGaN层404(为单层结构)位于为掺杂InGaN层403和多量子阱发光层50之间。The structure of the light-emitting diode provided in this embodiment is basically the same as that in Embodiment 5. The only difference is that the first sub-layer in the stress relief layer 40 is shown in FIG. 10 and includes alternately stacked GaN doped with the first impurity. layer 401 and InGaN layer 403; the second sub-layer, AlGaN layer 404 (which is a single-layer structure), is located between the doped InGaN layer 403 and the multi-quantum well light-emitting layer 50.

实施例7Example 7

本实施例提供的发光二极管的结构与实施例5基本相同,区别仅在于,所述应力释放层40中的第一子层如图11所示,包括交替层叠设置的未掺杂的GaN层402和InGaN层403;第二子层即AlGaN层404(为单层结构)位于为掺杂InGaN层403和多量子阱发光层50之间。The structure of the light-emitting diode provided in this embodiment is basically the same as that in Embodiment 5. The only difference is that the first sub-layer in the stress relief layer 40 is shown in Figure 11 and includes alternately stacked undoped GaN layers 402. and InGaN layer 403; the second sublayer, namely AlGaN layer 404 (a single-layer structure), is located between the doped InGaN layer 403 and the multi-quantum well light-emitting layer 50.

实施例8Example 8

本实施例提供的发光二极管的结构与实施例5基本相同,区别仅在于,所述应力释放层40中的第一子层如图12所示,包括掺杂第一杂质的GaN层401、未掺杂的GaN层402和InGaN层403;第二子层即AlGaN层404(为单层结构)位于为掺杂InGaN层403和多量子阱发光层50之间。The structure of the light-emitting diode provided in this embodiment is basically the same as that in Embodiment 5. The only difference is that the first sub-layer in the stress relief layer 40 is shown in Figure 12 and includes a GaN layer 401 doped with the first impurity. The doped GaN layer 402 and the InGaN layer 403; the second sub-layer, the AlGaN layer 404 (which is a single-layer structure), is located between the doped InGaN layer 403 and the multi-quantum well light-emitting layer 50.

尽管已用具体实施例来说明和描述了本发明,然而应意识到,以上各实施例仅用以说明本发明的技术方案,而非对其限制;本领域的普通技术人员应当理解:在不背离本发明的精神和范围的情况下,可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围;因此,这意味着在所附权利要求中包括属于本发明范围内的所有这些替换和修改。Although the present invention has been illustrated and described with specific embodiments, it should be realized that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit it; those of ordinary skill in the art should understand that: Without departing from the spirit and scope of the present invention, the technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features thereof may be equivalently substituted; however, these modifications or substitutions shall not make the corresponding technical solutions essentially depart from the scope of the technical solutions of the various embodiments of the present invention; therefore, it is meant that all such substitutions and modifications falling within the scope of the present invention are included in the appended claims.

Claims (13)

1. The light-emitting diode is characterized by comprising a substrate, and a buffer layer, an N-type semiconductor layer, a stress release layer, a multiple quantum well light-emitting layer and a P-type semiconductor layer which are sequentially laminated on the surface of the substrate;
wherein the stress relief layer comprises a first sub-layer and a second sub-layer;
the first sub-layer is of a periodic structure;
the second sub-layer is of a single-layer structure, and the second sub-layer is an AlGaN layer.
2. The led of claim 1, wherein the alternating period of the first sub-layer is 2-5 periods.
3. The light emitting diode of claim 1, wherein the first sub-layer comprises at least two of a GaN layer doped with a first impurity, an undoped GaN layer, and an InGaN layer.
4. A light emitting diode according to claim 3 comprising at least one of the following features (1) to (3):
(1) The GaN layer doped with the first impurityIs of the thickness of
(2) The thickness of the undoped GaN layer is
(3) The thickness of the InGaN layer is
5. The light-emitting diode according to claim 3, wherein the first sub-layer includes a GaN layer doped with the first impurity and an undoped GaN layer arranged in a periodically alternating stack;
alternatively, the first sub-layer includes a GaN layer doped with a first impurity and an InGaN layer arranged in a periodically alternating stack;
alternatively, the first sub-layer includes undoped GaN layers and InGaN layers that are alternately stacked periodically;
alternatively, the first sub-layer includes a GaN layer doped with the first impurity, an undoped GaN layer, and an InGaN layer, which are alternately stacked in a periodic manner.
6. A light emitting diode according to claim 3 wherein the first impurity in the first impurity doped GaN layer comprises carbon and/or silicon;
preferably, the carbon has a doping concentration of 1×10 17 ~5×10 17 atoms/cm 3
Preferably, the doping concentration of the silicon is 1×10 18 ~5×10 18 atoms/cm 3
7. The led of claim 1, wherein the AlGaN layer has a thickness of
8. The led of claim 1, wherein said AlGaN layer is further doped with silicon;
preferably, the doping concentration of the silicon is 1×10 18 ~5×10 18 atoms/cm 3
9. The light emitting diode of any one of claims 1-8, wherein the first sub-layer is disposed on the N-type semiconductor layer and the second sub-layer is disposed between the first sub-layer and the multiple quantum well light emitting layer.
10. The light emitting diode of any one of claims 1 to 8, wherein the first sub-layer and the second sub-layer are arranged in a periodic stack;
preferably, the alternating period of the first sub-layer and the second sub-layer is 2 to 5 periods.
11. The light-emitting diode according to claim 10, wherein the stress release layer comprises a GaN layer doped with a first impurity, an undoped GaN layer, an InGaN layer, and an AlGaN layer which are sequentially stacked and disposed on the N-type semiconductor layer in a periodic alternating manner;
or the stress release layer comprises a GaN layer doped with a first impurity, an InGaN layer and an AlGaN layer which are sequentially stacked and arranged on the N-type semiconductor layer in a periodical and alternating manner;
or the stress release layer comprises an undoped GaN layer, an InGaN layer and an AlGaN layer which are sequentially stacked and arranged on the N-type semiconductor layer in a periodical and alternating manner;
alternatively, the stress release layer includes a GaN layer doped with the first impurity, an undoped GaN layer, and an AlGaN layer sequentially stacked and disposed on the N-type semiconductor layer in a periodic alternating manner.
12. The light emitting diode of claim 1, wherein the N-type semiconductor layer comprises an undoped GaN layer and/or an N-type GaN layer doped with a second impurity;
preferably, the second impurity includes Si;
preferably, the doping concentration of the second impurity is 1×10 19 ~5×10 19 atoms/cm 3
13. The light emitting diode of claim 1, wherein the P-type semiconductor layer comprises a third impurity doped P-type GaN layer;
preferably, the third impurity comprises Mg;
preferably, the doping concentration of the third impurity is 1×10 19 ~1×10 21 atoms/cm 3
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119364943A (en) * 2024-12-27 2025-01-24 江西兆驰半导体有限公司 Micro-LED epitaxial wafer and preparation method thereof, and Micro-LED

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114512580B (en) * 2021-12-22 2023-09-22 淮安澳洋顺昌光电技术有限公司 Light-emitting diode
CN115472721B (en) * 2022-10-24 2023-09-15 淮安澳洋顺昌光电技术有限公司 Light-emitting diode epitaxial structure and light-emitting diode
CN119486397A (en) * 2025-01-16 2025-02-18 江西兆驰半导体有限公司 LED epitaxial wafer for ultra-large current and preparation method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2597686A1 (en) * 2011-11-25 2013-05-29 LG Innotek Co., Ltd. Ultraviolet semiconductor light emitting device
CN105428482A (en) * 2015-12-30 2016-03-23 厦门市三安光电科技有限公司 LED epitaxial structure and manufacturing method thereof
CN109119515A (en) * 2018-07-09 2019-01-01 华灿光电(浙江)有限公司 A kind of LED epitaxial slice and its manufacturing method
CN109378366A (en) * 2018-08-16 2019-02-22 华灿光电(浙江)有限公司 A light-emitting diode epitaxial wafer and its manufacturing method
CN109980056A (en) * 2019-02-28 2019-07-05 华灿光电(苏州)有限公司 Gallium nitride based LED epitaxial slice and its manufacturing method
CN113571611A (en) * 2021-07-14 2021-10-29 淮安澳洋顺昌光电技术有限公司 An epitaxial wafer with antistatic ability and its application in light-emitting diodes
CN114512580A (en) * 2021-12-22 2022-05-17 淮安澳洋顺昌光电技术有限公司 Light-emitting diode

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100027407A (en) * 2008-09-02 2010-03-11 삼성전기주식회사 Nitride semiconductor light emitting device
KR102066610B1 (en) * 2012-12-07 2020-01-15 엘지이노텍 주식회사 Light Emitting Device
CN104538521B (en) * 2014-12-29 2017-03-29 北京大学 A kind of high brightness near ultraviolet LED and preparation method thereof
KR102308701B1 (en) * 2015-03-04 2021-10-06 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 Uv light emitting device and lighting system
CN106057988B (en) * 2016-06-22 2018-10-30 华灿光电(苏州)有限公司 A kind of preparation method of the epitaxial wafer of GaN base light emitting
CN107706273A (en) * 2017-09-12 2018-02-16 合肥惠科金扬科技有限公司 A kind of microLED epitaxial structures and preparation method thereof
CN110311022B (en) * 2019-05-31 2020-12-01 华灿光电(浙江)有限公司 GaN-based light-emitting diode epitaxial wafer and its manufacturing method
CN111106534B (en) * 2019-10-30 2020-11-27 华灿光电股份有限公司 Laser diode and manufacturing method thereof
CN113644170A (en) * 2021-08-16 2021-11-12 聚灿光电科技(宿迁)有限公司 A kind of LED epitaxial structure based on in-situ heat treatment method and its growth method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2597686A1 (en) * 2011-11-25 2013-05-29 LG Innotek Co., Ltd. Ultraviolet semiconductor light emitting device
CN105428482A (en) * 2015-12-30 2016-03-23 厦门市三安光电科技有限公司 LED epitaxial structure and manufacturing method thereof
CN109119515A (en) * 2018-07-09 2019-01-01 华灿光电(浙江)有限公司 A kind of LED epitaxial slice and its manufacturing method
CN109378366A (en) * 2018-08-16 2019-02-22 华灿光电(浙江)有限公司 A light-emitting diode epitaxial wafer and its manufacturing method
CN109980056A (en) * 2019-02-28 2019-07-05 华灿光电(苏州)有限公司 Gallium nitride based LED epitaxial slice and its manufacturing method
CN113571611A (en) * 2021-07-14 2021-10-29 淮安澳洋顺昌光电技术有限公司 An epitaxial wafer with antistatic ability and its application in light-emitting diodes
CN114512580A (en) * 2021-12-22 2022-05-17 淮安澳洋顺昌光电技术有限公司 Light-emitting diode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119364943A (en) * 2024-12-27 2025-01-24 江西兆驰半导体有限公司 Micro-LED epitaxial wafer and preparation method thereof, and Micro-LED

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