CN109166920A - NLDMOS device and process - Google Patents
NLDMOS device and process Download PDFInfo
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- CN109166920A CN109166920A CN201810833741.6A CN201810833741A CN109166920A CN 109166920 A CN109166920 A CN 109166920A CN 201810833741 A CN201810833741 A CN 201810833741A CN 109166920 A CN109166920 A CN 109166920A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了一种NLDMOS器件，在P型衬底上具有第一及第二N型深阱，第一N型深阱作为漂移区，其上具有场氧；P型衬底表面具有栅氧化层及多晶硅栅极，位于所述两N型深阱之间并覆盖部分第二N型深阱；所述第一深阱中含有NLDMOS器件的漏区，位于场氧远离多晶硅栅极的末端；靠漏区的场氧上具有漏区场板；所述第二N型深阱中含有P阱，P阱中具有所述NLDMOS器件的源区，以及重掺杂P型区，重掺杂P型区作为P阱的引出端；所述P阱及第一N型深阱中还具有Ptop层；第一N型深阱上方的层间介质表面还具有漂移区场板；在第一N型深阱中，在场氧与Ptop层之间，还具有N型掺杂层，且N型掺杂层是分为两段，中间衬底材质隔开。本发明还公开了所述NLDMOS器件的工艺方法。
The invention discloses an NLDMOS device, which has first and second N-type deep wells on a P-type substrate, the first N-type deep well is used as a drift region and has field oxygen on it; the surface of the P-type substrate has gate oxide The layer and the polysilicon gate are located between the two N-type deep wells and cover part of the second N-type deep well; the first deep well contains the drain region of the NLDMOS device, which is located at the end of the field oxygen away from the polysilicon gate; There is a drain region field plate on the field oxygen near the drain region; the second N-type deep well contains a P-well, the P-well has the source region of the NLDMOS device, and a heavily doped P-type region, which is heavily doped with P The P-well and the first N-type deep well also have a Ptop layer; the interlayer dielectric surface above the first N-type deep well also has a drift zone field plate; in the first N-type deep well In the deep well, between the field oxygen and the Ptop layer, there is also an N-type doped layer, and the N-type doped layer is divided into two sections, and the intermediate substrate material is separated. The invention also discloses a process method of the NLDMOS device.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, in particular to a kind of NLDMOS device.The invention further relates to
The process of the NLDMOS device.
Background technique
700V LDMOS had not only had the characteristics that discrete device high-voltage great-current, but also had drawn low-voltage ic high density intelligence
The advantages of logic control, single-chip realize the function that original multiple chips could be completed, greatly reduce area, reduce into
This, improves efficiency, meets Modern Power Electronic Devices miniaturization, intelligent, the developing direction of low energy consumption.
Breakdown voltage and conducting resistance are to measure the key parameter of 700V device.(super junction is super by lateral SJ
Knot) using its key performance can be improved.Common 700V NLDMOS device structure is as shown in Figure 1, P type substrate 101 in figure
In have a N-type deep trap 102, also there is Ptop layer 105 in N-type deep trap 102.The p-type injection of its Ptop layer 105, which is played, accelerates drift region
High breakdown voltage is realized in the effect exhausted.
In the top of Ptop layer 105, also increases by one of N-type impurity injection 105b, further decrease the conducting resistance of device.
Fig. 2 is the corresponding top view above device.
Above structure the problem is that: device breakdown occur in drift region 112 edge of Metal field plate lower orientation
(the p-type impurity injection 105b mark in figure) is set, drift region surface n type doping concentration improves, and leads to electric-field enhancing at this, device
Part reduce pressure or it is unstable.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of NLDMOS device, operating voltage 700V has preferable
Breakdown voltage and on-resistance properties.
Another technical problem to be solved by this invention is to provide the process of the NLDMOS device.
To solve the above problems, a kind of NLDMOS device of the present invention, has first and second N in P type substrate
Moldeed depth trap, the first N-type deep trap have field oxygen as drift region thereon；P type substrate surface has gate oxide and polysilicon gate
Pole, between the two N-types deep trap and covering part the second N-type deep trap；Contain NLDMOS device in first deep trap
Drain region, the end positioned at field oxygen far from polysilicon gate；There is drain region field plate on the field oxygen in drain region；
Contain p-well in the second N-type deep trap, there is source region and the heavily doped P-type area of the NLDMOS device, weight in p-well
Exit of the doped p-type area as p-well；Also there are Ptop layers in the p-well and the first N-type deep trap；
Substrate surface has inter-level dielectric, and metal lead wire is drawn the source region of NLDMOS device and drain region by contact hole；First N
Inter-level dielectric surface above moldeed depth trap also has drift region field plate；
In the first N-type deep trap, between oxygen and Ptop on the scene layer, also there is n-type doping layer, and n-type doping layer is divided into two sections,
Intermediate substrate material separates.
Further, the n-type doping layer, partition point are located at the lower section at drift region field plate edge.
To solve the above problems, the process of NLDMOS device of the present invention, includes following processing step:
Step 1 forms first and second N-type deep trap independent of each other by ion implanting in P type substrate；
Step 2 opens field oxygen zone domain using active area photoetching, etches field oxygen zone, raw long field oxide；
Trap injection zone is opened in step 3, photoetching, and ion implanting forms p-well；
Step 4 carries out P-type ion injection respectively in p-well and in the first N-type deep trap, form Ptop layers；
Step 5, in the first N-type deep trap, the lower section of field oxygen carries out n-type doping injection, forms n-type doping layer；
Step 6, grows gate oxide, and depositing polysilicon simultaneously returns the polysilicon field plate carved and form polysilicon gate and drain terminal；
Step 7 carries out N-type impurity injection and p type impurity injection respectively, forms source region and the drain region of NLDMOS device, and
Heavily doped P-type area in p-well；
Step 8, deposit inter-level dielectric, etch contact hole, deposited metal and etch form pattern, including metal lead wire and drift
Area's field plate is moved, element manufacturing is completed.
Further, in the step 2, field oxygen is located on the first N-type deep trap, covers the first N-type deep trap and the first N
Substrate surface between moldeed depth trap and the second N-type deep trap.
Further, in the step 3, p-well is located in the second N-type deep trap, the background region as NLDMOS device.
Further, in the step 4, Ptop layers of injection is divided into a low energy injection and a high-energy injection,
Wherein, the low energy of P-type ion, which is injected, forms a p type island region under oxygen on the scene, the n-type doping carried out with subsequent 5th step is same
The p-type doping in region, low energy can neutralize part N-type impurity, reduce the concentration of N-type impurity at this；The high-energy of P-type ion
Injection is located at the lower section of N-doped zone, forms Ptop layers.
Further, in the step 5, the Implantation Energy of n-type doping is controlled, n-type doping layer is made to be located at field oxygen and Ptop
Position between layer, also, by the injection zone of exposure mask control n-type doping, so that n-type doping layer is divided into spaced apart two sections,
The position at interval is located at the lower section at the drift region field plate edge being subsequently formed.
Further, in the step 6, gate oxide is formed using thermal oxidation method.
Further, in the step 7, injected by N-type ion to be formed Liang Ge heavily doped N-type area respectively as
The source region of NLDMOS device and drain region；Draw-out area of the heavily doped P-type area as p-well.
Further, in the step 8, drain region and drain region field plate are connected the drain terminal to form device by the metal lead wire,
Heavily doped P-type area is connect the source to form NLDMOS device by another metal lead wire with source region, etches the drift region field plate of formation
Floating.
NLDMOS device of the present invention, the n-type doping layer in drift region can further decrease conducting resistance, together
When, the n-type doping layer of segmentation is equivalent to and undopes in this section of drift region of the lower section at drift region field plate edge, improves this
The electric field strength in region guarantees that NLDMOS device breakdown voltage will not be reduced because of the increase of drift region surface dopant concentration.
Detailed description of the invention
Fig. 1 is traditional NLDMOS device sectional view.
Fig. 2 is traditional NLDMOS device overlooking structure figure.
Fig. 3~10 are present invention process step schematic diagrams.
Figure 11 is present invention process flow chart of steps.
Description of symbols
101-P type substrates, 102-(first and second) N-type deep traps, 103-field oxygen, 104-p-wells, 105-Ptop layers,
105b-N type doped layer, 106-gate oxides, 107-polysilicons (grid, field plate), 108(108a-N-type heavily doped region
(drain terminal), 108b-N-type heavily doped region (source)), 109-heavily doped P-type areas, 110-inter-level dielectrics, 111-metals,
112- Metal field plate.
Specific embodiment
NLDMOS device of the present invention is as shown in Figure 10, has first and second N-type deep trap in P type substrate 101
102(note: being indicated with same appended drawing reference 102, is the first N-type deep trap under the covering of figure midfield oxygen 103, is comprising p-well 104
Second N-type deep trap).First N-type deep trap is as drift region.101 surface of P type substrate has gate oxide 106 and polysilicon gate
107, between the two N-types deep trap and covering part the second N-type deep trap；Contain NLDMOS device in first deep trap
Drain region 108a, the end positioned at field oxygen far from polysilicon gate；Have drain region field plate 107(and grid same on the field oxygen in drain region
For polycrystalline silicon material, identical appended drawing reference is used).
Contain p-well 104, source region 108b, Yi Jichong with the NLDMOS device in p-well in the second N-type deep trap
Doped p-type area 109, exit of the heavily doped P-type area as p-well；Also there are Ptop layers in the p-well and the first N-type deep trap.
Substrate surface has inter-level dielectric 110, and metal lead wire is drawn the source region of NLDMOS device and drain region by contact hole
Out；Inter-level dielectric surface above first N-type deep trap also has drift region field plate.
In the first N-type deep trap, between oxygen 103 and Ptop layer 105 on the scene, also there is n-type doping layer 105b, and N-type is mixed
Diamicton is divided into two sections, and intermediate substrate material separates.
The n-type doping layer, partition point are located at the lower section at drift region field plate edge.
The drift region of NLDMOS device of the present invention is played the role of longitudinal acceleration drift region and is exhausted using Ptop layers of injection,
Increase breakdown voltage.N-type impurity is injected at drift region surface interval, the N-type concentration on drift region surface is improved, further drops
Low on-resistance；The n-type doping on drift region surface is divided into two sections, the mixing without this step immediately below the edge of Metal field plate
It is miscellaneous, improve the electric field strength at this, retainer member breakdown voltage will not be reduced because of the increase of drift region surface dopant concentration.
The process of NLDMOS device of the present invention, the technique altogether comprising following step one to step 8, point
Other respective figure 3~10:
Step 1 forms first and second N-type deep trap independent of each other by ion implanting in P type substrate.
Step 2 opens field oxygen zone domain using active area photoetching, etches field oxygen zone, raw long field oxide；Field oxygen is located at the first N
On moldeed depth trap, the substrate surface between the first N-type deep trap and the first N-type deep trap and the second N-type deep trap is covered.
Trap injection zone is opened in step 3, photoetching, and ion implanting is carried out in the second N-type deep trap and forms p-well, as
The background region of NLDMOS device.
Step 4 carries out P-type ion injection respectively in p-well and in the first N-type deep trap, form Ptop layers.Ptop layers
Injection be divided into low energy injection and high-energy injection, wherein the low energy of progress P-type ion first, which is injected under oxygen on the scene, to be formed
One p type island region, the n-type doping injection carried out with subsequent 5th step are in the same area, and the p-type doping of low energy can neutralize portion
Divide N-type impurity, reduce the concentration of N-type impurity at this, is i.e. includes a p type impurity injection when n-type doping layer 105b is formed.Further
The high-energy injection of secondary P-type ion is located at the lower section of N-doped zone, forms Ptop layers.As shown in fig. 6, low energy is injected in figure
P-type injection figure in do not show, when injection, with the position for the Metal field plate 112 that masking film is subsequently formed, n-type doping layer is made to exist
The position of Metal field plate 112 disconnects.
Step 5, in the first N-type deep trap, the lower section of field oxygen carries out n-type doping injection, forms n-type doping layer；Control N
The Implantation Energy of type doping makes position of the n-type doping layer between field oxygen and Ptop layers, also, controls N-type by exposure mask and mix
Miscellaneous injection zone, makes n-type doping layer be divided into spaced apart two sections, and the position at interval is located at the drift region field plate being subsequently formed
Underface.
Step 6 grows gate oxide using thermal oxidation method, and depositing polysilicon simultaneously returns to carve and forms polysilicon gate, and leakage
The polysilicon field plate at end.
Step 7 carries out N-type impurity injection and p type impurity injection respectively, forms source region and the drain region of NLDMOS device,
And the heavily doped P-type area in p-well.It injects to form Liang Ge heavily doped N-type area respectively as NLDMOS device by N-type ion
Source region and drain region；Draw-out area of the heavily doped P-type area as p-well.
Step 8, deposit inter-level dielectric, etch contact hole, deposited metal and etch form pattern, including metal lead wire
And drift region field plate.Drain region and drain region field plate are connected the drain terminal to form device by the metal lead wire, and another metal lead wire will weigh
Doped p-type area connect the source to form NLDMOS device with source region, etches the drift region field plate floating of formation.The device system of completion
Make.
The above is only a preferred embodiment of the present invention, is not intended to limit the present invention.Come for those skilled in the art
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any modification, equivalent
Replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of NLDMOS device, there is first and second N-type deep trap in P type substrate, the first N-type deep trap as drift region,
There is field oxygen thereon；P type substrate surface has gate oxide and polysilicon gate, between the two N-types deep trap and covers
Part the second N-type deep trap；Drain region containing NLDMOS device in first deep trap, the end positioned at field oxygen far from polysilicon gate
End；There is drain region field plate on the field oxygen in drain region；
Contain p-well in the second N-type deep trap, there is source region and the heavily doped P-type area of the NLDMOS device, weight in p-well
Exit of the doped p-type area as p-well；Also there are Ptop layers in the p-well and the first N-type deep trap；
Substrate surface has inter-level dielectric, and metal lead wire is drawn the source region of NLDMOS device and drain region by contact hole；First N
Inter-level dielectric surface above moldeed depth trap also has drift region field plate；
It is characterized by: in the first N-type deep trap, between oxygen and Ptop on the scene layer, also there is n-type doping layer, and n-type doping layer
Two sections are divided into, centre is separated by substrate.
2. NLDMOS device as described in claim 1, it is characterised in that: the n-type doping layer, partition point are located at drift
The lower section at area field plate edge.
3. manufacturing the process of NLDMOS device as described in claim 1, it is characterised in that: walked comprising following technique
It is rapid:
Step 1 forms first and second N-type deep trap independent of each other by ion implanting in P type substrate；
Step 2 opens field oxygen zone domain using active area photoetching, etches field oxygen zone, raw long field oxide；
Trap injection zone is opened in step 3, photoetching, and ion implanting forms p-well；
Step 4 carries out P-type ion injection respectively in p-well and in the first N-type deep trap, form Ptop layers；
Step 5, in the first N-type deep trap, the lower section of field oxygen carries out n-type doping injection, forms n-type doping layer；
Step 6, grows gate oxide, and depositing polysilicon simultaneously returns the polysilicon field plate carved and form polysilicon gate and drain terminal；
Step 7 carries out N-type impurity injection and p type impurity injection respectively, forms source region and the drain region of NLDMOS device, and
Heavily doped P-type area in p-well；
Step 8, deposit inter-level dielectric, etch contact hole, deposited metal and etch form pattern, including metal lead wire and drift
Area's field plate is moved, element manufacturing is completed.
4. the process of NLDMOS device as claimed in claim 3, it is characterised in that: in the step 2, field oxygen is located at
On first N-type deep trap, the substrate surface between the first N-type deep trap and the first N-type deep trap and the second N-type deep trap is covered.
5. the process of NLDMOS device as claimed in claim 3, it is characterised in that: in the step 3, p-well is located at the
Background region in two N-type deep traps, as NLDMOS device.
6. the process of NLDMOS device as claimed in claim 3, it is characterised in that: in the step 4, Ptop layers
Injection is divided into a low energy injection and a high-energy injection, wherein the low energy of P-type ion, which is injected under oxygen on the scene, forms one
A p type island region, the n-type doping carried out with subsequent 5th step is the same area, and it is miscellaneous that the p-type doping of low energy can neutralize part N-type
Matter reduces the concentration of N-type impurity at this；The high-energy injection of P-type ion is located at the lower section of N-doped zone, forms Ptop layers.
7. the process of NLDMOS device as claimed in claim 3, it is characterised in that: in the step 5, control N-type is mixed
Miscellaneous Implantation Energy makes position of the n-type doping layer between field oxygen and Ptop layers, also, controls n-type doping by exposure mask
Injection zone, makes n-type doping layer be divided into spaced apart two sections, and the position at interval is located at the drift region field plate edge being subsequently formed
Lower section.
8. the process of NLDMOS device as claimed in claim 3, it is characterised in that: in the step 6, gate oxide
It is formed using thermal oxidation method.
9. the process of NLDMOS device as claimed in claim 3, it is characterised in that: in the step 7, by N-type from
Son injection forms source region and drain region of the Liang Ge heavily doped N-type area respectively as NLDMOS device；Heavily doped P-type area is as p-well
Draw-out area.
10. the process of NLDMOS device as claimed in claim 3, it is characterised in that: in the step 8, the metal
Drain region and drain region field plate are connected the drain terminal to form device by lead, and heavily doped P-type area is connect shape with source region by another metal lead wire
At the source of NLDMOS device, the drift region field plate floating of formation is etched.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113611732A (en) * | 2021-07-02 | 2021-11-05 | 上海华虹宏力半导体制造有限公司 | JFET device |
| CN113851521A (en) * | 2021-08-20 | 2021-12-28 | 上海华虹宏力半导体制造有限公司 | High-voltage field effect tube structure for improving on-resistance characteristic and manufacturing method |
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