CN104617149B - Isolated form NLDMOS device and its manufacturing method - Google Patents

Abstract

The invention discloses an isolated NLDMOS device. Two independent N-type deep wells are formed on a P-type silicon substrate; a P well is formed in the left part of the left N-type deep well; a P-type heavy well is formed in the left part of the P well. Doping region and a source N-type heavily doped region; a gate oxide layer is formed above the right part of the P well and the right part of the left N-type deep well; the P-type silicon between the left N-type deep well and the right N-type deep well Field oxygen is formed above the substrate and above the left part of the right N-type deep well; a drain terminal N-type heavily doped region is formed on the right part of the right N-type deep well; gate polysilicon is formed above the left part of the field oxygen and above the gate oxide layer A drift P-type implantation region is formed in the P-type silicon substrate and the right N-type deep well below the field oxygen, and the right part of the drift P-type implantation region is segmented and spaced. The invention also discloses a manufacturing method of the isolated NLDMOS device. The invention can reduce the on-resistance of the device while ensuring that the breakdown voltage of the isolated NLDMOS device does not decrease.

Description

Isolated NLDMOS device and manufacturing method thereof

technical field

The invention relates to semiconductor technology, in particular to an isolated NLDMOS device and a manufacturing method thereof.

Background technique

LDMOS (Laterally Diffused Metal Oxide Semiconductor) is currently widely used in power management circuits due to its advantages of high voltage resistance, high current drive capability, extremely low power consumption, and integration with CMOS.

The isolated NLDMOS device not only has the high-voltage and high-current characteristics of discrete devices, but also absorbs the advantages of high-density intelligent logic control of low-voltage integrated circuits. A single chip realizes the functions that can only be completed by multiple chips, which greatly reduces the area, reduces costs, and improves It meets the development direction of miniaturization, intelligence and low energy consumption of modern power electronic devices. Breakdown voltage and on-resistance are key parameters for measuring isolated NLDMOS devices.

There is an isolated NLDMOS (N-type laterally diffused metal oxide semiconductor) device. The unit structure is shown in FIG. An independent N-type deep well, the left part of the left N-type deep well 102a is formed with a P well 104, and the left part of the P well 104 is formed with a P-type heavily doped region 109 and a source N-type heavily doped region 108a, and the P well 104 A gate oxide layer 106 is formed on the right and upper right of the left N-type deep well 102a, above the P-type silicon substrate 101 between the left N-type deep well 102a and the right N-type deep well 102b, and the left part of the right N-type deep well 102b A field oxygen 103 is formed above, a drain terminal N-type heavily doped region 108b is formed on the right part of the right N-type deep well 102b, a gate polysilicon 107a is formed on the left part of the field oxygen 10 and above the gate oxide layer 106, and the right part of the field oxygen 10 A polysilicon field plate 107b at the drain end is formed above, and an interlayer dielectric 110 covers the surface of the device. The P-type heavily doped region 109 and the source N-type heavily doped region 108a pass through a metal 111 short of a metal 111 passing through the interlayer dielectric 110. connected together, the N-type heavily doped region 108b at the drain end and the polysilicon field plate 107b at the drain end are short-circuited together through another metal 111 passing through the interlayer dielectric 110, and the P-type silicon substrate 101 under the field oxygen 10 and the right A drift P-type implant region 105b is formed in the N-type deep well 102b, and a source-end P-type implant region 105a is formed in the P well 104 . In the isolated NLDMOS device shown in FIG. 1, the implantation of the drift P-type implant region 105b in the drift region can accelerate the depletion of the drift region and increase the breakdown device voltage, but because the drift P-type implant region 105b will compensate the drift region, Reducing the effective doping concentration in the drift region compresses the current channel in the drift region, so this will also increase the on-resistance of the device.

Contents of the invention

The technical problem to be solved by the invention is to reduce the on-resistance of the device while ensuring that the breakdown voltage of the isolated NLDMOS device does not decrease.

In order to solve the above-mentioned technical problems, the isolated NLDMOS device provided by the present invention has a unit structure that two independent N-type deep wells, a left N-type deep well and a right N-type deep well, are formed on a P-type silicon substrate;

The left N-type deep well has a P well formed on the left;

In the P well, a P-type heavily doped region and a source N-type heavily doped region are formed in the left part;

A gate oxide layer is formed above the right part of the P well and above the right part of the left N-type deep well;

Field oxygen is formed above the P-type silicon substrate between the left N-type deep well and the right N-type deep well, and above the left part of the right N-type deep well;

In the right N-type deep well, a drain N-type heavily doped region is formed on the right;

Gate polysilicon is formed above the left part of the field oxygen and above the gate oxide layer;

A drift P-type implantation region is formed in the P-type silicon substrate and the right N-type deep well below the field oxygen;

The right part of the drift P-type implantation region is segmented and spaced.

Preferably, a polysilicon field plate at the drain end is formed above the right part of the field oxygen;

The interlayer dielectric covers the surface of the device;

The P-type heavily doped region and the source N-type heavily doped region are shorted together by a metal passing through the interlayer dielectric;

The N-type heavily doped region at the drain end is short-circuited with the polysilicon field plate at the drain end through another metal passing through the interlayer dielectric.

Preferably, a source P-type implantation region is formed in the P well.

Preferably, the right part of the drift P-type implantation region is 1/2 to 2/3 of the drift P-type implantation region.

In order to solve the above-mentioned technical problems, the manufacturing method of the isolated NLDMOS device provided by the present invention comprises the following steps:

1. Two independent N-type deep wells, the left N-type deep well and the right N-type deep well, are formed by N-type ion implantation on the P-type silicon substrate;

2. Use active area lithography to open the field oxygen region and etch the field oxygen region above the P-type silicon substrate between the left N-type deep well and the right N-type deep well, and above the left part of the right N-type deep well , growth field oxygen;

3. Open the well implantation area by photolithography, and inject P-type ions into the left part of the left N-type deep well to form a P-well;

4. Perform P-type ion implantation below the field oxygen, and form a drift P-type implantation region in the P-type silicon substrate and the right N-type deep well below the field oxygen;

In the drift P-type injection region, the right part is segmented and spaced injection;

5. Perform follow-up process steps to complete the fabrication of isolated NLDMOS devices.

Preferably, the subsequent process steps in step five include:

(1). On the silicon wafer, a gate oxide layer is grown by a thermal oxidation method, and polysilicon is deposited; then the polysilicon gate is etched to form the gate polysilicon and the drain polysilicon field plate of the isolated NLDMOS device;

The gate polysilicon is located above the right part of the P well, above the right part of the left N-type deep well and above the left part of the field oxygen;

The polysilicon field plate at the drain end is located above the right part of the field oxygen;

(2). Selectively perform source-drain ion implantation, respectively form a P-type heavily doped region and a source N-type heavily doped region at the left part of the P well, and form a drain at the right part of the right N-type deep well Terminal N-type heavily doped region;

(3). On the silicon wafer, deposit the interlayer dielectric, etch the contact hole, then deposit the metal, and then etch the required pattern to form the source end of the isolated NLDMOS device and the lead-out metal of the background area, And the lead-out metal of the drain end, and finally complete the fabrication of the isolated NLDMOS device.

Preferably, in step 4, P-type ion implantation is performed in the P-well at the same time, and a source-end P-type implantation region is formed in the P-well.

Preferably, in step 4, the right part of the drift P-type implantation region is 1/2 to 2/3 of the drift P-type implantation region.

Preferably, in step 4, the right part of the drift P-type implantation region is implanted in segments at equal intervals.

Preferably, in step 4, the implanted P-type ions are boron ions, the implantation energy is 1000 keV to 1500 keV, and the implantation dose is 1E12 to 1E14 per square centimeter.

In the isolated NLDMOS device and its manufacturing method of the present invention, the right part of the drift P-type implantation region 105b in the drift region is segmented and spaced, and the two-dimensional depletion characteristics of the island-shaped P-type implantation region are fully utilized to maximize the horizontal and vertical directions. Depletion not only helps the drift region to be completely depleted, but also increases the effective doping concentration of the drift region and increases the current channel of the drift region, thereby reducing the on-resistance of the device while ensuring that the breakdown voltage of the device does not decrease (while maintaining the breakdown voltage The on-resistance can be reduced by up to 10% without change).

Description of drawings

In order to illustrate the technical solution of the present invention more clearly, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, In other words, other drawings can also be obtained from these drawings on the premise of not paying creative work.

FIG. 1 is a cross-sectional view of an existing isolated NLDMOS device;

Fig. 2 is a cross-sectional view of an embodiment of an isolated NLDMOS device of the present invention;

Fig. 3 is a cross-sectional view after forming an N-type deep well in an embodiment of a manufacturing method of an isolated NLDMOS device of the present invention;

4 is a cross-sectional view after field oxygen formation in an embodiment of the manufacturing method of the isolated NLDMOS device of the present invention;

5 is a cross-sectional view after the formation of the P well in an embodiment of the manufacturing method of the isolated NLDMOS device of the present invention;

6 is a cross-sectional view after the formation of the P-type implantation region in an embodiment of the manufacturing method of the isolated NLDMOS device of the present invention;

7 is a cross-sectional view after gate polysilicon is formed in an embodiment of the manufacturing method of the isolated NLDMOS device of the present invention;

FIG. 8 is a cross-sectional view after source-drain ion implantation in an embodiment of the method for manufacturing an isolated NLDMOS device according to the present invention.

Detailed ways

The technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Embodiment one

For an isolated NLDMOS device, the unit structure is shown in FIG. 2 , and two independent N-type deep wells, a left N-type deep well 102a and a right N-type deep well 102b, are formed on a P-type silicon substrate 101;

The left N-type deep well 102a has a P well 104 formed on the left;

In the P well 104, a P-type heavily doped region 109 and a source N-type heavily doped region 108a are formed on the left;

A gate oxide layer 106 is formed above the right part of the P well 104 and above the right part of the left N-type deep well 102a;

Field oxygen 103 is formed above the P-type silicon substrate 101 between the left N-type deep well 102a and the right N-type deep well 102b, and above the left part of the right N-type deep well 102b;

The right N-type deep well 102b has a drain N-type heavily doped region 108b formed on the right;

A gate polysilicon 107a is formed above the left part of the field oxygen 103 and above the gate oxide layer 106;

A drift P-type implant region 105b is formed in the P-type silicon substrate 101 and the right N-type deep well 102b below the field oxygen 103;

The right part of the drift P-type implantation region 105b is segmented and spaced.

Preferably, P-type silicon substrate 101, P well 104, drift P-type implantation region 105b, P-type heavily doped region 109, P-type doping concentration increases sequentially;

The N-type doping concentrations of the left N-type deep well 102a and the right N-type deep well 102b are lower than the N-type doping concentrations of the source N-type heavily doped region 108a and the drain N-type heavily doped region 108b.

Preferably, a drain terminal polysilicon field plate 107b is formed above the right part of the field oxide 103;

The interlayer dielectric 110 covers the surface of the device;

The P-type heavily doped region 109 and the source N-type heavily doped region 108a are short-circuited together by a metal 111 passing through the interlayer dielectric 110;

The drain terminal N-type heavily doped region 108b is short-circuited with the drain terminal polysilicon field plate 107b through another metal 111 passing through the interlayer dielectric 110;

Preferably, a source end P-type implantation region 105a is formed in the P well 104 .

Preferably, the right part of the drift P-type implantation region 105b is about 1/2 to 2/3 of the drift P-type implantation region 105b.

In the isolated NLDMOS device of Embodiment 1, the right part of the drift P-type implantation region 105b in the drift region is segmented and spaced, and the two-dimensional depletion characteristics of the island-shaped P-type implantation region are fully utilized to achieve maximum depletion in the horizontal and vertical directions. It not only helps the drift region to be completely depleted, but also increases the effective doping concentration of the drift region and increases the current channel of the drift region, so that the on-resistance of the device is reduced while ensuring that the breakdown voltage of the device (up to 700V) is not reduced (while maintaining the breakdown voltage) The on-resistance can be reduced by up to 10% when the breakdown voltage remains the same). Since there will be an electric field peak at the left end of the drift region, if the left part of the drift P-type injection region is segmented, the left end of the drift region will quickly reach the critical electric field, so the left part of the drift P-type injection region will not be divided to reduce the peak electric field at the left end of the drift region.

Embodiment two

The manufacturing method of the isolated NLDMOS device of Embodiment 1 includes the following process steps:

1. Two independent N-type deep wells, left N-type deep well 102a and right N-type deep well 102b, are formed by N-type ion implantation on the P-type silicon substrate 101, as shown in FIG. 3 ;

2. Open the field oxygen region by using active region lithography, etch the field oxygen region above the P-type silicon substrate 101 between the left N-type deep well 102a and the right N-type deep well 102b, and the right N-type deep well Above the left part of 102b, the growth field oxygen 103, as shown in Figure 4;

3. Open the well implantation region by photolithography, and implant P-type impurity ions into the left part of the left N-type deep well 102a to form a P-well 104, as shown in Figure 5, the P-well 104 is used as the background area of the isolated NLDMOS device;

Four. Perform P-type ion implantation below the field oxygen, and form a drift P-type implantation region 105b in the P-type silicon substrate 101 and the right N-type deep well 102b below the field oxygen 10, as shown in Figure 6;

The right part of the drift P-type implantation region 105b is segmented and spaced implantation;

5. Perform follow-up process steps to complete the fabrication of isolated NLDMOS devices.

Preferably, the subsequent process steps in step five include:

(1). On the silicon wafer, a gate oxide layer 106 is grown by thermal oxidation, and polysilicon 107 is deposited; then the polysilicon gate is etched to form the gate polysilicon 107a and the drain terminal polysilicon field plate 107b of an isolated NLDMOS device, as shown in FIG. As shown in Figure 7;

The gate polysilicon 107a is located above the right part of the P well 104, above the right part of the left N-type deep well 102a and above the left part of the field oxygen 10;

The polysilicon field plate 107b at the drain end is located above the right part of the field oxygen 10;

(2). Selectively perform conventional source-drain ion implantation, respectively form a P-type heavily doped region 109 and a source N-type heavily doped region 108a in the left part of the P well 104, and form a deep N-type region on the right The drain terminal N-type heavily doped region 108b is formed in the right part of the well 102b, as shown in FIG. 8 ;

(3). On the silicon wafer, deposit the interlayer dielectric 110, etch out the contact hole, then deposit the metal (such as aluminum) 111, and then etch the required pattern to form the source terminal and the local of the isolated NLDMOS device The lead-out metal plate of the bottom area and the lead-out metal plate of the drain end complete the fabrication of the isolated NLDMOS device, as shown in FIG. 2 .

Preferably, in Step 4, P-type ion implantation is performed in the P-well 104 at the same time, and a source-end P-type implantation region 105 a is formed in the P-well 104 .

Preferably, in step 4, the right part of the drift P-type implantation region 105b is about 1/2 to 2/3 of the drift P-type implantation region 105b.

Preferably, in Step 4, the right part of the drift P-type implantation region 105b is implanted in segments at equal intervals.

Preferably, in step 4, the implanted P-type ions are boron ions, the implantation energy is 1000 keV to 1500 keV, and the implantation dose is 1E12 to 1E14 per square centimeter.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.

Claims (8)

1. a kind of isolated form NLDMOS device, which is characterized in that left N-type deep trap, right N-type deep trap are formed in P-type silicon substrate Two independent N-type deep traps；

The left N-type deep trap, left part are formed with a p-well；

The p-well, left part are formed with a p-type heavily doped region and a source N-type heavily doped region；

Above the p-well right part and above the left N-type deep trap right part, it is formed with gate oxide；

The left N-type deep trap with above P-type silicon substrate between the right N-type deep trap and above the right N-type deep trap left part, It is formed with oxygen；

The right N-type deep trap, right part are formed with a drain terminal N-type heavily doped region；

Above the field oxygen left part and above the gate oxide, it is formed with grid polycrystalline silicon；

In P-type silicon substrate and right N-type deep trap below the field oxygen, it is formed with drift p-type injection region；

The drift p-type injection region, right part is section gap shape, and left part is not divided；

Drift p-type injection region right part, 1/2 to 2/3 for drift p-type injection region.

2. isolated form NLDMOS device according to claim 1, which is characterized in that

Drain terminal polysilicon field plate is formed with above the field oxygen right part；

Inter-level dielectric is covered in device surface；

The p-type heavily doped region is with the source N-type heavily doped region by the way that a metal of inter-level dielectric is passed through to be shorted together；

The drain terminal N-type heavily doped region is with the drain terminal polysilicon field plate by passing through another metal short circuit of inter-level dielectric one It rises.

3. isolated form NLDMOS device according to claim 1, which is characterized in that

A source p-type injection region is formed in the p-well.

4. a kind of manufacturing method of isolated form NLDMOS device, which is characterized in that include the following steps：

One, forms the independent N-type deep trap of left N-type deep trap, right N-type deep trap two in P-type silicon substrate by N-type ion implanting；

Two, utilize active area photoetching, open field oxygen zone domain, field oxygen zone are etched, in left N-type deep trap with the p-type between right N-type deep trap Above silicon substrate and above right N-type deep trap left part, raw long field oxide；

Trap injection zone is opened in three, photoetching, and p-well is formed in left N-type deep trap left part implanting p-type ion；

Four, carry out p-type ion implanting below the field oxygen, are formed in the P-type silicon substrate and right N-type deep trap below oxygen on the scene P-type of drifting about injection region；

The drift p-type injection region, right part are injected for section gap, and left part is does not divide injection；

Drift p-type injection region right part, 1/2 to 2/3 for drift p-type injection region；

Five, carry out subsequent process steps, complete the making of isolated form NLDMOS device.

5. the manufacturing method of isolated form NLDMOS device according to claim 4, which is characterized in that

Subsequent process steps in step 5, including：

(1) grows gate oxide, depositing polysilicon on silicon chip by thermal oxidation process；Then polysilicon gate etching is carried out, Form the grid polycrystalline silicon of isolated form NLDMOS device and drain terminal polysilicon field plate；

The grid polycrystalline silicon, above the p-well right part, above the left N-type deep trap right part and on the field oxygen left part Side；

The drain terminal polysilicon field plate, above the field oxygen right part；

(2) the carry out source and drain ion implanting of selectivity is respectively formed p-type heavily doped region and source N-type weight in the p-well left part Doped region forms drain terminal N-type heavily doped region in the right N-type deep trap right part；

(3) deposits inter-level dielectric, etches contact hole, then deposit metal, then etch required pattern, shape on silicon chip Into the source and the extraction metal of background region and the extraction metal of drain terminal of isolated form NLDMOS device, isolated form is finally completed The making of NLDMOS device.

6. the manufacturing method of isolated form NLDMOS device according to claim 4, which is characterized in that

In step 4, while p-type ion implanting is carried out in the p-well, a source p-type injection region is formed in the p-well.

7. the manufacturing method of isolated form NLDMOS device according to claim 4, which is characterized in that

In step 4, drift p-type injection region right part injects at equal intervals for segmentation.

8. the manufacturing method of isolated form NLDMOS device according to claim 4, which is characterized in that

In step 4, the p-type ion of injection is boron ion, and Implantation Energy is 1000kev to 1500kev, implantation dosage 1E12 It is every square centimeter to 1E14.