[go: up one dir, main page]

CN108666218A - 薄膜晶体管和显示基板及其制作方法、显示装置 - Google Patents

薄膜晶体管和显示基板及其制作方法、显示装置 Download PDF

Info

Publication number
CN108666218A
CN108666218A CN201710197332.7A CN201710197332A CN108666218A CN 108666218 A CN108666218 A CN 108666218A CN 201710197332 A CN201710197332 A CN 201710197332A CN 108666218 A CN108666218 A CN 108666218A
Authority
CN
China
Prior art keywords
layer
electrode
thin film
film transistor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710197332.7A
Other languages
English (en)
Inventor
舒适
徐传祥
罗腾
谷丰
张斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201710197332.7A priority Critical patent/CN108666218A/zh
Priority to EP17870620.6A priority patent/EP3602614A4/en
Priority to PCT/CN2017/108322 priority patent/WO2018176829A1/en
Priority to US15/768,634 priority patent/US10546885B2/en
Publication of CN108666218A publication Critical patent/CN108666218A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明涉及显示技术领域，公开了一种薄膜晶体管和显示基板及其制作方法、显示装置。所述制作方法通过一次构图工艺同时制得薄膜晶体管的有源层、源电极和漏电极，减少了一次构图工艺，使得掩膜板的数量减少，简化了产品的制作工艺，降低了生产成本。

Description

薄膜晶体管和显示基板及其制作方法、显示装置
技术领域
本发明涉及显示技术领域，特别是涉及一种薄膜晶体管和显示基板及其制作方法、显示装置。
背景技术
显示基板是平板显示的重要组件，控制像素的开关，显示面板的重要指标，如分辨率、刷新频率等都和显示基板相关。显示基板的最小组成单元是像素，像素中最关键的是半导体器件，半导体器件的性质决定了整个显示面板的品质。目前大尺寸、高分辨率、高频率是显示的发展趋势，对半导体器件提出的要求就是足够高的开态电流和较低的漏电流。分辨率越高、频率越高，留给一行像素的充电时间越短，为了再较短的时间完成充电，就必须提高半导体器件的开态电流。提高器件开态电流的方法主要是选择高迁移率的半导体材料。
低温多晶硅(LTPS)材料由于具有极高的迁移率，可以作为高性能显示设备的半导体材料，并且可以将驱动电路集成在玻璃基板上，实现窄边框和低功耗。但是，LTPS阵列基板的工艺难度较大，除了非晶硅退火均匀性控制、掺杂控制难度大之外，对材料的严格要求也提高了该技术的门槛，需要开发Mask减少的制作方法，以降低生产成本。
发明内容
本发明提供一种薄膜晶体管和显示基板及其制作方法、显示装置，用以减少制作工艺中使用的掩膜板数量，降低成本。
为解决上述技术问题，本发明实施例中提供一种薄膜晶体管的制作方法，包括：
在一基底上依次形成半导体层和源漏金属层；
对所述半导体层和源漏金属层进行一次构图工艺，形成薄膜晶体管的有源层、源电极和漏电极。
如上所述的制作方法，其中，还包括：
依次形成覆盖有源层、源电极和漏电极的栅绝缘层和层间绝缘层；
对所述层间绝缘层进行构图工艺，在所述层间绝缘层中形成一第一窗口，露出栅绝缘层；
在所述第一窗口中形成栅电极，所述栅电极在所述基底上的正投影位于所述有源层在所述基底上的正投影内。
如上所述的制作方法，其中，在依次形成半导体层和源漏金属层的步骤之前，所述制作方法还包括：
在所述基底上形成图案化的遮光层，所述有源层在所述基底上的正投影位于所述遮光层在所述基底上的正投影中。
如上所述的制作方法，其中，所述制作方法还包括：
在所述遮光层上形成缓冲层；
所述半导体层为多晶硅层，具体在所述缓冲层上形成非晶硅层，并对所述非晶硅层进行脱氢及准分子激光退火工艺形成所述多晶硅层。
本发明实施例中还提供一种显示基板的制作方法，包括制备薄膜晶体管的步骤，采用如上所述的制作方法制备所述薄膜晶体管。
如上所述的制作方法，其中，所述制作方法还包括：
在所述薄膜晶体管上形成钝化层；
在所述钝化层上形成透明导电层，对所述透明导电层进行构图工艺形成像素电极和第一电极；
形成贯穿所述钝化层、层间绝缘层和栅绝缘层的第一过孔和第二过孔，所述像素电极通过所述第一过孔与所述漏电极电性连接，所述第一电极通过所述第二过孔与所述源电极电性连接。
如上所述的制作方法，其中，在形成钝化层的步骤之前，所述制作方法还包括：
在所述薄膜晶体管上形成有机绝缘层的图形，所述有机绝缘层中具有一第二窗口，露出所述薄膜晶体管的源电极所在区域的至少一部分和漏电极所在区域的至少一部分；
在所述有机绝缘层和钝化层之间形成公共电极。
本发明实施例中还提供一种薄膜晶体管，包括设置在一基底上的有源层、源电极和漏电极，所述源电极和漏电极接触设置在所述有源层的背离所述基底的表面上，且所述源电极和漏电极在所述基底上的正投影位于所述有源层在所述基底上的正投影中。
如上所述的薄膜晶体管，其中，还包括：
覆盖所述有源层、源电极和漏电极的栅绝缘层；
设置在所述栅绝缘层上的层间绝缘层，所述层间绝缘层中具有一第一窗口，露出栅绝缘层；
栅电极，设置在所述第一窗口内，所述栅电极在所述基底上的正投影位于所述有源层在所述基底上的正投影内。
本发明实施例中还提供一种显示基板，包括如上所述的薄膜晶体管。
如上所述的显示基板，其中，所述显示基板还包括：
设置在所述薄膜晶体管上的钝化层；
同层设置在所述钝化层上的像素电极和第一电极，所述像素电极通过贯穿所述钝化层、层间绝缘层和栅绝缘层的第一过孔与所述漏电极电性连接，所述第一电极通过贯穿所述钝化层、层间绝缘层和栅绝缘层的第二过孔与所述源电极电性连接。
如上所述的显示基板，其中，所述显示基板还包括：
设置在所述薄膜晶体管上的有机绝缘层，所述钝化层设置在所述有机绝缘层上，所述有机绝缘层中具有一第二窗口，露出所述薄膜晶体管的源电极所在区域的至少一部分和漏电极所在区域的至少一部分；
设置在所述有机绝缘层和钝化层之间的公共电极。
本发明实施例中还提供一种显示装置，包括如上所述的显示基板。
本发明的上述技术方案的有益效果如下：
上述技术方案中，通过一次构图工艺同时制得薄膜晶体管的有源层、源电极和漏电极，减少了一次构图工艺，使得掩膜板的数量减少，简化了产品的制作工艺，降低了生产成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1表示本发明实施例中薄膜晶体管的制作流程图；
图2-图13表示本发明实施例中显示基板的制作过程图。
具体实施方式
下面将结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
实施例一
本实施例中提供一种薄膜晶体管的制作方法，用以减少制作过程中使用的掩膜板数量，简化制作工艺，降低生产成本。
参见图1所示，所述薄膜晶体管的制作方法包括：
在一基底上依次形成半导体层和源漏金属层；
对所述半导体层和源漏金属层进行一次构图工艺，形成薄膜晶体管的有源层、源电极和漏电极。
上述技术方案通过一次构图工艺同时制得薄膜晶体管的有源层、源电极和漏电极，减少了一次构图工艺，使得掩膜板的数量减少，简化了制作工艺，降低了生产成本。
其中，有源层的材料可以选择迁移率较高的低温多晶硅。当然，也可以选择单晶硅、金属氧化物半导体材料。
本发明的技术方案适用于顶栅型薄膜晶体管，也适用于底栅型薄膜晶体管。
本发明的薄膜晶体管可以但并不局限于应用在显示器件上，例如：应用在液晶显示装置的阵列基板上，应用在有机电致发光显示装置的显示基板上。
当本实施例中的薄膜晶体管为顶栅型薄膜晶体管时，如图1所示，所述制作方法还包括：
依次形成覆盖有源层、源电极和漏电极的栅绝缘层和层间绝缘层；
对所述层间绝缘层进行构图工艺，在所述层间绝缘层中形成一第一窗口，露出栅绝缘层；
在所述第一窗口中形成栅电极，所述栅电极在所述基底上的正投影位于所述有源层在所述基底上的正投影内。
上述技术方案在形成栅电极之前，在栅绝缘层上先形成层间绝缘层，能够有效减小栅电极与源电极和漏电极之间的寄生电容。另外，栅绝缘层和层间绝缘层的分层结构设计可以确保栅绝缘层和层间绝缘层具有较好的刻蚀选择性。
本实施例中，在依次形成半导体层和源漏金属层的步骤之前，所述制作方法还包括：
在所述基底上形成图案化的遮光层，所述有源层在所述基底上的正投影位于所述遮光层在所述基底上的正投影中。
上述步骤形成的遮光层能够阻挡从有源层的背离源电极和漏电极的一侧的光线照射有源层，防止光照影响有源层的半导体性能。所述遮光层可以由遮光的绝缘材料制得。
当薄膜晶体管的半导体层为多晶硅层时，所述制作方法还包括：
在所述遮光层上形成缓冲层；
具体在所述缓冲层上形成非晶硅层，并对所述非晶硅层进行脱氢及准分子激光退火工艺形成所述多晶硅层。所述缓冲层可以由氮化硅、氧化硅或氮氧化硅材料制得，可以为单层或复合层结构，用于防止遮光层影响半导体层的性能。
本实施例中还提供一种显示基板的制作方法，包括制备薄膜晶体管的步骤，并采用实施例一中的制作方法制备所述薄膜晶体管，以减少制作工艺中使用的掩膜板数量，简化制作工艺，降低生产成本。
当所述显示基板为薄膜晶体管阵列基板时，所述制作方法还包括：
在所述薄膜晶体管上形成钝化层；
在所述钝化层上形成透明导电层，对所述透明导电层进行构图工艺形成像素电极和第一电极；
形成贯穿所述钝化层、层间绝缘层和栅绝缘层的第一过孔和第二过孔，所述像素电极通过所述第一过孔与所述漏电极电性连接，所述第一电极通过所述第二过孔与所述源电极电性连接。
上述步骤通过一次刻蚀工艺形成贯穿所述钝化层、层间绝缘层和栅绝缘层的过孔，减少制作工艺中使用的掩膜板数量。并在形成像素电极的同时，形成与漏电极连接的第一电极，可作为测试用，用以向源电极施加测试电压。
对于横向电场型薄膜晶体管阵列基板，在形成钝化层的步骤之前，所述制作方法还包括：
在所述薄膜晶体管上形成有机绝缘层的图形，所述有机绝缘层中具有一第二窗口，露出所述薄膜晶体管的源电极的至少一部分和漏电极的至少一部分；
在所述有机绝缘层和钝化层之间形成公共电极。
上述技术方案在形成公共电极之前，在位于薄膜晶体管和公共电极之间的有机绝缘层上形成第二窗口，以露出所述薄膜晶体管的源电极所在区域的至少一部分和漏电极所在区域的至少一部分，从而不会增加像素电极与漏电极之间的绝缘层厚度，以不影响贯穿所述钝化层、层间绝缘层和栅绝缘层的过孔的质量。
结合图2-图13所示，以横向电场型薄膜晶体管阵列基板为例，显示基板的制作方法具体包括：
步骤S1、在一透明的基底100上形成遮光层8，并形成覆盖遮光层8的缓冲层107，参见图2所示；
缓冲层107可以为由氮化硅、氧化硅或氮氧化硅等绝缘材料制得的单层或复合层结构，一方面可以阻挡遮光层8影响薄膜晶体管的性能，另一方面可以为薄膜晶体管提供平坦的制作表面。
步骤S2、通过成膜工艺(如：沉积、溅射)在完成步骤S1的基底100上依次形成半导体层105和源漏金属层106，如图2所示；对半导体层105和源漏金属层106进行一次构图工艺形成有源层1、源电极2和漏电极3，结合图6所示；
有源层1的材料可以为低温多晶硅，也可以为金属氧化物半导体，如：HIZO、ZnO、TiO2、CdSnO、MgZnO、IGO、IZO、ITO或IGZO。当有源层1由低温多晶硅材料制得时，半导体层105为多晶硅层。则形成半导体层105的步骤可以为：首先在缓冲层107上形成非晶硅层，并对所述非晶硅层进行脱氢及准分子激光退火工艺形成多晶硅层105。
对半导体层105和源漏金属层106进行的一次构图工艺具体包括：
首先，在源漏金属层106上形成光刻胶21，并利用半色调或灰色调掩膜板对光刻胶21进行曝光，显影后，形成光刻胶21的图形，包括光刻胶完全保留区域、光刻胶部分保留区域和光刻胶不保留区域，其中，光刻胶完全保留区域对应源电极和漏电极所在的区域，光刻胶部分保留区域对应源电极和漏电极之间的区域，光刻胶不保留区域对应其他区域；采用刻蚀工艺去除光刻胶不保留区域的半导体层105和源漏金属层106，形成源漏金属层的第一图形20和有源层1，结合图2和图3所示；
之后，通过灰化工艺去除光刻胶部分保留区域的光刻胶，如图4所示；采用刻蚀工艺去除光刻胶部分保留区域的源漏金属层，形成源电极2和漏电极3的图形，如图5所示；
最后，剥离剩余的光刻胶，形成源电极2和漏电极3，如图6所示。
步骤S3、通过成膜工艺(如：沉积、涂覆)在完成步骤S2的基底100上依次形成栅绝缘层101和层间绝缘层102，对层间绝缘层102进行构图工艺，在层间绝缘层102中形成第一窗口10，露出栅绝缘层101，如图7所示；
栅绝缘层101和层间绝缘层102可以为由氮化硅、氧化硅或氮氧化硅等绝缘材料制得的单层或复合层结构。
例如：栅绝缘层101由氮化硅或氧化硅制得，厚度为400-800；层间绝缘层102可以由氮化硅制得，厚度为1000-3000；层间绝缘层102也可以由氧化硅制得，厚度为2000-6000。栅绝缘层101和层间绝缘层102的分层结构设计可以确保栅绝缘层101和层间绝缘层102具有较好的刻蚀选择性。
步骤S4、在第一窗口10中形成栅电极4，结合图7和图8所示；
步骤S5、在完成步骤S4的基底100上形成有机绝缘层104，对有机绝缘层104进行构图工艺，在有机绝缘层104中形成第二窗口11，露出所述薄膜晶体管的源电极2的至少一部分和漏电极3的至少一部分，如图9所示；
在形成栅电极4之后，可以对有源层1的与源电极2接触的源区和与漏电极3接触的漏区进行掺杂，并在有源层1的靠近漏区的部分进行轻掺杂。
步骤S6、在有机绝缘层104上形成公共电极7，如图10所示；
步骤S7、在完成步骤S7的基底100上形成钝化层103，如图11所示；
步骤S8、通过一次刻蚀工艺(如：干法刻蚀)形成贯穿钝化层103、层间绝缘层102和栅绝缘层101的第一过孔12和第二过孔13，如图12所示；
步骤S9、在完成步骤S8的基底100上形成像素电极5和第一电极6，像素电极5通过第一过孔12与漏电极3电性连接，第一电极6通过第二过孔13与源电极2电性连接，如图13所示。
具体通过对同一透明导电层的构图工艺形成像素电极5和第一电极6。第一电极6可以用于输入测试信号，以便于对产品质量进行测试。
至此完成显示基板的制作。
其中，源电极2、漏电极3和栅电极4的材料可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，可以是单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。像素电极5和公共电极7由透明导电材料制得，如：HIZO、ZnO、TiO2、CdSnO、MgZnO、IGO、IZO、ITO或IGZO。
在实际制作过程中，还可以根据需要对上述步骤进行合理调整，例如：可以调整像素电极和公共电极的位置关系，公共电极还可以直接接触设置在基底上，其都属于本发明的保护范围。
实施例二
本实施例中提供一种采用实施例一中的制作方法制得薄膜晶体管，结合图13所示，所述薄膜晶体管包括设置在一基底100上的有源层1、源电极2和漏电极3，源电极2和漏电极3接触设置在有源层1的背离基底100的表面上，且源电极2和漏电极3在基底100上的正投影位于有源层1在基底100上的正投影中。
上述薄膜晶体管的有源层、源电极和漏电极通过一次构图工艺同时制得，减少了一次构图工艺，使得掩膜板的数量减少，简化了制作工艺，降低了生产成本。
本发明的技术方案适用于顶栅型薄膜晶体管，也适用于底栅型薄膜晶体管。
当本实施例中的薄膜晶体管为顶栅型薄膜晶体管时，还包括：
覆盖有源层1、源电极2和漏电极3的栅绝缘层101；
设置在栅绝缘层101上的层间绝缘层102，层间绝缘层102中具有一第一窗口，露出栅绝缘层101；
栅电极4，设置在所述第一窗口内，栅电极4在基底100上的正投影位于有源层1在基底100上的正投影内。
上述顶栅型薄膜晶体管，在栅电极与源电极、漏电极之间增加了层间绝缘层，够有效减小栅电极与源电极和漏电极之间的寄生电容。
本实施例中，所述薄膜晶体管还可以包括设置在基底100上的图案化的遮光层8，遮光层8位于有源层1的靠近基底100的一侧，且有源层1在基底100上的正投影位于遮光层8在基底100上的正投影中。通过设置遮光层8，能够阻挡从有源层1的背离源电极2和漏电极3的一侧的光线照射有源层，防止光照影响有源层1的半导体性能。
可选的，遮光层8和有源层1之间还设置有缓冲层107，用于防止遮光层8影响有源层1的半导体性能。
本实施例中还提供一种显示基板，包括上述的薄膜晶体管，由于通过一次构图工艺同时制得薄膜晶体管的有源层、源电极和漏电极，从而减少了一次构图工艺，使得掩膜板的数量减少，简化了制作工艺，降低了生产成本。
当所述显示基板为薄膜晶体管阵列基板时，如图13所示，所述显示基板还包括：
设置在所述薄膜晶体管上的钝化层103；
同层设置在钝化层103上的像素电极5和第一电极6，像素电极5通过贯穿钝化层103、层间绝缘层102和栅绝缘层101的第一过孔12与漏电极3电性连接，第一电极6通过贯穿钝化层103、层间绝缘层102和栅绝缘层101的第二过孔13与源电极2电性连接。
上述薄膜晶体管阵列基板，贯穿所述钝化层、层间绝缘层和栅绝缘层的第一过孔和第二过孔可以通过一次刻蚀工艺制得，一减少制作工艺中使用的掩膜板数量。并在形成像素电极的同时，形成与漏电极连接的第一电极，可作为测试用。而且本发明中源电极和漏电极设置在有源层上的接触结构，能够减少像素电极与漏电极搭接的电阻，并且减小了厚度差，在后续的刻蚀工艺时，有利于减少不良。
对于横向电场型薄膜晶体管阵列基板，如图13所示，所述显示基板还包括：
设置在所述薄膜晶体管上的有机绝缘层104，钝化层103设置在有机绝缘层104上，有机绝缘层104中具有一第二窗口，露出所述薄膜晶体管的源电极2所在区域的至少一部分和漏电极3所在区域的至少一部分；
设置在有机绝缘层104和钝化层103之间的公共电极7。
上述显示基板，在位于薄膜晶体管和公共电极之间的有机绝缘层上开设第二窗口，以露出所述薄膜晶体管的源电极所在区域的至少一部分和漏电极所在区域的至少一部分，从而不会增加像素电极与漏电极之间的绝缘层厚度，以不影响贯穿所述钝化层、层间绝缘层和栅绝缘层的过孔的质量。
本实施例中还提供一种显示装置，包括如上所述的显示基板，以简化产品的制作工艺，降低生产成本。
所述显示装置可以为液晶显示装置、有机电致发光显示装置或其它显示装置。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本发明的保护范围。

Claims (13)

1.一种薄膜晶体管的制作方法，其特征在于，包括：
在一基底上依次形成半导体层和源漏金属层；
对所述半导体层和源漏金属层进行一次构图工艺，形成薄膜晶体管的有源层、源电极和漏电极。
2.根据权利要求1所述的制作方法，其特征在于，还包括：
依次形成覆盖有源层、源电极和漏电极的栅绝缘层和层间绝缘层；
对所述层间绝缘层进行构图工艺，在所述层间绝缘层中形成一第一窗口，露出栅绝缘层；
在所述第一窗口中形成栅电极，所述栅电极在所述基底上的正投影位于所述有源层在所述基底上的正投影内。
3.根据权利要求2所述的制作方法，其特征在于，在依次形成半导体层和源漏金属层的步骤之前，所述制作方法还包括：
在所述基底上形成图案化的遮光层，所述有源层在所述基底上的正投影位于所述遮光层在所述基底上的正投影中。
4.根据权利要求3所述的制作方法，其特征在于，所述制作方法还包括：
在所述遮光层上形成缓冲层；
所述半导体层为多晶硅层，具体在所述缓冲层上形成非晶硅层，并对所述非晶硅层进行脱氢及准分子激光退火工艺形成所述多晶硅层。
5.一种显示基板的制作方法，包括制备薄膜晶体管的步骤，其特征在于，采用权利要求1-4任一项所述的制作方法制备所述薄膜晶体管。
6.根据权利要求5所述的制作方法，其特征在于，所述制作方法还包括：
在所述薄膜晶体管上形成钝化层；
在所述钝化层上形成透明导电层，对所述透明导电层进行构图工艺形成像素电极和第一电极；
形成贯穿所述钝化层、层间绝缘层和栅绝缘层的第一过孔和第二过孔，所述像素电极通过所述第一过孔与所述漏电极电性连接，所述第一电极通过所述第二过孔与所述源电极电性连接。
7.根据权利要求6所述的制作方法，其特征在于，在形成钝化层的步骤之前，所述制作方法还包括：
在所述薄膜晶体管上形成有机绝缘层的图形，所述有机绝缘层中具有一第二窗口，露出所述薄膜晶体管的源电极所在区域的至少一部分和漏电极所在区域的至少一部分；
在所述有机绝缘层和钝化层之间形成公共电极。
8.一种薄膜晶体管，包括设置在一基底上的有源层、源电极和漏电极，其特征在于，所述源电极和漏电极接触设置在所述有源层的背离所述基底的表面上，且所述源电极和漏电极在所述基底上的正投影位于所述有源层在所述基底上的正投影中。
9.根据权利要求8所述的薄膜晶体管，其特征在于，还包括：
覆盖所述有源层、源电极和漏电极的栅绝缘层；
设置在所述栅绝缘层上的层间绝缘层，所述层间绝缘层中具有一第一窗口，露出栅绝缘层；
栅电极，设置在所述第一窗口内，所述栅电极在所述基底上的正投影位于所述有源层在所述基底上的正投影内。
10.一种显示基板，其特征在于，包括权利要求8或9所述的薄膜晶体管。
11.根据权利要求10所述的显示基板，其特征在于，所述显示基板还包括：
设置在所述薄膜晶体管上的钝化层；
同层设置在所述钝化层上的像素电极和第一电极，所述像素电极通过贯穿所述钝化层、层间绝缘层和栅绝缘层的第一过孔与所述漏电极电性连接，所述第一电极通过贯穿所述钝化层、层间绝缘层和栅绝缘层的第二过孔与所述源电极电性连接。
12.根据权利要求11所述的显示基板，其特征在于，所述显示基板还包括：
设置在所述薄膜晶体管上的有机绝缘层，所述钝化层设置在所述有机绝缘层上，所述有机绝缘层中具有一第二窗口，露出所述薄膜晶体管的源电极所在区域的至少一部分和漏电极所在区域的至少一部分；
设置在所述有机绝缘层和钝化层之间的公共电极。
13.一种显示装置，其特征在于，包括权利要求10-12任一项所述的显示基板。
CN201710197332.7A 2017-03-29 2017-03-29 薄膜晶体管和显示基板及其制作方法、显示装置 Pending CN108666218A (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201710197332.7A CN108666218A (zh) 2017-03-29 2017-03-29 薄膜晶体管和显示基板及其制作方法、显示装置
EP17870620.6A EP3602614A4 (en) 2017-03-29 2017-10-30 THIN LAYER TRANSISTOR AND DISPLAY SUBSTRATE, RELATED MANUFACTURING PROCESS AND DISPLAY DEVICE
PCT/CN2017/108322 WO2018176829A1 (en) 2017-03-29 2017-10-30 Thin film transistor and display substrate, fabrication method thereof, and display device
US15/768,634 US10546885B2 (en) 2017-03-29 2017-10-30 Thin film transistor and display substrate, fabrication method thereof, and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710197332.7A CN108666218A (zh) 2017-03-29 2017-03-29 薄膜晶体管和显示基板及其制作方法、显示装置

Publications (1)

Publication Number Publication Date
CN108666218A true CN108666218A (zh) 2018-10-16

Family

ID=63674164

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710197332.7A Pending CN108666218A (zh) 2017-03-29 2017-03-29 薄膜晶体管和显示基板及其制作方法、显示装置

Country Status (4)

Country Link
US (1) US10546885B2 (zh)
EP (1) EP3602614A4 (zh)
CN (1) CN108666218A (zh)
WO (1) WO2018176829A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109212854A (zh) * 2018-08-29 2019-01-15 武汉华星光电技术有限公司 一种ltps阵列基板的制造方法
CN111048524A (zh) * 2019-11-26 2020-04-21 深圳市华星光电半导体显示技术有限公司 阵列基板及制备方法、显示面板
CN113113424A (zh) * 2021-03-17 2021-07-13 武汉华星光电半导体显示技术有限公司 显示面板
CN113707692A (zh) * 2021-07-13 2021-11-26 信利（惠州）智能显示有限公司 Amoled显示屏制造方法及结构
CN112736104B (zh) * 2020-12-28 2023-08-11 上海奕瑞光电子科技股份有限公司 平板探测器的制备方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10720454B2 (en) * 2018-06-05 2020-07-21 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Manufacturing method for array substrate and liquid crystal display device
CN112331679B (zh) * 2020-11-05 2022-08-19 湖北长江新型显示产业创新中心有限公司 显示装置
CN114520239A (zh) * 2020-11-20 2022-05-20 京东方科技集团股份有限公司 X射线平板探测器及其制作方法、探测装置、成像系统
KR20230103661A (ko) * 2021-12-31 2023-07-07 엘지디스플레이 주식회사 표시패널 및 표시장치
CN114639688B (zh) * 2022-03-14 2025-04-08 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板及显示装置
CN114883343B (zh) * 2022-04-21 2024-03-26 北海惠科光电技术有限公司 薄膜晶体管、显示基板和薄膜晶体管的制备方法
WO2024165987A1 (en) * 2023-02-09 2024-08-15 Zinite Corporation Passivation elements of a thin film transistor

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102318073A (zh) * 2009-03-31 2012-01-11 松下电器产业株式会社 挠性半导体装置及其制造方法
CN102683338A (zh) * 2011-09-13 2012-09-19 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板及其制造方法
CN103367458A (zh) * 2012-04-03 2013-10-23 元太科技工业股份有限公司 薄膜晶体管及其制造方法
CN105655352A (zh) * 2016-01-14 2016-06-08 武汉华星光电技术有限公司 低温多晶硅tft阵列基板的制作方法
US20160225879A1 (en) * 2011-12-22 2016-08-04 Innocom Technology(Shenzhen) Co., Ltd. Manufacturing method of thin film transistor substrate
CN105938800A (zh) * 2016-07-01 2016-09-14 深圳市华星光电技术有限公司 薄膜晶体管的制造方法及阵列基板的制造方法
CN106328586A (zh) * 2016-08-24 2017-01-11 武汉华星光电技术有限公司 低温多晶硅阵列基板的制备方法、阵列基板以及显示面板
CN106445251A (zh) * 2016-12-27 2017-02-22 武汉华星光电技术有限公司 内嵌式触控面板及其阵列基板

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI383502B (zh) * 2007-10-02 2013-01-21 Chunghwa Picture Tubes Ltd 畫素結構及其製造方法
JP5294929B2 (ja) * 2009-03-06 2013-09-18 シャープ株式会社 半導体装置、ｔｆｔ基板、および表示装置
KR101305377B1 (ko) * 2009-06-16 2013-09-06 엘지디스플레이 주식회사 상부발광 방식 유기전계 발광소자 및 그 제조 방법
US8648397B2 (en) * 2009-12-17 2014-02-11 Sharp Kabushiki Kaisha Semiconductor device, active matrix substrate and display device
KR101108176B1 (ko) * 2010-07-07 2012-01-31 삼성모바일디스플레이주식회사 더블 게이트형 박막 트랜지스터 및 이를 구비한 유기 발광 표시 장치
TW202414842A (zh) * 2011-05-05 2024-04-01 日商半導體能源研究所股份有限公司 半導體裝置及其製造方法
KR20130033676A (ko) 2011-09-27 2013-04-04 엘지디스플레이 주식회사 프린지 필드 스위칭 모드 액정표시장치
CN103915380A (zh) * 2014-03-31 2014-07-09 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置
CN104360557B (zh) 2014-11-26 2017-04-26 京东方科技集团股份有限公司 阵列基板及其制造方法，以及显示装置
JP6662665B2 (ja) * 2015-03-19 2020-03-11 株式会社半導体エネルギー研究所 液晶表示装置及び該液晶表示装置を用いた電子機器

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102318073A (zh) * 2009-03-31 2012-01-11 松下电器产业株式会社 挠性半导体装置及其制造方法
CN102683338A (zh) * 2011-09-13 2012-09-19 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板及其制造方法
US20160225879A1 (en) * 2011-12-22 2016-08-04 Innocom Technology(Shenzhen) Co., Ltd. Manufacturing method of thin film transistor substrate
CN103367458A (zh) * 2012-04-03 2013-10-23 元太科技工业股份有限公司 薄膜晶体管及其制造方法
CN105655352A (zh) * 2016-01-14 2016-06-08 武汉华星光电技术有限公司 低温多晶硅tft阵列基板的制作方法
CN105938800A (zh) * 2016-07-01 2016-09-14 深圳市华星光电技术有限公司 薄膜晶体管的制造方法及阵列基板的制造方法
CN106328586A (zh) * 2016-08-24 2017-01-11 武汉华星光电技术有限公司 低温多晶硅阵列基板的制备方法、阵列基板以及显示面板
CN106445251A (zh) * 2016-12-27 2017-02-22 武汉华星光电技术有限公司 内嵌式触控面板及其阵列基板

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109212854A (zh) * 2018-08-29 2019-01-15 武汉华星光电技术有限公司 一种ltps阵列基板的制造方法
WO2020042278A1 (zh) * 2018-08-29 2020-03-05 武汉华星光电技术有限公司 一种ltps阵列基板的制造方法
US11522070B2 (en) 2018-08-29 2022-12-06 Wuhan China Star Optoelectronics Technology Co., Ltd Manufacturing method of low temperature poly-silicon substrate (LTPS)
CN111048524A (zh) * 2019-11-26 2020-04-21 深圳市华星光电半导体显示技术有限公司 阵列基板及制备方法、显示面板
CN112736104B (zh) * 2020-12-28 2023-08-11 上海奕瑞光电子科技股份有限公司 平板探测器的制备方法
CN113113424A (zh) * 2021-03-17 2021-07-13 武汉华星光电半导体显示技术有限公司 显示面板
CN113113424B (zh) * 2021-03-17 2024-02-02 武汉华星光电半导体显示技术有限公司 显示面板
CN113707692A (zh) * 2021-07-13 2021-11-26 信利（惠州）智能显示有限公司 Amoled显示屏制造方法及结构

Also Published As

Publication number Publication date
US20190067340A1 (en) 2019-02-28
WO2018176829A1 (en) 2018-10-04
US10546885B2 (en) 2020-01-28
EP3602614A1 (en) 2020-02-05
EP3602614A4 (en) 2020-12-23

Similar Documents

Publication Publication Date Title
CN108666218A (zh) 薄膜晶体管和显示基板及其制作方法、显示装置
CN103219391B (zh) 一种薄膜晶体管及其制作方法、阵列基板和显示装置
JP5775253B2 (ja) 薄膜トランジスタ基板とその製造方法
CN105470197B (zh) 低温多晶硅阵列基板的制作方法
CN104362125B (zh) 阵列基板及其制作方法、显示装置
CN105489552B (zh) Ltps阵列基板的制作方法
CN104022126B (zh) 一种阵列基板、其制作方法及显示装置
CN104218041B (zh) 阵列基板及制备方法和显示装置
CN109037150B (zh) 金属氧化物半导体薄膜晶体管阵列基板及其制作方法
CN105573549A (zh) 阵列基板、触控屏和触控显示装置及其制作方法
CN104867870B (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
CN103311310A (zh) 一种薄膜晶体管及其制备方法、阵列基板
CN104465788A (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN105702623A (zh) Tft阵列基板的制作方法
CN103227147A (zh) Tft-lcd阵列基板及其制造方法、液晶显示器
CN103915451B (zh) 一种阵列基板及其制造方法、显示装置
CN105097552A (zh) 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
CN107808826A (zh) 一种底发射顶栅自对准薄膜晶体管的制备方法
CN103745954B (zh) 显示装置、阵列基板及其制造方法
CN105374749B (zh) 一种薄膜晶体管及其制造方法
CN105529366A (zh) 金属氧化物薄膜晶体管及其制造方法
CN108550625A (zh) 一种薄膜晶体管及其制作方法
CN105140239B (zh) 一种薄膜晶体管、其制作方法、阵列基板及其制作方法
US10205029B2 (en) Thin film transistor, manufacturing method thereof, and display device
CN104157609B (zh) Tft基板的制作方法及其结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20181016