CN108573932A - Silicon carbide substrate for epitaxy and semiconductor chip - Google Patents

Abstract

The present invention provides a silicon carbide substrate and a semiconductor chip for epitaxy, wherein the silicon carbide substrate has a surface and a plurality of patterned structures protruding from the surface, and the crystal plane of the surface is the (0001) plane; The width of the patterned structure gradually decreases from bottom to top and forms at least one inclined side, and the crystal plane of the side is (-1,0,1,2) plane. A gallium nitride epitaxial layer is provided on the top of the silicon carbide substrate to form the semiconductor chip. Therefore, laterally extending dislocation defects are formed at the bottom of the gallium nitride epitaxial layer, which makes it difficult to form upwardly extending through dislocation defects, allowing the gallium nitride epitaxial layer to have good epitaxial quality.

Description

Silicon carbide substrate and semiconductor chip for epitaxy

technical field

The invention relates to semiconductor epitaxy, in particular to a silicon carbide substrate and a semiconductor chip for epitaxy.

Background technique

Existing semiconductor components, such as semiconductor light-emitting components, high-electron-mobility field-effect transistors (High-electron-mobility transistor, HEMT), laser diodes, light-emitting diodes, etc., are mostly provided on a substrate with gallium nitride epitaxy layer, and then fabricate the structure of the component on the gallium nitride epitaxial layer.

The current technology is to set the gallium nitride epitaxial layer on the sapphire substrate, but there is a lattice mismatch and a difference in thermal expansion coefficient between sapphire and gallium nitride. Therefore, the quality of the formed gallium nitride epitaxial layer Often poor. The quality of the GaN epitaxial layer is related to the performance of the device. In order to improve the quality of the GaN epitaxial layer, most of the current methods are to set a buffer layer between the sapphire substrate and the GaN epitaxial layer, and then grow the epitaxial layer on the buffer layer. The purpose of the buffer layer is to reduce lattice mismatch, reduce defect density, or reduce the difference in thermal expansion coefficient between the substrate and the epitaxial layer, thereby improving the quality of the epitaxial layer.

Compared with sapphire substrates, the lattice matching between SiC substrates and GaN is better, so the quality of GaN epitaxial layers disposed on SiC substrates will be better than those disposed on sapphire substrates. The quality of GaN epitaxial layers.

How to further improve the quality of the gallium nitride epitaxial layer on the silicon carbide substrate is the research and development direction of relevant scholars and manufacturers.

Contents of the invention

In view of this, the object of the present invention is to provide a silicon carbide substrate for epitaxy and a semiconductor chip, which can obtain a gallium nitride epitaxy layer with better quality.

In order to achieve the above object, the silicon carbide substrate for epitaxy provided by the present invention has a top, and the top is used for setting a gallium nitride epitaxial layer, and the top has a surface and a plurality of protrusions formed from the surface. A patterned structure, wherein the crystal plane of the surface is a (0001) plane; the width of the patterned structure gradually decreases from bottom to top and at least one inclined side is formed, and the crystal plane of the side is (-1 ,0,1,2) surface.

In order to achieve the above object, the present invention also provides a semiconductor chip, comprising the above-mentioned silicon carbide substrate for epitaxy, and a gallium nitride epitaxial layer disposed on the top of the silicon carbide substrate for epitaxy.

The advantage of the present invention is that, since the crystal plane formed on the side of the patterned structure of the silicon carbide substrate for epitaxy is a (-1,0,1,2) plane, it is beneficial to the growth of the gallium nitride epitaxial layer, therefore, the gallium nitride The epitaxial layer can be grown from the side of the patterned structure first, and then accumulated laterally and upwardly. In this way, laterally extending dislocation defects are formed at the bottom of the GaN epitaxial layer, and it is difficult to form penetrating dislocation defects extending upward, so that the GaN epitaxial layer has good epitaxial quality.

Description of drawings

1 is a schematic diagram of a silicon carbide substrate according to a first embodiment of the present invention;

2A to 2E are schematic diagrams of the manufacturing process of the silicon carbide substrate according to the first embodiment of the present invention;

3 is a schematic diagram of the initial stage of growing a gallium nitride epitaxial layer on a silicon carbide substrate according to the first embodiment of the present invention;

4 is a schematic diagram of a semiconductor chip according to a first embodiment of the present invention;

5 is an image of the semiconductor chip of the first embodiment of the present invention observed by a transmission electron microscope;

6 is a schematic diagram of a silicon carbide substrate according to a second embodiment of the present invention;

7 is a schematic diagram of the initial stage of growing a gallium nitride epitaxial layer on a silicon carbide substrate according to the second embodiment of the present invention;

8 is a schematic diagram of a semiconductor chip according to a second embodiment of the present invention;

FIG. 9 is an image of the semiconductor chip according to the second embodiment of the present invention observed by a transmission electron microscope.

Symbol Description:

1. Semiconductor chips;

10. Silicon carbide substrate;

12. Top;

122. surface;

124. Patterned structure;

124a, side;

16. GaN epitaxial layer;

16a, gallium nitride;

162. Connection surface;

164. Disparity defects;

2. Semiconductor chips;

20. Silicon carbide substrate;

202. Patterned structure;

202a, top surface;

202b, side;

204. surface;

22. GaN epitaxial layer;

22a, gallium nitride;

222. Connection surface;

224. Disparity defects;

100. Silicon carbide substrate;

102. Upper surface;

104. Hard shielding;

106. Patterned photoresist layer;

θ, included angle;

W, width;

H, height;

D, D', spacing.

Detailed ways

Specific implementations of the silicon carbide substrate for epitaxy and the semiconductor chip provided by the present invention will be described in detail below in conjunction with the accompanying drawings.

Please refer to FIG. 1 , which is a silicon carbide substrate 10 according to a first embodiment of the present invention. The silicon carbide substrate 10 has a top 12, and the top 12 has a surface 122 and protrudes from the surface 122. A plurality of patterned structures 124 .

Wherein, the crystal plane of the surface 122 is a (0001) plane. The patterned structure 124 is in the shape of a pyramid in this embodiment, and its width gradually decreases from bottom to top to form at least one inclined side 124a. The crystal plane of the side 124a is (-1,0,1, 2) Faces, in this embodiment, the number of the at least one side 124a is six faces. An angle θ is formed between each of the side surfaces 124a and the surface 122 (that is, the angle between the (0001) plane and the (-1,0,1,2) plane). The angle θ is 110-130 degrees, preferably 121.5 degrees. The maximum width W of the bottom of each patterned structure 124 is 1-5 microns, preferably 1-3 microns; the height H from the surface 122 to the highest point of each patterned structure 124 is 0.3-5 microns. 2 microns. The distance D between the bottoms of two adjacent patterned structures 124 is 2-3 microns, preferably 2.5 microns. The surface roughness of each side 124 a is smaller than the surface roughness of the surface 122 .

Please refer to FIG. 2A to FIG. 2E , which are schematic diagrams of the manufacturing process of the silicon carbide substrate according to the first embodiment of the present invention. The manufacturing process of the silicon carbide substrate 10 includes the following steps:

(a) Referring to FIG. 2A , take a silicon carbide substrate 100 having an upper surface 102 .

(b) Referring to FIG. 2B , a hard mask 104 is disposed on the upper surface 102 of the silicon carbide substrate. In this embodiment, 500 nm of SiO ₂ is deposited by PECVD as the hard mask 104 .

(c) Referring to FIG. 2C , a patterned photoresist layer 106 is fabricated on the hard mask 104 by lithography technology. In this embodiment, the photoresist layer 106 is a dot array photoresist with a diameter of 2 μm and a pitch of 1 μm.

(d) Please refer to FIG. 2D, remove the area not covered by the patterned photoresist layer 106 in the hard mask 104 by an etching process, in this embodiment, use a multi-chamber plasma etching system (Multi-chamber Plasma Etching System) performs a first-stage dry etching process for 170 seconds to transfer the photoresist pattern onto the hard mask 104 .

(e) Referring to FIG. 2E , a dry etching process is used to remove the area of the silicon carbide substrate 100 not covered by the hard mask 104 with lateral etching. In this embodiment, a second-stage dry etching process is performed with a multi-chamber plasma etching system (Multi-chamber PlasmaEtching System) to form the surface 122 and the Patterned structure 124 . Finally, soak in BOE (Buffered Oxide Etecher) to etch and remove the photoresist layer 106 and the hard mask 104 , thus completing the fabrication of the silicon carbide substrate 10 of this embodiment. The dry etching process can adopt physical etching, chemical etching or physical and chemical combined etching.

Due to the dry etching process, compared with the side surface 124a of the patterned structure 124, the surface 122 is more damaged, so the surface 122 forms a damaged area with defects such as microcracks and greater stress, so the The surface roughness of the surface 122 is greater than the surface roughness of the side surface 124 a of the patterned structure 124 . Of course, laser, ion distribution or bombardment, electron bombardment of the surface 122 can also be used to form the damaged area.

Please refer to Fig. 3 and Fig. 4, the process of making the semiconductor chip 1 of this embodiment is: grow a gallium nitride epitaxial layer 16 on the described silicon carbide substrate 10 by MOCVD, on the described gallium nitride epitaxial layer 16 In the initial stage of growth, gallium nitride 16a first grows on the side surface 124a of the patterned structure 124 (see FIG. 3 ), and then gradually extends laterally and accumulates to cover the surface 122, and at the same time accumulates upward to form a carbon layer directly disposed on the surface 122. The gallium nitride epitaxial layer 16 on top of the silicon substrate 10 . Since the gallium nitride 16a is first grown from the side surface 124a of the patterned structure 124 and extended to cover the surface 122, the gallium nitride epitaxial layer 16 is directly connected to the side surface 124a of the patterned structure 124 and directly Contact the surface 122 . Then the semiconductor chip 1 of this embodiment is formed (see FIG. 4 ). The gallium nitride epitaxial layer 16 has a plurality of connection surfaces 162, each of the connection surfaces 162 is respectively connected to the side 124a whose crystal plane is a (-1, 0, 1, 2) plane, and each of the connection surfaces The crystal plane of 162 is (-1,1,0,1) plane.

The gallium nitride epitaxial layer 16 has a dislocation defect (dislocation) 164 extending laterally at the position connecting each of the side surfaces 124a, and the gallium nitride epitaxial layer 16 directly contacts the surface 122 The site does not have upwardly extending dislocations. Therefore, the laterally extending dislocation defects 164 are not easy to extend upward to form penetrating dislocations, so that the quality of the GaN epitaxial layer 16 above the patterned structure 124 is higher, which is beneficial to subsequent manufacturing processes.

Please refer to FIG. 5 , which is an image of the interface between the gallium nitride epitaxial layer 16 and the silicon carbide substrate 10 of the semiconductor chip 1 of the present embodiment observed with a transmission electron microscope (TEM), wherein (b) is an enlarged view of (a) image. It can be seen from FIG. 5 that laterally extending dislocation defects can be clearly observed in the region of the GaN epitaxial layer 16 adjacent to the side surface 124a of the patterned structure 124, while the GaN epitaxial layer 16 is adjacent to the silicon carbide substrate. The region of the surface 122 of 10 has no dislocation defects extending upwards, so it can be seen that the gallium nitride epitaxial layer 16 is first grown from the side surface 124a of the patterned structure 124 when growing, and it is not easy to grow on the side surface 124a of the patterned structure 124. The above-mentioned surface 122 grows, therefore, it is difficult to form upwardly extending threading dislocation defects.

6 is a schematic diagram of a silicon carbide substrate 20 according to a second embodiment of the present invention, which has substantially the same structure as that of the first embodiment. The difference is that the patterned structure 202 of this embodiment is trapezoidal, and the patterned structure 202 has a The top surface 202a, the surface roughness of the top surface 202a is greater than the surface roughness of the side surface 202b, and the distance D' between the top surfaces 202a of two adjacent patterned structures 202 is 2-5 microns, preferably 3 microns. The manufacturing process of the silicon carbide substrate 20 is substantially the same as that of the first embodiment, the difference is that in the step of dry etching the silicon carbide substrate in this embodiment, the degree of lateral etching is less, thus forming the silicon carbide substrate. the top surface. Due to the step of performing dry etching on the silicon carbide substrate, the dielectric part of the dry etching will penetrate the hard mask and damage the top surface 202a of the patterned structure 202, therefore, the top surface 202a of the patterned structure 202 will also form damage. Area.

Please refer to FIG. 7 and FIG. 8 , the process of manufacturing the semiconductor chip 2 of this embodiment is roughly the same as that of the first embodiment. In the initial stage of the growth of the gallium nitride epitaxial layer 22, the gallium nitride 22a is first formed on the patterned structure 202. The side 202b grows (see FIG. 7 ), and then gradually extends laterally to cover the surface 204 and accumulates upwards to form the semiconductor chip 2 of this embodiment (see FIG. 8 ). The gallium nitride epitaxial layer 22 has a plurality of connection surfaces 222, the connection surfaces 222 are respectively connected to the side surfaces 202b whose crystal planes are (-1, 0, 1, 2) planes, each of the connection surfaces 222 The crystal plane of is (-1,1,0,1).

The gallium nitride epitaxial layer 22 has dislocation defects 224 extending laterally at the parts connecting the side faces 202 b, and the gallium nitride epitaxial layer 22 does not have dislocation defects at the parts directly contacting the surface 204 A dislocation defect extending upwards. The laterally extending dislocation defects 224 are less likely to extend upward to form penetrating dislocations, so that the quality of the GaN epitaxial layer 22 above the patterned structure 202 is higher.

Please refer to FIG. 9, which is an image observed by a transmission electron microscope (TEM) at the interface between the gallium nitride epitaxial layer 22 and the silicon carbide substrate 20 of the semiconductor chip 2 of this embodiment, wherein (b) is an enlarged image of (a) . It can be seen from FIG. 9 that laterally extending dislocation defects can be clearly observed in the region of the GaN epitaxial layer 22 adjacent to the side surface 202b of the patterned structure 202, while the GaN epitaxial layer 22 is adjacent to the silicon carbide substrate. The regions of the surface 204 and the top surface 202a of 20 do not have dislocation defects extending upward, so it can be seen that the GaN epitaxial layer 22 is first grown from the side surface 202b of the patterned structure 202 , it is not easy to grow on the surface 204 and the top surface 202a, therefore, it is not easy to form penetrating dislocation defects extending upward.

In the foregoing embodiments, the gallium nitride epitaxial layer is directly disposed on the top of the silicon carbide substrate, and no intermediary layer (such as carbon carbide) other than silicon carbide and gallium nitride is disposed between the silicon carbide substrate and the gallium nitride epitaxial layer aluminum buffer layer).

According to the above, since the crystal plane formed on the side of the patterned structure of the silicon carbide substrate for epitaxy is the (-1,0,1,2) plane, it is beneficial to the growth of the gallium nitride epitaxial layer. Therefore, gallium nitride epitaxy The crystal layer can grow from the side of the patterned structure first, and then accumulate laterally and upwardly. In this way, laterally extending dislocation defects are formed at the bottom of the GaN epitaxial layer, and it is difficult to form penetrating dislocation defects extending upward, so that the GaN epitaxial layer has good epitaxial quality.

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications should also be considered Be the protection scope of the present invention.

Claims (13)

1. A silicon carbide substrate for epitaxy, having a top, and the top is used for setting a gallium nitride epitaxial layer, characterized in that, the top has a surface and a plurality of patterns formed by protruding from the surface structure, wherein the crystal plane of the surface is a (0001) plane; the width of the patterned structure gradually decreases from bottom to top and forms at least one inclined side, and the crystal plane of the side is (-1, 0,1,2) faces. 2 . The silicon carbide substrate for epitaxy according to claim 1 , wherein an angle is formed between each side surface and the surface, and the angle is 110-130 degrees. 3 . 3 . The silicon carbide substrate for epitaxy according to claim 1 , wherein the number of the at least one side is six. 4 . 4 . The silicon carbide substrate for epitaxy according to claim 1 , wherein the maximum width of the bottom of each patterned structure is 1-5 microns. 5. The silicon carbide substrate for epitaxy according to claim 1, wherein the height of each patterned structure is 0.3-2 microns. 6 . The silicon carbide substrate for epitaxy according to claim 1 , wherein the distance between the bottoms of two adjacent patterned structures is 2-3 microns. 7 . The silicon carbide substrate for epitaxy according to claim 1 , wherein the surface roughness of each side is smaller than the surface roughness of the surface. 8. The silicon carbide substrate for epitaxy according to claim 7, wherein each of the patterned structures has a top surface, and the surface roughness of the top surface of each of the patterned structures is greater than the surface roughness of its side surface Spend. 9 . The silicon carbide substrate for epitaxy according to claim 8 , wherein the distance between the top surfaces of two adjacent patterned structures is 2-5 microns. 10. A semiconductor chip, characterized in that it comprises: The silicon carbide substrate for epitaxy according to any one of claims 1 to 9; and A gallium nitride epitaxial layer is arranged on the top of the silicon carbide substrate for epitaxial. 11. The semiconductor chip according to claim 10, wherein the gallium nitride epitaxial layer has a plurality of connection surfaces, the connection surfaces are respectively connected to the side surfaces, and the crystal planes of each of the connection surfaces are (-1,1,0,1) plane. 12 . The semiconductor chip according to claim 10 , wherein the gallium nitride epitaxial layer has dislocation defects extending laterally at the parts connecting the side faces. 13 . 13 . The semiconductor chip according to claim 12 , wherein the gallium nitride epitaxial layer does not have upwardly extending dislocation defects at a portion contacting the surface. 14 .