TWI792462B - Composite substrate for epitaxial growth and method of manufacturing the same - Google Patents

Abstract

A composite substrate for epitaxial growth includes a heavily doped substrate, a dielectric buffer layer and a semiconductor layer. The dielectric buffer layer is disposed on the heavily doped substrate. The semiconductor layer is disposed on the dielectric buffer layer, and a micro pattern is formed on one side of the semiconductor layer, where an epitaxial structure is grown on the side of the semiconductor layer having the micro pattern. In addition, a method of manufacturing the composite substrate is also provided.

Description

Composite substrate for epitaxy growth and manufacturing method thereof

The present disclosure relates to a composite substrate, in particular to a composite substrate for epitaxial growth and a manufacturing method thereof.

Gallium nitride material is regarded as a high-power and high-speed transistor application because of its wide energy gap, high critical electric field, high thermal conductivity, high saturation electron velocity, high-frequency transmission capability, and small component size. As an ideal material, it is widely used in high-frequency components such as high electron mobility transistor (HEMT) or light-emitting diode (LED) components.

Silicon substrates have competitive advantages in terms of price and cost. Therefore, the circuit design scheme of growing III-V semiconductor compounds such as gallium nitride on silicon substrates is being vigorously researched and developed. Due to the large difference in properties such as lattice constant and thermal expansion coefficient between GaN and silicon substrates, a large tensile stress will be generated during the growth of GaN, which will cause the silicon wafer to warp or even crack. As a result, the leakage current of the formed GaN device increases, and the carrier mobility and operating efficiency are reduced.

In view of this, the present disclosure provides a composite substrate for epitaxial growth and a manufacturing method thereof. The composite substrate can resist warping, and it provides epitaxial structure growth of high electron mobility transistors, and an epitaxial structure with high epitaxial quality and low warpage can be obtained, so as to solve the deficiencies in the conventional technology.

According to an embodiment of the present disclosure, a composite substrate for epitaxial growth is provided, including a heavily doped substrate, a dielectric buffer layer, and a semiconductor layer. The dielectric buffer layer is arranged on the heavily doped substrate, the semiconductor layer is arranged on the dielectric buffer layer, and a micropattern is formed on one side of the semiconductor layer, wherein the epitaxial structure is grown on the side of the semiconductor layer with the micropattern superior.

According to an embodiment of the present disclosure, a method for manufacturing a composite substrate for epitaxial growth is provided, including: providing a first substrate and a second substrate; performing a heavily doped process on the first substrate to form a heavily doped base; The heterogeneous substrate, or the second substrate, or both of the above are oxidized to at least form a dielectric buffer layer to wrap the heavily doped substrate or the second substrate; after forming the dielectric buffer layer, attach the second substrate to the heavily doped substrate bonding; bonding the second substrate to the heavily doped substrate, then performing heat treatment; thinning the second substrate to form a semiconductor layer on the dielectric buffer layer; and performing photolithography and etching processes on the surface of the semiconductor layer A micropattern is formed, wherein epitaxial structures are grown on the micropatterned surface of the semiconductor layer.

100: composite substrate

102:Heavily doped substrate

104: Dielectric buffer layer

106: Semiconductor layer

106P: micro pattern

108: Hard mask layer

110: Stress compensation layer

114: Dielectric buffer layer

116: semiconductor layer

200: epitaxial structure

202: nucleation layer

204: buffer layer

206: High resistance layer

208: Channel layer

210: barrier layer

212: cover layer

300: Production method

302: Step

304: step

306: Step

308: Step

310: step

312: Step

In order to make the above and other objects, features and embodiments of the present disclosure more comprehensible, the attached drawings are described as follows. In addition, for the sake of clarity, each feature in the drawings may not necessarily be drawn according to the actual scale, so The dimensions of some features in some drawings may be intentionally enlarged or reduced.

FIG. 1 is a schematic cross-sectional view of a composite substrate according to an embodiment of the present disclosure.

FIG. 2 is a schematic cross-sectional view of an epitaxial structure grown on a composite substrate according to an embodiment of the present disclosure.

FIG. 3 , FIG. 4 , FIG. 5 and FIG. 6 are schematic cross-sectional views of composite substrates according to some embodiments of the present disclosure, wherein there are different types of micropatterns on the surface of the semiconductor layer.

FIG. 7 is a schematic cross-sectional view of a composite substrate according to another embodiment of the disclosure, wherein a dielectric buffer layer wraps a semiconductor layer.

FIG. 8 is a schematic cross-sectional view of a composite substrate according to another embodiment of the present disclosure, wherein a dielectric buffer layer wraps the semiconductor layer, and a stress compensation layer is disposed on the back of the heavily doped substrate.

FIG. 9 is a schematic cross-sectional view of a composite substrate according to another embodiment of the disclosure, which includes two stacked semiconductor layers.

FIG. 10 is a flowchart of a method for manufacturing a composite substrate according to an embodiment of the present disclosure.

In order to make the description of the present disclosure more detailed and complete, the following provides illustrative descriptions of the implementations and specific embodiments of the present disclosure; but this is not the only way to implement or use the specific embodiments of the present invention. The description covers features of various embodiments as well as method steps and their sequences for constructing and operating those embodiments. However, other embodiments can also be used to achieve the same or equivalent functions and step sequences.

The numerical ranges and parameters described below are approximate numerical values. Here, "about" usually means that the actual numerical value is within plus or minus 10%, 5%, 1% or 0.5% of a specific numerical value or range. It should be understood that all ranges, amounts, values, ratios and percentages used herein are modified by "about". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the appended patent claims are approximate values and may be changed as required.

FIG. 1 is a schematic cross-sectional view of a composite substrate 100 according to an embodiment of the present disclosure. The composite substrate 100 includes a heavily doped substrate 102 , such as an n-type or p-type heavily doped substrate, but not limited thereto. The heavily doped substrate 102 can be a silicon-based substrate such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon, or other materials with high thermal conductivity, and the dopant atoms therein can be boron (B), phosphorus (P), or arsenic (As). , tungsten (Tb) or a combination thereof, and the doping concentration is higher than 10 ¹⁸ atoms/cubic centimeter (atom/cm ³ ), more preferably higher than 10 ¹⁹ atom/cm ³ . In addition, the composite substrate 100 further includes a dielectric buffer layer 104 disposed on the heavily doped substrate 102 , and a semiconductor layer 106 disposed on the dielectric buffer layer 104 . The dielectric buffer layer 104 may be an oxide layer with a high dielectric constant. In one embodiment, the dielectric buffer layer 104 is, for example, silicon oxide, and may be formed by a thermal oxidation process or a deposition method. In another embodiment, the dielectric buffer layer 104 may be a dielectric layer made of other materials, such as silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a high dielectric material with a dielectric constant higher than 4. dielectric constant, and can be formed by deposition. According to an embodiment of the present disclosure, the dielectric buffer layer 104 may wrap the front, back and sides of the heavily doped substrate 102 . According to another embodiment of the present disclosure, the dielectric buffer layer 104 may wrap the bottom surface and the side surface of the semiconductor layer 106 . According to yet another embodiment of the present disclosure, the dielectric buffer layer 104 and another dielectric buffer layer may respectively wrap the heavily doped substrate 102 and the semiconductor layer 106 .

According to an embodiment, the semiconductor layer 106 may be single crystal silicon or sapphire, and the semiconductor layer 106 includes micropatterns, such as micropatterns 106P on one side or surface of the semiconductor layer 106 . The micropattern 106P can be made of a plurality of linear three-dimensional patterns, or an array of a plurality of three-dimensional patterns, the cross-sectional shape of these individual three-dimensional patterns can be trapezoidal, inverted trapezoidal, triangle or square, and the plane of these individual three-dimensional patterns The shape may be circular, triangular or polygonal, for example, these individual three-dimensional patterns may be circular pillars, circular cones, triangular pillars, polygonal pillars, triangular cones, polygonal cones, and the like. In addition, these individual three-dimensional patterns can be connected to each other by using the bottom of the semiconductor layer 106 , or can be separated from each other to expose the underlying dielectric buffer layer 104 . According to an embodiment of the present disclosure, the pitch of these three-dimensional patterns of the micropattern 106P may be 0.5 micrometers (μm) to 10 μm; the planar dimensions (such as width/length/diameter, etc.) of individual three-dimensional patterns may be 0.5 μm to 5 μm; three-dimensional The height of the pattern may be 0.2 μm to 5 μm. The thickness of the heavily doped substrate 102 is much greater than the thickness of the semiconductor layer 106. According to an embodiment of the present disclosure, the thickness of the heavily doped substrate 102 is less than 1000 μm, the thickness of the semiconductor layer 106 is 0.5 μm to 3 μm, and the thickness of the dielectric buffer layer 104 The thickness is 0.5 μm to 2 μm.

FIG. 2 is a schematic cross-sectional view of an epitaxial structure 200 grown on a composite substrate 100 according to an embodiment of the present disclosure. The epitaxial structure 200 is grown on the semiconductor layer 106 of the composite substrate 100 with micro-patterns. On the surface of case 106P, in one embodiment, the epitaxial structure 200 may be a HEMT III-V compound semiconductor element epitaxial structure (such as a gallium nitride element epitaxial structure), and the epitaxial structure 200 may include nucleation Layer 202, buffer layer 204, high resistance layer 206, channel layer 208, barrier layer 210 and cover layer 212 are sequentially stacked on the composite substrate 100 from bottom to top, wherein the nucleation layer 202 is, for example, aluminum nitride ( AlN) layer; the buffer layer 204 is, for example, a graded aluminum gallium nitride (AlGaN) layer, or a superlattice layer (superlattice) formed by alternating stacking of aluminum gallium nitride (AlGaN) layers and gallium nitride (GaN) structure); the high-resistance layer 206 is, for example, aluminum gallium nitride (AlGaN) or gallium nitride (GaN) layer doped with carbon or iron, and its resistivity is higher than that of the buffer layer 204; the channel layer 208 is, for example, An undoped or n-type gallium nitride (GaN) layer; the barrier layer 210 is, for example, an aluminum gallium nitride (AlGaN) layer, or an aluminum nitride (AlN) layer; the capping layer 212 is, for example, a p-type aluminum nitride gallium (AlGaN) layer, or gallium nitride (GaN) layer, but the present disclosure is not limited to the above materials.

According to the embodiment of the present disclosure, because high-temperature heat treatment is included in the manufacturing process of the composite substrate 100, and after high-temperature heat treatment, oxides will be precipitated in the heavily doped substrate 102, and when the doping concentration is high, The density of oxide precipitation is also higher, which increases the mechanical strength of the heavily doped substrate 102, and then when the epitaxial structure 200 is grown on the composite substrate 100, it can resist or slow down the warping deformation caused by the stress during epitaxial growth. , and reduce the thermal shock caused by the temperature rise and fall during the epitaxy process, so that the surface curvature of the epitaxy structure 200 changes little. For example, when the heavily doped substrate 102 is a silicon-based substrate, the precipitated oxides may include doped oxides, such as boron (B), phosphorus (P), arsenic (As), Oxides of tungsten (Tb) or combinations thereof. In addition, increasing the thickness of the heavily doped substrate 102 helps to improve the warpage resistance of the composite substrate 100, and the thinner semiconductor layer 106 will generate self-alignment during high-temperature epitaxy to reduce stress. For the epitaxial growth of the epitaxial structure 200 , the substrate 100 can achieve high epitaxial quality and anti-warping effect. For example, the overall warpage of the epitaxial structure 200 and the composite substrate 100 can be less than 50 μm.

In addition, the composition and thickness of the dielectric buffer layer 104 can also be adjusted to enhance the overall bending resistance or Young's modulus of the composite substrate 100, thus improving the warpage of the composite substrate 100. degree of curvature.

In addition, when the epitaxial structure 200 is epitaxially grown on the composite substrate 100 , the bonding interface between the heavily doped substrate 102 and the semiconductor layer 106 can release the stress caused by the epitaxial growth, further preventing warping and cracks. Moreover, according to an embodiment of the present disclosure, the micropattern 106P on the surface of the semiconductor layer 106 can allow the epitaxial structure 200 to grow in the manner of epitaxial lateral overgrowth (ELOG). The resulting defects are bent during the process to avoid increased defect diffusion. At the same time, the micropattern 106P can also increase the epitaxial growth interface (boundary), absorb the stress generated by lattice mismatch, and cooperate with the anti-warping characteristics of the composite substrate 100 disclosed in the present disclosure to obtain low defect density and high epitaxial quality. , low warpage, and low stress GaN epitaxial structure, and then when it is applied to HEMT in the future, it will improve the electrical characteristics and efficiency of HEMT, such as the breakdown voltage, heat conduction and yield improvement.

FIG. 3 is a schematic cross-sectional view of a composite substrate according to an embodiment of the present disclosure. The difference between FIG. 3 and FIG. 1 is that the micropattern 106P of the composite substrate 100 in FIG. 3 is composed of multiple pyramidal three-dimensional patterns. The cross-sectional shape of these pyramidal three-dimensional patterns is triangular, and the positions between the bottoms of these pyramidal three-dimensional patterns can be used as nucleation points during epitaxy. In one embodiment, these pyramidal three-dimensional patterns can be connected to each other by using the bottom of the semiconductor layer 106 ; in another embodiment, these pyramidal three-dimensional patterns can also be separated from each other to expose the underlying dielectric buffer layer 104 . In addition, according to an embodiment of the present disclosure, the three-dimensional patterns whose cross-sectional shapes are triangular may also be striped patterns parallel to each other. For other plane shapes, dimensions, pitches, etc. of the three-dimensional patterns, reference can be made to the description of the first FIG. 1 above.

FIG. 4 is a schematic cross-sectional view of a composite substrate according to another embodiment of the present disclosure. The difference between FIG. 4 and FIG. 3 lies in the cross-sections of the columnar three-dimensional patterns of the micropattern 106P of the composite substrate 100 in FIG. 4 The shape is trapezoidal, and the top surfaces of these columnar three-dimensional patterns can be used as nucleation points during epitaxy. In an embodiment, the columnar three-dimensional patterns can be connected to each other by using the bottom of the semiconductor layer 106 . For other plane shapes, dimensions, pitches, etc. of the three-dimensional patterns, reference can be made to the description of the first FIG. 1 above.

FIG. 5 is a schematic cross-sectional view of a composite substrate according to another embodiment of the disclosure, and FIG. The difference between Figure 5 and Figure 4 is that the cross-sectional shape of these columnar three-dimensional patterns of the micropattern 106P of the composite substrate 100 in Figure 5 is an inverted trapezoid, and a hard mask layer is also provided on the top surface of these columnar three-dimensional patterns 108. The hard mask layer 108 can be made of silicon nitride, silicon oxide, or a combination of the foregoing, or other high-temperature-resistant materials. The material layer of the hard mask layer 108 can be formed through an oxidation reaction, a nitriding reaction, or a deposition method. Photolithography and etching process to form the pattern of the hard mask layer 108 . The hard mask layer 108 can serve as a patterned mask when the micropattern 106P is etched, and can protect the top surface of the micropattern 106P. The positions between the top surfaces of the columnar three-dimensional patterns and the bottoms of the columnar three-dimensional patterns can be used as nucleation points during epitaxy. In one embodiment, these columnar three-dimensional patterns can be connected to each other by using the bottom of the semiconductor layer 106 . For other plane shapes, dimensions, pitches, etc. of the three-dimensional patterns, reference can be made to the description of the first FIG. 1 above.

FIG. 6 is a schematic cross-sectional view of a composite substrate according to another embodiment of the present disclosure. The difference between FIG. 6 and FIG. 5 lies in the cross-sections of the columnar three-dimensional patterns of the micropattern 106P of the composite substrate 100 in FIG. 6 The shape is trapezoidal, and the sides of these trapezoidal columnar three-dimensional patterns can be used as nucleation points during epitaxy. In one embodiment, these columnar three-dimensional patterns are separated from each other to expose the underlying dielectric buffer layer 104 . For other details about the planar shape, size, and spacing of the three-dimensional patterns, please refer to the description in FIG. 1 above.

FIG. 7 is a schematic cross-sectional view of a composite substrate according to another embodiment of the present disclosure. The difference between FIG. 7 and FIG. 1 is that the dielectric buffer layer 104 of the composite substrate 100 in FIG. 7 is wrapped around the semiconductor layer 106. Bottom and sides.

FIG. 8 is a schematic cross-sectional view of a composite substrate according to another embodiment of the present disclosure. The difference between FIG. 8 and FIG. compensation layer 110 . The stress compensation layer 110 can be a dielectric layer, such as silicon oxide, silicon nitride or a combination of the foregoing, with a thickness of 0.1 μm to 10 μm, and can be formed by thermal oxidation or deposition. According to an embodiment of the present disclosure, the overall warpage of the composite substrate 100 during epitaxy can be compensated by the thickness of the stress compensation layer 110 , and the mechanical strength of the composite substrate 100 can also be adjusted by the thickness of the stress compensation layer 110 , For example Young's coefficient.

FIG. 9 is a schematic cross-sectional view of a composite substrate according to another embodiment of the present disclosure. The difference between FIG. 9 and FIG. 1 is that the composite substrate 100 in FIG. 9 further includes another semiconductor layer 116 and another dielectric. The buffer layer 114 is disposed between the semiconductor layer 106 and the dielectric buffer layer 104, so that the composite substrate 100 of FIG. 9 has a two-layer semiconductor layer stack. In other embodiments, a stack of three or more semiconductor layers may be disposed between the semiconductor layer 106 and the dielectric buffer layer 104 , and further dielectric buffer layers may be disposed between these stacked semiconductor layers. According to an embodiment of the present disclosure, the uppermost semiconductor layer 106 is Si(111), and other semiconductor layers may be a stacked combination of Si(111), Si(100), and Si(110). The interface between these stacked semiconductor layers and the dielectric buffer layer is not fully bonded, so it can be partially moved to the position with the least stress during high-temperature epitaxy to release the stress caused by epitaxy growth and effectively prevent warpage and cracks generation.

FIG. 10 is a flowchart of a manufacturing method 300 of the composite substrate 100 according to an embodiment of the present disclosure. Firstly, step 302 is performed to provide a first substrate and a second substrate. According to an embodiment of the present disclosure, the first substrate may be a handle wafer, and its material may be a silicon-based substrate such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The second substrate may be a device wafer, and its material may be single crystal silicon, silicon carbide, gallium arsenide, sapphire, indium phosphide or gallium nitride. Next, step 304 is performed to perform a heavily doped process on the first substrate to form a heavily doped substrate, such as the heavily doped substrate 102 shown in FIGS. 1 to 9 . According to an embodiment of the present disclosure, the dopant atoms used in the heavy doping process may be boron (B), phosphorus (P), arsenic (As), uranium (Tb) or a combination thereof, and the doping concentration is higher than 10 ¹⁸ atom/cm ³ , more preferably higher than 10 ¹⁹ atom/cm ³ .

Then, step 306 is performed to oxidize the heavily doped base or the second substrate, or both, to form at least one dielectric buffer layer surrounding the heavily doped base or the second substrate, or to form two dielectric buffer layers. The layers wrap the aforementioned two separately. For example, in one embodiment, the dielectric buffer layer 104 wraps around the heavily doped substrate 102 as shown in FIG. 1 . In another embodiment, a dielectric buffer layer may wrap the second substrate. In yet another embodiment, both the heavily doped base and the second substrate may each be wrapped by a dielectric buffer layer. In one embodiment, the thermal oxidation process may be performed at 950° C. to 1250° C., such as 1050° C., in an oxygen-containing environment to form the dielectric buffer layer. The time of the thermal oxidation process is 1 to 6 hours, and the thickness of the dielectric buffer layer is, for example, 0.5 μm to 2μm silicon oxide layer.

After that, attach the second substrate to the heavily doped base. The second substrate and the heavily doped substrate can be aligned and bonded under normal pressure or in a vacuum environment. At this time, the dielectric buffer layer formed on the second substrate, or the heavily doped substrate, or both of them is beneficial to the two substrates. tight fit.

Afterwards, step 308 is performed, and heat treatment is performed after bonding the second substrate and the heavily doped base. According to an embodiment of the present disclosure, the heat treatment after bonding the second substrate and the heavily doped base can be performed at a temperature of 950° C. to 1250° C. or 1050° C. to 1250° C. in an oxygen-containing environment, and the heat treatment time is less than 2 hours. This heat treatment can help the bonding (bonding) of the second substrate and the heavily doped substrate, and make the oxygen precipitation behavior of the heavily doped substrate occur. This precipitation behavior is the oxide precipitation of doping atoms. As the heat treatment time increases, The higher the doping concentration, the higher the density of the precipitated oxide, and the larger the size of the precipitated oxide, which will help to improve the mechanical strength of the heavily doped substrate. In one embodiment, compared with the undoped For the first substrate, the Young's modulus of the heavily doped substrate can be increased by about 10 to 15%.

Then, step 310 is performed to thin the second substrate to form a semiconductor layer on the dielectric buffer layer, such as the semiconductor layer 106 shown in FIGS. 1 to 9 . According to an embodiment of the present disclosure, the thickness of the second substrate can be reduced to 0.5 μm to 3 μm by grinding, polishing and other processes.

Next, perform step 312, perform photolithography and etching processes, and form micropatterns on the surface of the semiconductor layer to obtain a composite substrate, wherein the epitaxial structure is grown on the surface of the semiconductor layer with micropatterns, such as the first to ninth A micropattern 106P of the semiconductor layer 106 is shown. A photoresist layer can be coated on the semiconductor layer 106 , and a patterned photoresist can be obtained by exposing and developing (also known as photolithography) process, or a patterned photoresist can be obtained by laser engraving or other methods. Using the patterned photoresist as a mask, an etching process is performed on the semiconductor layer 106 to form a micro pattern 106P on the surface of the semiconductor layer 106 . Various types of micropatterns 106P can be obtained according to the pattern of the photoresist, the material of the semiconductor layer 106 , and the etchant and etching parameters used in the etching process. The pattern of the photoresist can correspond to the micropattern 106P to be formed, and the semiconductor layer 106 with different crystal planes can be selected, and different types of micropattern 106P can be obtained after etching. The etching process can be a dry etching or a wet etching process. The dry etching is a plasma etching process, which can use a combination of etching gases containing F, Cl, Br, or other etchant vapors, such as KOH, NaOH, HCl, HNO ₃ etc., and by controlling the etching parameters, for example, the etching time is 0.5 minutes to 3 hours, and the etching temperature is 60° C. to 150° C., to obtain different types of micropatterns 106P. In addition, according to an embodiment of the present disclosure, a hard mask layer can also be formed on the semiconductor layer 106, and the hard mask layer can be patterned through photolithography and etching processes, and the patterned hard mask layer can be used as an etching mask. , the semiconductor layer 106 is etched to form a micropattern 106P, and the patterned hard mask layer 108 is left on the top surface of the micropattern 106P, as shown in FIGS. 5 and 6 .

According to an embodiment of the present disclosure, the epitaxial structure 200 is grown on the surface of the semiconductor layer 106 of the composite substrate 100 having the micropattern 106P. The micropattern 106P on the surface of the semiconductor layer 106 can allow the epitaxial structure 200 to grow in a lateral epitaxy growth (ELOG) manner, and bend the generated defects during the epitaxy process to avoid increased defect diffusion. At the same time, the micropattern 106P also The interface (boundary) for epitaxial growth can be increased to absorb the stress generated by lattice mismatch. In addition, the heavily doped substrate 102 of the composite substrate 100 will have oxides precipitated after high temperature heat treatment, which increases the mechanical strength of the heavily doped substrate 102, and then when the epitaxial structure 200 grows on the composite substrate 100, it can resist or The warping deformation caused by the stress during the epitaxy growth is slowed down, and the thermal shock caused by the temperature rise and fall during the epitaxy process is reduced, so that the surface curvature of the epitaxy structure 200 changes little. Therefore, the composite substrate 100 of the present disclosure can achieve high epitaxial quality and anti-warping effects for the epitaxial growth of the epitaxial structure 200 , and further, when applied to HEMTs, can improve the electrical properties and efficiency of HEMTs.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: composite substrate

102:Heavily doped substrate

104: Dielectric buffer layer

106: Semiconductor layer

106P: micro pattern

200: epitaxial structure

202: nucleation layer

204: buffer layer

206: High resistance layer

208: Channel layer

210: barrier layer

212: cover layer

Claims (7)

A composite substrate for epitaxial growth, comprising: a heavily doped substrate; a first dielectric buffer layer disposed on the heavily doped substrate; a second semiconductor layer disposed on the first dielectric buffer layer; a second dielectric buffer layer, disposed on the second semiconductor layer; and a first semiconductor layer, disposed on the second dielectric buffer layer, forming a micropattern, and growing an epitaxial structure on the micropattern superior. The composite substrate for epitaxial growth as described in Claim 1, wherein the doping atoms of the heavily doped substrate include boron (B), phosphorus (P), arsenic (As) or uranium (Tb), and the doping concentration Higher than 10 ¹⁸ atoms/cubic centimeter (atom/cm ³ ). The composite substrate for epitaxial growth according to claim 1, wherein the heavily doped substrate includes single crystal silicon, polycrystalline silicon or amorphous silicon, and the first semiconductor layer includes single crystal silicon or sapphire. The composite substrate for epitaxial growth as described in claim 1, wherein the first dielectric buffer layer includes silicon oxide, and wraps the front, back, and side surfaces of the heavily doped substrate, or wraps the bottom surface of the first semiconductor layer and sides, or wrap the heavily doped substrate and the first semiconductor layer. The composite substrate for epitaxial growth as claimed in claim 1 further includes a stress compensation layer disposed on the back side of the heavily doped substrate, wherein the stress compensation layer includes silicon oxide. The composite substrate for epitaxial growth as described in Claim 1, wherein the first semiconductor layer The micropattern includes a plurality of linear three-dimensional patterns, or an array of multiple three-dimensional patterns, and the cross-sectional shape of these three-dimensional patterns includes trapezoid, inverted trapezoid, triangle or square, and the planar shape of these three-dimensional patterns includes circle, triangle or polygon. The composite substrate for epitaxial growth as claimed in claim 1, wherein the epitaxial structure includes an epitaxial structure of a III-V group semiconductor element of a high electron mobility transistor.

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