CN107908221A - A kind of low-power consumption LDO systems - Google Patents
A kind of low-power consumption LDO systems Download PDFInfo
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- CN107908221A CN107908221A CN201711009140.5A CN201711009140A CN107908221A CN 107908221 A CN107908221 A CN 107908221A CN 201711009140 A CN201711009140 A CN 201711009140A CN 107908221 A CN107908221 A CN 107908221A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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Abstract
The invention discloses a kind of low-power consumption LDO systems, including：One micro-current generation circuit, its core are that metal-oxide-semiconductor is operated in sub-threshold region, produce the reference current of as low as na level；One reference generating circuit, using cascade cascaded structure, reference voltage is provided for the system；One regulator circuit, using series voltage stabilizing structure, metal-oxide-semiconductor is connected in power supply loop, and stabilized supply voltage is controlled by controlling the grid voltage of metal-oxide-semiconductor.A kind of low-power consumption LDO systems of the present invention, whole system are operated under Naan level currents, and power consumption is very small, and stability is high.
Description
Technical field
The present invention relates to LDO circuit field, more particularly to a kind of low-power consumption LDO systems.
Background technology
In the application of Internet of Things and most of wireless telecommunications, associated receiver circuitry or radiating circuit etc. are all that needs are low
Power consumption, therefore the LDO of low-power consumption（Low dropout regulator, low-dropout linear voltage-regulating circuit）Circuit is to entirely should
It is very crucial and very necessary for.Pith of the LDO circuit as analog circuit, generally requires wider at one
Voltage range in normal work, therefore do not require nothing more than low in energy consumption, it is also necessary to which performance is stablized, and has preferable temperature characterisitic.Tradition
The circuit of mode, its power consumption are all that microwatt level is other, are not belonging to low power dissipation design category.
The content of the invention
To overcome the above-mentioned problems of the prior art, it is a primary object of the present invention to provide a kind of low-power consumption LDO systems
System, whole system are operated under Naan level currents, and power consumption is very small, and stability is high.
In view of the above and other objects, the present invention provides a kind of low-power consumption LDO systems, it is included at least：
One micro-current generation circuit, its core are that metal-oxide-semiconductor is operated in sub-threshold region, produce the reference current of as low as na level, this
And the source of nA electric currents is provided to whole circuit；One reference generating circuit, is the system using cascade cascaded structure
Reference voltage is provided, it is simple to be mainly characterized by reference circuit structure, and performance is more stablized, and avoids production band-gap reference so multiple
Miscellaneous power consumption and big circuit；One regulator circuit, using series voltage stabilizing structure, metal-oxide-semiconductor is connected in power supply loop, passes through control
The grid voltage of metal-oxide-semiconductor controls stabilized supply voltage, and the wherein operating current of amplifier is 150nA, belongs to the work of sub-threshold region
Make category, purpose is also to reduce power consumption.
The present invention proposes a kind of low-power consumption LDO systems, including：
The micro-current generation circuit is by the first PMOS tube PM1, the second PMOS tube PM2, the 3rd PMOS tube PM3, the 4th PMOS tube
PM4, the first PNP triode Q1, the 8th NMOS tube NM8 and the 9th NMOS tube NM9 are formed, the source electrode of PM1 pipes and the source electrode of PM2 pipes
It is connected and is connected to LVDD；The grid of PM2 pipes and the grid of PM1 pipes, the grid of PM3 pipes, the drain electrode of PM3 pipes, the grid of PM4 pipes
The drain electrode of pole, NM8 pipes is connected, its node label is VP；The drain electrode of PM2 pipes is connected with the source electrode of PM4 pipes；The leakage of PM1 pipes
The source electrode of pole PM3 pipes is connected；The drain electrode of PM4 pipes is connected with the emitter of Q1 pipes, the grid of NM8 pipes；The source electrode of NM8 pipes with
The drain electrode of the grid, NM9 pipes of NM9 pipes is connected；The base stage of Q1 pipes, the collector of Q1 pipes, the source electrode ground connection of NM9 pipes.
The reference generating circuit is by the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 7th PMOS tube PM7, the 8th PMOS
Pipe PM8, the 9th PMOS tube PM9, the tenth PMOS tube PM10, the 11st PMOS tube PM11, the 12nd PMOS tube PM12, the first NMOS
Pipe NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6,
7th NMOS tube NM7, first resistor R1 are formed；The source electrode of PM5 pipes and the source electrode of PM6 pipes, the source electrode of PM7 pipes, the source electrode of PM8 pipes
It is connected with the source electrode of PM1 pipes and is connected to LVDD；The grid of PM5 pipes, the grid of PM6 pipes, the grid of PM7 pipes, the grid of PM8
Pole, the grid of PM9 pipes, the grid of PM10 pipes, the grid of PM11 pipes, the grid of grid and PM2 pipes of PM12 pipes link together；
The drain electrode of PM8 pipes is connected with the source electrode of PM12 pipes；The drains of PM12 pipes and the drain of NM6 pipes, the grid of NM6 pipes, NM7 pipes
Grid is connected；The source electrode of NM6 pipes is connected with the drain of NM7 pipes, the source electrode of NM5 pipes；The source electrode ground connection of NM7 pipes；PM7 pipes
Drain electrode is connected with the source electrode of PM11 pipes；The drain of PM11 pipes and the drain of NM4 pipes, the grid of NM4 pipes, the grid phase of NM5 pipes
Connection；The source electrode of NM4 pipes is connected with the drain of NM5 pipes, the source electrode of NM3 pipes；The drain electrode of PM6 pipes is connected with the source electrode of PM10 pipes
Connect；The drain of PM10 pipes is connected with the grid of the grid of NM2 pipes, the drain of NM2 pipes, NM3 pipes；The source electrode of NM2 pipes is managed with NM3
Drain, the source electrode of NM1 pipes is connected；The drain electrode of PM5 pipes is connected with the source electrode of PM9 pipes；The drain of PM9 pipes is with resistance R1's
One end is connected, its node label is VREF；The other end of resistance R1 is connected with the grid of NM1 pipes, the drain of NM1 pipes.
The regulator circuit is by the first capacitance C1, the second capacitance C2, second resistance R2, the 13rd PMOS tube PM13, the tenth
Four PMOS tube PM14, the 15th PMOS tube PM15, the 16th PMOS tube PM16, the 17th PMOS tube PM17, the 18th PMOS tube
PM18, the 19th PMOS tube PM19, the 20th PMOS tube PM20, the 21st PMOS tube PM21, the 22nd PMOS tube PM22,
23rd PMOS tube PM23, the 24th PMOS tube PM24, the tenth NMOS tube NM10, the 11st NMOS tube NM11, the 12nd
NMOS tube NM12, the 13rd NMOS tube NM13, the 14th NMOS tube NM14, the 15th NMOS tube NM15, the 16th NMOS tube
NM16 and the 17th NMOS tube NM17 is formed；One end of capacitance C1, the source electrode of PM24 pipes, the source electrode of PM23 pipes, the source of PM22 pipes
The drain electrode of pole, the source electrode of PM21 pipes, NM16 pipes is all connected with high voltage power supply HVDD；The other end of capacitance C1 and the grid of NM16 pipes
The drain electrode of pole and NM17 pipes is connected, node label ST；The grid of PM24 pipes and the drain electrode of PM24 pipes, PM23 pipes grid,
The drain electrode of NM14 pipes is connected with the grid of NM14 pipes；The source electrode of NM14 pipes is connected with the drain electrode of NM12 pipes；The leakage of PM23 pipes
Pole is connected with the grid of the drain electrode of PM22 pipes, the grid of PM22 pipes, the grid of PM21 pipes, the drain electrode of NM15 pipes and NM15 pipes；
The source electrode of NM15 pipes is connected with the drain electrode of NM13 pipes；Drain electrode and the source electrode of NM16 pipes, the source electrode of PM17 pipes, the PM13 of PM21 pipes
The source electrode of pipe, one end of capacitance C2 are connected with the source electrode of PM2 pipes, output terminal of its node as low pressure LVDD；PM13 pipes
Grid is connected with the drain electrode of PM13 pipes and the source electrode of PM14 pipes；The grid of PM14 pipes and the drain electrode of PM14 pipes and the one of resistance R2
End is connected；The other end of resistance R2 is connected with the source electrode of PM15 pipes；The grid of PM15 pipes and the drain electrode of PM15 pipes and PM16
The source electrode of pipe is connected, its node label is VFB；The grid of PM17 pipes and the grid of PM18 pipes are all connected with node VP；
The drain electrode of PM17 pipes is connected with PM18 pipe source electrodes；The drain electrode of PM18 pipes is connected with the source electrode of PM19 pipes and the source electrode of PM20 pipes
Connect；The grid connecting node VFB of PM19 pipes；The grid of PM20 pipes and the grid of NM17 pipes all connecting node VREF；PM19 pipes
Drain electrode is connected with the grid of the drain electrode of NM10 pipes, the grid of NM10 pipes and NM13 pipes, its node label is NET2；PM20 pipes
Drain electrode is connected with the grid of the drain electrode of NM11 pipes, the grid of NM11 pipes and NM12 pipes, its node label is NET1；NM17 pipes
Source electrode, the source electrode of NM12 pipes, the source electrode of NM13 pipes, the source electrode of NM10 pipes, the source electrode of NM11 pipes, the grid of PM16 pipes, PM16 pipes
Drain electrode and the other end of capacitance C2 be all grounded.
Brief description of the drawings
The attached drawing for forming the part of the application is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its explanation is used to explain the present invention, do not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is a kind of low-power consumption LDO system circuit diagrams of the present invention.
Embodiment
With reference to shown in Fig. 1, in the following embodiments, a kind of low-power consumption LDO systems, it is included at least：One micro- electricity
Generation circuit is flowed, its core is that metal-oxide-semiconductor is operated in sub-threshold region, produces the reference current of as low as na level, this is also to whole
Circuit provides the source of nA electric currents；One reference generating circuit, using cascade cascaded structure, provides with reference to electricity for the system
Pressure, it is simple to be mainly characterized by reference circuit structure, and performance is more stablized, and avoids the so complicated power consumption of production band-gap reference again big
Circuit；One regulator circuit, using series voltage stabilizing structure, metal-oxide-semiconductor is connected in power supply loop, by the grid for controlling metal-oxide-semiconductor
Pole tension controls stabilized supply voltage, and the wherein operating current of amplifier is 150nA, belongs to the programme area of sub-threshold region, mesh
Be also reduce power consumption.
Capacitance C1, NM17 pipe, NM16 pipes form system start-up circuit；When high voltage power supply HVDD is powered on, the two of capacitance C1
Terminal voltage will not suddenly change, therefore node ST can be coupled to high potential, the conducting of NM16 pipes, and certain electricity is begun with LVDD
Pressure, micro-current generation circuit started to work and started to provide electric current this when, and when the work of whole circuit stability and benchmark produces
When circuit VREF exports a normal value, the grid of NM17 pipes becomes high voltage, and the conducting of NM17 pipes, low electricity is pulled into by node ST
Position, cut-off NM16 pipes, so as to close start-up circuit, whole start-up circuit also just completes startup work.
PM1 pipes, PM2 pipes, PM3 pipes, PM4 pipes, triode Q1, NM8 pipe, NM9 pipes form micro-current generation circuit, Q1 pipe phases
When in a positive diode, the voltage of emitter to base stage, equivalent to the sum of gate source voltage of NM8 pipes and NM9 pipes, then
NM8 pipes are just forced to enter sub-threshold region, therefore the low current that the electric current Ib produced is nA ranks.Amplifier in regulator circuit, its
Operating current is also from herein, and in amplifier, the electric current of 75nA is replicated using current-mirror structure, there is provided to amplifier as tail electricity
Stream, therefore the operating current about 150nA of whole amplifier.
PM5 is managed, PM6 pipes, PM7 pipes, PM8 pipes, PM9 pipes, PM10 are managed, PM11 pipes, PM12 pipes, NM1 pipes, NM2 pipes, NM3 are managed,
NM4 pipes, NM5 pipes, NM6 pipes, NM7 pipes, resistance R1 form reference generating circuit；NM1 pipes, NM2 pipes, NM3 pipes, NM4 are managed, NM5 is managed,
NM6 pipes, NM7 pipes are cascaded in a manner of automatic biasing, and NM6 pipes and NM7 pipes, NM4 pipes and NM5 pipes, NM2 pipes and NM3 pipes are all located
In identical p-well, all it is biased in subthreshold region, and they all produce positive temperature coefficient voltage；Mirror current source
PMOS tube uses cascode structure, increases the stability of image current in biasing circuit, increases interference free performance.PM1 pipes,
PM2 pipes, PM3 pipes, PM4 pipes, PM5 are managed, PM6 is managed, PM7 pipes, PM8 pipes, PM9 pipes, PM10 are managed, PM11 is managed and the size of PM12 pipes
It is just as.
Output terminal of the drain of PM9 pipes as reference voltage V REF, current flowing resistance R1 and NM1 pipe, in weak inversion regime
The diode connected transistor NM1 of work is used as negative temperature coefficient voltage, and finally going out to produce Positive and Negative Coefficient Temperature in VREF offsets
A magnitude of voltage.Resistance R1 auxiliary output voltage values reach the balance of temperature coefficient, that is, this road can be reduced by increasing resistance
Required electric current, can further save power consumption.
PM13 pipes, PM14 pipes, PM15 pipes, PM16 pipes and resistance R2 form bleeder circuit, and four PMOS tube all make diode
Connection, HVDD is segmented, by the size of regulation resistance R2, and then the voltage accounting of adjustment node VFB, finally control LVDD.
The effect of resistance R2 is that voltage that can be as needed carries out more flexible micro-adjustment.
Capacitance C1, capacitance C2, PM17 pipe, PM18 pipes, PM19 pipes, PM20 pipes, PM21 pipes, PM22 pipes, PM23 pipes, PM24
Pipe, NM10 pipes, NM11 pipes, NM12 pipes, NM13 pipes, NM14 pipes, NM15 pipes, NM16 pipes and NM17 pipes form regulator circuit core
Point；PM19 is managed and PM20 pipes composition comparator, the both ends of the control source comparator of node VFB and node VREF, when on HVDD
Load current become hour, VFB voltages are higher than VREF voltages, and the electric current for flowing through NM13 pipes just diminishes, and flows through the electric current of NM12 pipes
Just become larger, since mirror image acts on, the electric current of PM23 pipes also becomes larger, and then forces the electric current of PM22 pipes to diminish, PM22 pipes and PM21
The current-mirror structure of pipe causes the electric current of PM21 pipes also to diminish, and the electric current of last PM21 pipes and the load current of HVDD reach flat
Weighing apparatus.Wherein, the electric current that PM17 pipes and PM18 pipes are mirrored to from micro-current generation circuit is less than 100 Naans；Capacitance C2 is as storage
Can capacitance use.
The present invention proposes a kind of low-power consumption LDO systems, and compared with other circuits, whole system is operated in Naan rank electricity
Flow down, power consumption is very small, and stability is high.
Although the present invention is illustrated using specific embodiment, the present invention's is not intended to limit to the explanation of embodiment
Scope.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention
In the case of, easily carry out various modifications or embodiment can be combined, these also should be regarded as protection scope of the present invention.
Claims (4)
1. a kind of low-power consumption LDO systems, including：
One micro-current generation circuit, its core are that metal-oxide-semiconductor is operated in sub-threshold region, produce the reference current of as low as na level；One
Reference generating circuit, using cascade cascaded structure, reference voltage is provided for the system；One regulator circuit, uses series connection
Structure of voltage regulation, metal-oxide-semiconductor is connected in power supply loop, and stabilized supply voltage is controlled by controlling the grid voltage of metal-oxide-semiconductor.
A kind of 2. low-power consumption LDO systems as claimed in claim 1, it is characterised in that：The micro-current generation circuit is by first
PMOS tube PM1, the second PMOS tube PM2, the 3rd PMOS tube PM3, the 4th PMOS tube PM4, the first PNP triode Q1, the 8th NMOS
Pipe NM8 and the 9th NMOS tube NM9 are formed, and the source electrode of PM1 pipes is connected with the source electrode of PM2 pipes and is connected to LVDD；The grid of PM2 pipes
Pole and the grid of PM1 pipes, the grid of PM3 pipes, the drain electrode of PM3 pipes, the drain electrode of grid, NM8 pipes of PM4 pipes are connected, its node
It is labeled as VP；The drain electrode of PM2 pipes is connected with the source electrode of PM4 pipes；The source electrode of the drain electrode PM3 pipes of PM1 pipes is connected；PM4 pipes
Drain electrode is connected with the emitter of Q1 pipes, the grid of NM8 pipes；The source electrode of NM8 pipes is connected with the drain electrode of the grid, NM9 pipes of NM9 pipes
Connect；The base stage of Q1 pipes, the collector of Q1 pipes, the source electrode ground connection of NM9 pipes.
A kind of 3. low-power consumption LDO systems as claimed in claim 1, it is characterised in that：The reference generating circuit is by the 5th
PMOS tube PM5, the 6th PMOS tube PM6, the 7th PMOS tube PM7, the 8th PMOS tube PM8, the 9th PMOS tube PM9, the tenth PMOS tube
PM10, the 11st PMOS tube PM11, the 12nd PMOS tube PM12, the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube
NM3, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7, first resistor R1 are formed；
The source electrode of PM5 pipes is connected and is connected to the source electrode of the source electrode of PM6 pipes, the source electrode of PM7 pipes, the source electrode of PM8 pipes and PM1 pipes
LVDD；The grid of PM5 pipes, the grid of PM6 pipes, the grid of PM7 pipes, the grid of PM8, the grid of PM9 pipes, PM10 pipes grid,
The grid of PM11 pipes, the grid of the grid and PM2 pipes of PM12 pipes link together；The drain electrode of PM8 pipes and the source electrode phase of PM12 pipes
Connection；The drain of PM12 pipes is connected with the grid of the drain of NM6 pipes, the grid of NM6 pipes, NM7 pipes；The source electrode and NM7 of NM6 pipes
The drain of pipe, the source electrode of NM5 pipes are connected；The source electrode ground connection of NM7 pipes；The drain electrode of PM7 pipes is connected with the source electrode of PM11 pipes；
The drain of PM11 pipes is connected with the grid of the drain of NM4 pipes, the grid of NM4 pipes, NM5 pipes；The source electrode of NM4 pipes and NM5 pipes
Drain, the source electrode of NM3 pipes are connected；The drain electrode of PM6 pipes is connected with the source electrode of PM10 pipes；The drain of PM10 pipes and NM2 pipes
Grid, the drain of NM2 pipes, the grid of NM3 pipes are connected；The source electrode of NM2 pipes is connected with the drain of NM3 pipes, the source electrode of NM1 pipes
Connect；The drain electrode of PM5 pipes is connected with the source electrode of PM9 pipes；The drain of PM9 pipes is connected with one end of resistance R1, its node label
For VREF；The other end of resistance R1 is connected with the grid of NM1 pipes, the drain of NM1 pipes.
A kind of 4. low-power consumption LDO systems as claimed in claim 1, it is characterised in that：The regulator circuit by the first capacitance C1,
Second capacitance C2, second resistance R2, the 13rd PMOS tube PM13, the 14th PMOS tube PM14, the 15th PMOS tube PM15, the tenth
Six PMOS tube PM16, the 17th PMOS tube PM17, the 18th PMOS tube PM18, the 19th PMOS tube PM19, the 20th PMOS tube
PM20, the 21st PMOS tube PM21, the 22nd PMOS tube PM22, the 23rd PMOS tube PM23, the 24th PMOS tube
PM24, the tenth NMOS tube NM10, the 11st NMOS tube NM11, the 12nd NMOS tube NM12, the 13rd NMOS tube NM13, the 14th
NMOS tube NM14, the 15th NMOS tube NM15, the 16th NMOS tube NM16 and the 17th NMOS tube NM17 are formed；The one of capacitance C1
End, the source electrode of PM24 pipes, the source electrode of PM23 pipes, the source electrode of PM22 pipes, the source electrode of PM21 pipes, NM16 pipes drain electrode all with high-voltage electricity
Source HVDD is connected；The other end of capacitance C1 is connected with the drain electrode of the grid and NM17 pipes of NM16 pipes, node label ST；
The grid of PM24 pipes is connected with the grid of the drain electrode of PM24 pipes, the grid of PM23 pipes, the drain electrode of NM14 pipes and NM14 pipes；NM14
The source electrode of pipe is connected with the drain electrode of NM12 pipes；The drain electrode of PM23 pipes and the drain electrode of PM22 pipes, the grid of PM22 pipes, PM21 pipes
The drain electrode of grid, NM15 pipes is connected with the grid of NM15 pipes；The source electrode of NM15 pipes is connected with the drain electrode of NM13 pipes；PM21 is managed
Drain electrode be connected with the source electrode of the source electrode of NM16 pipes, the source electrode of PM17 pipes, the source electrode of PM13 pipes, one end of capacitance C2 and PM2 pipes
Connect, output terminal of its node as low pressure LVDD；The grid of PM13 pipes is connected with the drain electrode of PM13 pipes and the source electrode of PM14 pipes；
The grid of PM14 pipes is connected with the drain electrode of PM14 pipes and one end of resistance R2；The source electrode phase of the other end of resistance R2 and PM15 pipes
Connection；The grid of PM15 pipes is connected with the drain electrode of PM15 pipes and the source electrode of PM16 pipes, its node label is VFB；PM17 pipes
The grid of grid and PM18 pipes is all connected with node VP；The drain electrode of PM17 pipes is connected with PM18 pipe source electrodes；The leakage of PM18 pipes
Pole is connected with the source electrode of PM19 pipes and the source electrode of PM20 pipes；The grid connecting node VFB of PM19 pipes；The grid of PM20 pipes and
The grid of NM17 pipes all connecting node VREF；The drain electrode of PM19 pipes and the drain electrode of NM10 pipes, the grid of NM10 pipes and NM13 pipes
Grid is connected, its node label is NET2；The drain electrode of PM20 pipes and the drain electrode of NM11 pipes, the grid of NM11 pipes and NM12 pipes
Grid is connected, its node label is NET1；The source electrode of NM17 pipes, the source electrode of NM12 pipes, the source electrode of NM13 pipes, the source of NM10 pipes
Pole, the source electrode of NM11 pipes, the grid of PM16 pipes, the other end of the drain electrode of PM16 pipes and capacitance C2 are all grounded.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711009140.5A CN107908221A (en) | 2017-10-25 | 2017-10-25 | A kind of low-power consumption LDO systems |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711009140.5A CN107908221A (en) | 2017-10-25 | 2017-10-25 | A kind of low-power consumption LDO systems |
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| CN107908221A true CN107908221A (en) | 2018-04-13 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111562806A (en) * | 2020-05-18 | 2020-08-21 | 西安拓尔微电子有限责任公司 | Reference source circuit for realizing low temperature coefficient voltage and current on CMOS (complementary metal oxide semiconductor) process |
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| CN103792979A (en) * | 2012-11-02 | 2014-05-14 | 上海华虹集成电路有限责任公司 | Serial voltage-stabilizing circuit in radio frequency identification |
| CN204462924U (en) * | 2015-03-26 | 2015-07-08 | 厦门新页科技有限公司 | Reference voltage circuit |
| CN105786082A (en) * | 2016-05-30 | 2016-07-20 | 江南大学 | Band-gap reference voltage source without resistor or operational amplifier |
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2017
- 2017-10-25 CN CN201711009140.5A patent/CN107908221A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050127987A1 (en) * | 2003-12-16 | 2005-06-16 | Yukio Sato | Reference voltage generating circuit |
| CN103699167A (en) * | 2012-09-28 | 2014-04-02 | 上海华虹集成电路有限责任公司 | Reference voltage circuit for radiofrequency identification |
| CN103792979A (en) * | 2012-11-02 | 2014-05-14 | 上海华虹集成电路有限责任公司 | Serial voltage-stabilizing circuit in radio frequency identification |
| CN204462924U (en) * | 2015-03-26 | 2015-07-08 | 厦门新页科技有限公司 | Reference voltage circuit |
| CN105786082A (en) * | 2016-05-30 | 2016-07-20 | 江南大学 | Band-gap reference voltage source without resistor or operational amplifier |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111562806A (en) * | 2020-05-18 | 2020-08-21 | 西安拓尔微电子有限责任公司 | Reference source circuit for realizing low temperature coefficient voltage and current on CMOS (complementary metal oxide semiconductor) process |
| CN111562806B (en) * | 2020-05-18 | 2024-06-04 | 拓尔微电子股份有限公司 | Reference source circuit for realizing low temperature coefficient voltage and current in CMOS process |
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Application publication date: 20180413 |
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