CN115079762A - Low dropout linear regulator circuit - Google Patents
Low dropout linear regulator circuit Download PDFInfo
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The application discloses low dropout linear regulator circuit, including source follower, low dropout regulator and low-voltage starting circuit. Wherein, the low pressure starting circuit is used for pulling down the grid voltage of the voltage adjusting tube under the condition that the input voltage is higher than the first threshold voltage and the output voltage is lower than the second threshold voltage, thereby the voltage adjusting tube is basically and completely conducted, the output voltage is approximately equal to the input voltage, thereby the purpose of improving the voltage value of the output voltage in the starting process is realized, the problem that the output voltage of the existing low-dropout linear voltage regulator circuit is too low in the starting process is solved, and the improvement of the circuit stability is facilitated.
Description
Technical Field
The invention relates to the technical field of linear regulators, in particular to a low dropout regulator circuit.
Background
In modern electronic products, chips have become indispensable core components, and particularly, with the advance of integrated circuit manufacturing processes and the desire of human beings to integrate more complex functions in a Chip area as limited as possible, a small System Chip called a System On Chip (SOC) is promoted, wherein the SOC Chip generally comprises a microprocessor MCU, an analog IP core, a digital IP core, an embedded memory module, an external communication interface module, and a power management module provided by a power supply. In the actual chip design, different voltage-resistant devices (such as 1V \1.5V \1.8V \3.3V \5V, etc.) are often adopted in the SOC chip according to the requirements of the relationship among the area, the speed and the power consumption, and then the SOC chip needs to be supplied with power by corresponding power supply voltage.
Most portable electronic products use a lithium battery as a peripheral power supply to supply power, the voltage range of the lithium battery is 2.6V-3.6V, and obviously, the lithium battery cannot directly supply power to a Low-voltage module, and then different power supply voltages need to be designed inside an SOC chip to supply power to related modules, and a Low Dropout Regulator (LDO) is often used for on-chip power management of a chip of a mobile consumer electronic device because the LDO has the characteristics of simple structure, small static power consumption, small output voltage ripple, and the like.
Traditional LDO circuit can start smoothly in order to guarantee, generally can adopt source follower to add the LDO circuit and come the comprehensive power supply to back stage circuit component, when supply voltage is lower, adopts the source follower to supply power to back stage circuit before band gap reference circuit among the LDO circuit has not produced sufficient bias current, increases to make band gap reference circuit can produce behind the sufficient bias current LDO circuit when power supply and opens, and automatic switching is the output power supply of LDO circuit. However, because a margin of a threshold voltage is lost when the source follower circuit supplies power, an output voltage is generally lower before switching to supply power to the LDO circuit in the conventional scheme, and a deficiency of the supply voltage may cause some elements in a subsequent circuit to fail to operate normally, thereby reducing the stability of the system.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a low dropout regulator circuit, which can keep the output voltage substantially equal to the input voltage during the low voltage start-up process, thereby greatly increasing the output voltage during the start-up process and improving the stability of the system.
According to an embodiment of the present invention, there is provided a low dropout linear regulator circuit including: a source follower connected between an input node and an output node, configured to derive a first output voltage at the output node based on an input voltage at the input node if the input voltage at the input node is below a first threshold voltage; a low dropout voltage regulator including a voltage regulating transistor and an error amplifier configured to regulate a voltage at the output node based on a reference voltage and a feedback voltage to obtain a second output voltage at the output node if the voltage at the output node is above a second threshold voltage; and the low-voltage starting circuit is configured to completely conduct a voltage adjusting tube in the low-dropout voltage regulator under the conditions that the input voltage is higher than the first threshold voltage and the voltage at the output node is lower than the second threshold voltage.
Optionally, the low dropout regulator further comprises a bandgap reference circuit, the voltage regulating tube having a control terminal configured to receive a control signal and an output terminal coupled to the output node; the error amplifier is configured to modulate the control signal based on a feedback voltage of the output voltage and a reference voltage such that a voltage at the output node is regulated; the bandgap reference circuit is configured to generate the reference voltage and a bias current of the error amplifier based on an output voltage at the output node, and a magnitude of the bias current matches a voltage at the output node.
Optionally, the low-voltage start circuit includes: the power supply end of the low-voltage control module is connected with the output node, the input end of the low-voltage control module is connected with the bias current generated by the band-gap reference circuit, and the low-voltage control module is configured to compare the bias current with a set threshold value and generate a pull-down control signal according to the comparison result; and the pull-down module is connected between the control terminal of the voltage adjusting tube and the ground, the control terminal of the pull-down module is connected with the pull-down control signal, and the pull-down module is configured to pull down the control signal of the voltage adjusting tube according to the pull-down control signal.
Optionally, the low pressure control module includes: a fourth PMOS transistor and a first NMOS transistor which are sequentially connected between the output node and the ground, wherein the common end of the fourth PMOS transistor and the common end of the first NMOS transistor are used for outputting the pull-down control signal; and the third PMOS transistor and the fourth resistor are sequentially connected between the output node and the ground, the common end of the third PMOS transistor and the common end of the fourth resistor are connected with the control terminals of the fourth PMOS transistor and the first NMOS transistor, and the third PMOS transistor obtains the bias current in a mirror image mode.
Optionally, the pull-down module includes: and the third resistor and the tenth NMOS transistor are sequentially connected between the control terminal of the voltage adjusting tube and the ground, and the control terminal of the tenth NMOS transistor is connected with the pull-down control signal.
Optionally, when the bias current indicates that the output voltage is lower than the second threshold voltage, the first NMOS transistor is turned off, the fourth PMOS transistor is turned on, and the pull-down control signal is at a high level to turn on the tenth NMOS transistor; when the bias current represents that the output voltage is higher than the second threshold voltage, the first NMOS transistor is turned on, the fourth PMOS transistor is turned off, and the pull-down control signal is at a low level to turn off the tenth NMOS transistor.
Optionally, the source follower includes: a seventh resistor having a first end connected to the input voltage; a zener diode having a cathode connected to the second end of the seventh resistor and an anode connected to ground; and a ninth NMOS transistor having a first end connected to the input voltage, a control terminal connected to a second end of the seventh resistor, and a second end connected to the output node.
Optionally, when the input voltage is lower than the first threshold voltage, the ninth NMOS transistor is turned on, and a first output voltage is obtained at the output node according to the input voltage; when the input voltage is higher than the first threshold voltage, the ninth NMOS transistor is turned off.
Optionally, the bandgap reference circuit includes: the fifth PMOS transistor, the eighth PMOS transistor, the sixth resistor, the first bipolar transistor and the fifth resistor are sequentially connected between the output node and the ground; a sixth PMOS transistor, a ninth PMOS transistor, and a second bipolar transistor sequentially connected between the output node and ground, control terminals of the fifth PMOS transistor and the sixth PMOS transistor being connected to a first end of the sixth resistor, control terminals of the eighth PMOS transistor and the ninth PMOS transistor being connected to a second end of the sixth resistor, and control terminals of the first bipolar transistor and the second bipolar transistor being connected to an output terminal of the reference voltage; a second NMOS transistor connected between the output node and an output terminal of the reference voltage, a control terminal being connected to a second end of the ninth PMOS transistor; and a seventh PMOS transistor, a tenth PMOS transistor, and a third NMOS transistor sequentially connected between the output node and ground, a control terminal of the seventh PMOS transistor being connected to a control terminal of the fifth PMOS transistor, a control terminal of the tenth PMOS transistor being connected to a control terminal of the eighth PMOS transistor, the third NMOS transistor providing the bias current to the error amplifier in a mirror image manner.
Optionally, the error amplifier includes: a fifth NMOS transistor and a sixth NMOS transistor, a control terminal of the fifth NMOS transistor is connected with the reference voltage, and a control terminal of the sixth NMOS transistor is connected with the feedback voltage; a first end of the fourth NMOS transistor is connected to second ends of the fifth NMOS transistor and the sixth NMOS transistor, a second end of the fourth NMOS transistor is grounded, and the fourth NMOS transistor obtains the bias current in a mirror image manner; and the eleventh PMOS transistor is connected between the input voltage and the first end of the fifth NMOS transistor, the twelfth PMOS transistor is connected between the input voltage and the first end of the sixth NMOS transistor, control terminals of the eleventh PMOS transistor and the twelfth PMOS transistor are connected with the second end of the twelfth PMOS transistor, and a common end of the eleventh PMOS transistor and the fifth NMOS transistor is connected with the control terminal of the voltage regulating tube.
Optionally, the error amplifier further includes: a seventh NMOS transistor connected between the eleventh PMOS transistor and the fifth NMOS transistor; and an eighth NMOS transistor connected between the twelfth PMOS transistor and the sixth NMOS transistor, wherein the seventh NMOS transistor and the eighth NMOS transistor are high voltage clamp transistors, and control terminals of the seventh NMOS transistor and the eighth NMOS transistor are connected to the output node.
Optionally, the low dropout regulator circuit further includes: and the first PMOS transistor and the second PMOS transistor are sequentially connected between the input voltage and the voltage adjusting tube and are low-voltage clamping transistors.
In summary, the low dropout regulator circuit according to the embodiment of the invention includes a source follower, a low dropout regulator and a low voltage start-up circuit. The low dropout regulator comprises a voltage adjusting tube and an error amplifier, wherein the voltage adjusting tube is used for adjusting the voltage at the output node based on a reference voltage and a feedback voltage to obtain a second output voltage at the output node under the condition that the voltage at the output node is higher than a second threshold voltage, the low dropout regulator is used for pulling down the grid voltage of the voltage adjusting tube under the condition that the input voltage is higher than the first threshold voltage and the output voltage is lower than the second threshold voltage, so that the voltage adjusting tube is basically and completely conducted, the output voltage is approximately equal to the input voltage, the purpose of improving the voltage value of the output voltage in the starting process is realized, and the problem that the output voltage of the existing low dropout linear regulator circuit is too low in the starting process is solved, the stability of the circuit is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
FIG. 1 is a block diagram of a system architecture of a low dropout linear regulator circuit according to an embodiment of the present invention;
fig. 2 shows a circuit schematic of a low dropout linear regulator circuit according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or sub-circuit through an electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
In the present application, a voltage regulator is a transistor operating in a linear mode to provide a current path, including one selected from a bipolar transistor or a field effect transistor. The input terminal and the output terminal of the voltage adjusting tube are respectively a high potential end and a low potential end on the current path, and the control terminal is used for receiving a driving signal to control the voltage drop of the voltage adjusting tube. The voltage regulator may be a PMOS (P-Metal-Oxide-Semiconductor) transistor or an NMOS (N-Metal-Oxide-Semiconductor) transistor. The first terminal, the second terminal, and the control terminal of the PMOS transistor are a source, a drain, and a gate, respectively, and the first terminal, the second terminal, and the control terminal of the NMOS transistor are a drain, a source, and a gate, respectively.
The invention is described in detail below with reference to the figures and the specific embodiments.
Referring to fig. 1, fig. 1 shows a system configuration block diagram of a low dropout linear regulator circuit 100 according to an embodiment of the present invention, which includes a source follower 110, a low dropout regulator 120 and a low voltage start-up circuit 130. The low dropout linear regulator circuit 100 is configured to support operation in a situation (e.g., where the input voltage VIN is below a first threshold voltage) to enable the source follower 110 to derive the output voltage VOUT from the input voltage VIN to power the subsequent stage circuit; and supports operation in another case (e.g., where the input voltage VIN is higher than the first threshold voltage) to power the subsequent stage circuits through the low dropout regulator 120. The ldo 120 includes a bandgap reference circuit (voltage reference)121, an Error Amplifier (Error Amplifier)122, and a voltage regulator MH3, the voltage regulator MH3 having a source-drain current path coupled between an input voltage VIN and an output voltage VOUT and configured to provide current to an output node. Specifically, the voltage-adjusting transistor MH3 is implemented by a PMOS transistor having its source coupled to the input voltage VIN node and the drain of the voltage-adjusting transistor MH3 coupled to the output voltage VOUT node. The gate terminal of the voltage adjusting transistor MH3 is configured to receive a control signal PG as the gate voltage of the voltage adjusting transistor MH3, which can control the current of the voltage adjusting transistor MH 3. The load capacitor CL and the load resistor RL are connected between the output voltage VOUT node and ground.
The error amplifier 122 has a positive input terminal for receiving the feedback voltage VFB of the output voltage VOUT, an inverted input terminal for receiving the reference voltage VREF, and an output terminal connected to the gate terminal of the voltage regulator MH3 to output the control signal PG. Error amplifier 122 compares feedback voltage VFB with reference voltage VREF, and when a deviation occurs between the feedback voltage VFB and reference voltage VREF, error amplifier 122 amplifies the deviation to control the source-drain voltage drop of voltage regulator MH 3. In this embodiment, when the output voltage VOUT decreases, the voltage difference between the feedback voltage VFB and the reference voltage VREF increases, so that the voltage applied to the control terminal of the voltage regulator MH3 increases, the on-resistance between the first terminal and the second terminal of the voltage regulator MH3 decreases, the voltage drop across the voltage regulator MH3 decreases, so that the voltage at the output terminal of the low dropout linear regulator circuit 100 increases, and the output voltage VOUT returns to a normal level.
In other embodiments of the present invention, the low dropout regulator 120 further comprises a resistive feedback network connected between the output voltage VOUT node and ground, and the error amplifier 122 generates the control signal PG according to a voltage difference between a feedback voltage VFB provided by the resistive feedback network and a reference voltage VREF. As an example, the low dropout regulator circuit 100 includes a resistor R1 and a resistor R2 connected in series between the output voltage VOUT node and ground, with the intermediate node of the resistor R1 and the resistor R2 being used to provide the feedback voltage VFB of the output voltage VOUT.
The supply terminal of the bandgap reference circuit 121 is connected to the output of the source follower 110 for generating a bias current for the error amplifier 122 to normally operate and a stable reference voltage VREF. In this embodiment, the bandgap reference circuit 121 generates a bias current and a stable reference voltage, which have requirements on the voltage of the output voltage VOUT, and when the output voltage VOUT is low, the bandgap reference circuit 121 cannot generate a sufficient bias current, so the low dropout regulator circuit 100 of this embodiment further includes a low voltage start circuit 130, where the low voltage start circuit 130 is configured to pull down the gate voltage of the voltage regulating tube MH3 when the output voltage VOUT is lower than a second threshold voltage, so that the voltage regulating tube MH3 is substantially completely turned on, so that the output voltage VOUT is approximately equal to the input voltage VIN, thereby achieving the purpose of increasing the voltage value of the output voltage VOUT during the start-up process.
Specifically, the low voltage start-up circuit 130 includes a low voltage control module 131 and a pull-down module 132. The first end of the Pull-down module 132 is connected to the gate of the voltage adjusting transistor MH3, the second end is grounded, the control end is connected to the output of the low-voltage control module 131 to receive the Pull-down control signal Pull, the power supply end of the low-voltage control module 131 is connected to the node of the output voltage VOUT, the input end is connected to the bias current Ib generated by the bandgap reference circuit 121, the low-voltage control module 131 is configured to compare the bias current Ib with a set threshold, determine the current potential of the output voltage VOUT according to the comparison result, and then control the high-low level state of the Pull-down control signal Pull. As mentioned above, the magnitude of the bias current Ib generated by the bandgap reference circuit 121 is related to the magnitude of the output voltage VOUT, when the output voltage VOUT is lower than a second threshold voltage, the bias current Ib is smaller than the set threshold, the low voltage control module 131 provides the Pull-down control signal Pull at a high level to turn on the Pull-down module 132, and when the output voltage VOUT is higher than the second threshold voltage, the bias current Ib is higher than the set threshold, the low voltage control module 131 provides the Pull-down control signal Pull at a low level to turn off the Pull-down module 132.
It should be noted that the bandgap reference circuit 121 of the embodiment of the present invention is mainly used for providing a reference current and a reference voltage VREF which are approximately invariant with temperature and power supply voltage, and may be implemented by various bandgap reference voltage sources in the art, which is not limited to this invention.
Referring to fig. 2, fig. 2 shows a circuit schematic of a low dropout linear regulator circuit according to an embodiment of the invention. The source follower 110 includes a resistor R7, a zener diode DZ, and an NMOS transistor MN 9. The resistor R7 and the zener diode DZ are sequentially connected between the input voltage VIN and the ground GND, an anode of the zener diode DZ is connected to one end of the resistor R7 away from the input voltage VIN, a cathode of the zener diode DZ is connected to the ground GND, the NMOS transistor MN9 is, for example, a high-voltage NMOS transistor, a gate of the NMOS transistor MN9 is connected to the anode of the zener diode DZ, a drain of the NMOS transistor MN is connected to the input voltage VIN, and a source of the NMOS transistor is connected to a node of the output voltage VOUT.
The bandgap reference circuit 121 includes PMOS transistors MP5 to MP10, bipolar transistors Q1 and Q2, resistors R5 and R6, and NMOS transistors MN2 and MN 3. The bipolar transistors Q1 and Q2 are NPN transistors, for example, sources of the PMOS transistors MP5 and MP6 are connected to the node VOUT, drains are connected to sources of the PMOS transistors MP8 and MP9, respectively, a first end of the resistor R6 is connected to the drain of the PMOS transistor MP8, and a second end is connected to a collector of the NPN transistor Q1. In addition, the gates of the PMOS transistors MP5 and MP6 are connected to the first end of the resistor R6, and the gates of the PMOS transistors MP8 and MP9 are connected to the second end of the resistor R6. An emitter of the NPN transistor Q1 is connected to a first terminal of the resistor R5, and a second terminal of the resistor R5 is connected to the ground GND. The NPN transistor Q2 has a first terminal connected to the drain of the PMOS transistor MP9, an emitter connected to ground GND, a base connected to the base of the NPN transistor Q1, and a common node for outputting the reference voltage VREF. The NMOS transistor MN2 has a drain connected to the output voltage VOUT, a gate connected to the drain of the PMOS transistor MP9, and a source connected to the reference voltage VREF node. The PMOS transistors MP7, MP10 and the NMOS transistor MN3 are sequentially connected between the output voltage VOUT and the ground GND, the PMOS transistor MP7 and the PMOS transistors MP5 and MP6 respectively form a current mirror, the PMOS transistor MP10 and the PMOS transistors MP8 and MP9 respectively form a current mirror, the PMOS transistors MP7 and MP10 provide the bias current generated by the bandgap reference circuit 121 to the NMOS transistor MN3 in a mirror image manner, and the NMOS transistor MN3 mirrors the current to the error amplifier 122 as a tail current of the operational amplifier.
The error amplifier 122 includes NMOS transistors MN4 to MN8 and PMOS transistors MP11 and MP 12. The NMOS transistors MN5 and MN6 form an input differential pair transistor of the error amplifier, the NMOS transistors MN7 and MN8 are high-voltage clamp NMOS transistors, the PMOS transistors MP11 and MP12 form a current source load of the error amplifier, and the NMOS transistor MN4 and the NMOS transistor MN3 form a current mirror to provide a tail current to the error amplifier 122 in a mirror image manner. The sources of the PMOS transistors MP11 and MP12 are connected to the input voltage VIN, the drains of the PMOS transistors MP12 are connected to the gates of the PMOS transistors MP11 and MP12, the drains of the PMOS transistors MP11 and MP12 are also connected to the drains of the high-voltage clamp NMOS transistors MN7 and MN8, the gates of the high-voltage clamp NMOS transistors MN7 and MN8 are connected to the output voltage VOUT node, the sources of the high-voltage clamp NMOS transistors MN7 and MN8 are connected to the drains of the differential pair transistors MN5 and MN6, the gates of the NMOS transistors MN5 and MN6 are connected to the reference voltage VREF and the feedback voltage VFB, the drain of the NMOS transistor MN4 is connected to the sources of the NMOS transistors MN5 and MN6, the gates are connected to the gate and the drain of the NMOS transistor MN3, and the sources are connected to ground GND.
The source of the voltage adjusting tube MH3 is connected to the input voltage VIN, the gate is connected to the drain of the PMOS transistor MP11, the drain is connected to the output voltage VOUT node, and the resistors R1 and R2 are sequentially connected between the output voltage VOUT node and ground GND to form a voltage dividing resistor network to provide the feedback voltage VFB of the output voltage VOUT.
Further, the low dropout linear regulator circuit 100 of the present embodiment further includes low voltage clamp PMOS transistors MP1 and MP2, the PMOS transistors MP1 and MP2 are sequentially connected between the input voltage VIN and the gate of the voltage regulating transistor MH3, and the gates and drains of the PMOS transistors MP1 and MP2 are connected to each other.
Further, the low dropout regulator 100 of the present embodiment further includes a compensation capacitor C1 and a compensation resistor R8, and the compensation capacitor C1 and the compensation resistor R8 are sequentially connected between the source of the NMOS transistor MN7 and the node of the output voltage VOUT.
With reference to fig. 2, the Pull-down module 132 includes a resistor R3 and an NMOS transistor MN10, the resistor R3 and the NMOS transistor MN10 are sequentially connected between the gate of the voltage regulator MH3 and the ground GND, the drain of the NMOS transistor MN10 is connected to the resistor R3, the source is connected to the ground GND, and the gate is connected to the Pull-down control signal Pull.
The low voltage control module 131 includes an NMOS transistor MN1, PMOS transistors MP3 and MP4, and a resistor R4. The source of the PMOS transistor MP4 is connected to the output voltage VOUT, the drain is used for outputting the Pull-down control signal Pull, the drain of the NMOS transistor MN1 is connected to the drain of the PMOS transistor MP4, the source of the NMOS transistor MN1 is connected to ground GND, the gate of the NMOS transistor MN1 is connected to the gate of the PMOS transistor MP4, the source of the PMOS transistor MP3 is connected to the output voltage VOUT, the gate is connected to the gates of the PMOS transistors MP5 and MP6, the drain is connected to the gate of the PMOS transistor MP4 and the first end of the resistor R4, and the second end of the resistor R4 is connected to ground GND. The PMOS transistor MP3 and the PMOS transistor MP5 constitute a current mirror for obtaining the bias current Ib generated in the bandgap reference circuit 121 by way of mirroring.
As mentioned above, the bandgap reference circuit 121 generates the bias current and the stable reference voltage, which have voltage requirements for the output voltage VOUT, and it is assumed that the bandgap reference circuit 121 can generate the bias current and the reference voltage enough for the error amplifier 122 to operate normally when the output voltage VOUT is equal to the set value V1. The PMOS transistor MP3 mirrors the current Ib of the PMOS transistor MP5 to the resistor R4, assuming that I _ MP3 is k Ib, where I _ MP3 is the current in the PMOS transistor MP3, Ib is the bias current generated by the bandgap reference circuit 121 and capable of making the operational amplifier normally operate, and the threshold voltage of the high-voltage NMOS transistor is VTH _ HN and the threshold voltage of the low-voltage MOS transistor is VTH _ L. When the output voltage VOUT is V1, the gate voltage VG _ MN1 of the NMOS transistor MN1 is I _ MP 3R 4 k Ib R4, and VG _ MN1> V1/2 has a resistor R4> V1/(2k Ib). By setting the coefficient k, the VG _ MN1 can be made to approach the preset output value of the output voltage VOUT when the bandgap reference normally operates, so as to determine the coefficient k and the value of the resistor R4.
When the input voltage VIN < VTH _ HN + VTH _ L (i.e., VTH _ HN + VTH _ L is the first threshold voltage), and the output voltage VOUT < VTH _ L, the PMOS transistor MP4 and the NMOS transistor MN1 in the low-voltage control module 131 are both in an off state, and at this time, the gate of the NMOS transistor MN10 is in a high-impedance state, and the source follower formed by the NMOS transistor MN9 ensures the generation of the output voltage VOUT at this time. When the input voltage VIN > VTH _ HN + VTH _ L and VTH _ L < VOUT < V1, the NMOS transistor MN9 in the source follower 110 is turned off, the NMOS transistor MN1 in the low-voltage control module 131 is in an off state, and the PMOS transistor MP4 is turned on, so that the Pull-down control signal Pull is high, the NMOS transistor MN4 in the Pull-down module 132 is turned on, and pulls down the gate of the voltage adjustment tube MH3, and the gate-source voltage of the voltage adjustment tube MH3 is VGS _ MP1+ VGS _ MP2, where VGS _ MP1 and VGS _ MP2 are the gate-source voltages of the PMOS transistors MP1 and MP2, respectively, so that the voltage adjustment tube MH3 is substantially completely turned on, and the output voltage is approximately equal to the input voltage VOUT. When the output voltage VOUT > V1, the Pull-down control signal Pull is inverted to a low level to turn off the NMOS transistor MN10, and the bias current generated by the bandgap reference circuit 121 is sufficient to make the operational amplifier operate normally, so that the output voltage VOUT is adjusted to a preset output value by the error amplifier 122.
Accordingly, the embodiment of the present invention further provides an electronic device, which includes the low dropout regulator circuit 100 provided in the above embodiment.
In one embodiment of the present invention, the electronic device provided by the present invention may be a portable electronic device such as a cellular phone.
In summary, the embodiment of the invention provides a low dropout regulator circuit, which includes a source follower, a low dropout regulator and a low voltage start-up circuit. The low dropout regulator comprises a voltage adjusting tube and an error amplifier, wherein the voltage adjusting tube is used for adjusting the voltage at the output node based on a reference voltage and a feedback voltage to obtain a second output voltage at the output node under the condition that the voltage at the output node is higher than a second threshold voltage, the low dropout regulator is used for pulling down the grid voltage of the voltage adjusting tube under the condition that the input voltage is higher than the first threshold voltage and the output voltage is lower than the second threshold voltage, so that the voltage adjusting tube is basically and completely conducted, the output voltage is approximately equal to the input voltage, the purpose of improving the voltage value of the output voltage in the starting process is realized, and the problem that the output voltage of the existing low dropout linear regulator circuit is too low in the starting process is solved, the stability of the circuit is improved.
It is noted that relational terms such as first and second, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined from the following claims.
Claims (12)
1. A low dropout linear regulator circuit comprising:
a source follower connected between an input node and an output node, configured to derive a first output voltage at the output node based on an input voltage at the input node if the input voltage at the input node is below a first threshold voltage;
a low dropout voltage regulator including a voltage regulating transistor and an error amplifier configured to regulate a voltage at the output node based on a reference voltage and a feedback voltage to obtain a second output voltage at the output node if the voltage at the output node is above a second threshold voltage; and
a low voltage start-up circuit configured to fully conduct a voltage regulation tube in the LDO if the input voltage is higher than the first threshold voltage and the voltage at the output node is lower than the second threshold voltage.
2. The low dropout linear regulator circuit of claim 1, wherein the low dropout linear regulator further comprises a bandgap reference circuit,
the voltage regulating tube has a control terminal configured to receive a control signal and an output terminal coupled to an output node;
the error amplifier is configured to modulate the control signal based on a feedback voltage of the output voltage and a reference voltage such that a voltage at the output node is regulated;
the bandgap reference circuit is configured to generate the reference voltage and a bias current of the error amplifier based on an output voltage at the output node, and a magnitude of the bias current matches a voltage at the output node.
3. The low dropout linear regulator circuit of claim 2, wherein the low voltage start-up circuit comprises:
the power supply end of the low-voltage control module is connected with the output node, the input end of the low-voltage control module is connected with the bias current generated by the band-gap reference circuit, and the low-voltage control module is configured to compare the bias current with a set threshold value and generate a pull-down control signal according to the comparison result; and
the pull-down module is connected between the control terminal of the voltage adjusting tube and the ground, and the control terminal of the pull-down module is connected with the pull-down control signal and is configured to pull down the control signal of the voltage adjusting tube according to the pull-down control signal.
4. The low dropout linear regulator circuit of claim 3, wherein the low voltage control module comprises:
a fourth PMOS transistor and a first NMOS transistor which are sequentially connected between the output node and the ground, wherein the common end of the fourth PMOS transistor and the common end of the first NMOS transistor are used for outputting the pull-down control signal; and
the third PMOS transistor and the fourth resistor are sequentially connected between the output node and the ground, the common end of the third PMOS transistor and the common end of the fourth resistor are connected with the control terminals of the fourth PMOS transistor and the first NMOS transistor, and the third PMOS transistor obtains the bias current in a mirror image mode.
5. The low dropout linear regulator circuit of claim 4, wherein the pull-down module comprises:
and the third resistor and the tenth NMOS transistor are sequentially connected between the control terminal of the voltage adjusting tube and the ground, and the control terminal of the tenth NMOS transistor is connected with the pull-down control signal.
6. The low dropout linear regulator circuit of claim 5, wherein the first NMOS transistor is turned off, the fourth PMOS transistor is turned on, and the pull-down control signal is high to turn on the tenth NMOS transistor when the bias current is indicative of the output voltage being below the second threshold voltage;
when the bias current represents that the output voltage is higher than the second threshold voltage, the first NMOS transistor is turned on, the fourth PMOS transistor is turned off, and the pull-down control signal is at a low level to turn off the tenth NMOS transistor.
7. The low dropout linear regulator circuit of claim 1, wherein the source follower comprises:
a seventh resistor having a first end connected to the input voltage;
a zener diode having a cathode connected to the second end of the seventh resistor and an anode connected to ground; and
a ninth NMOS transistor having a first end connected to the input voltage, a control terminal connected to a second end of the seventh resistor, and a second end connected to the output node.
8. The low dropout linear regulator circuit of claim 7, wherein the ninth NMOS transistor is turned on when the input voltage is below the first threshold voltage, resulting in a first output voltage at the output node from the input voltage;
when the input voltage is higher than the first threshold voltage, the ninth NMOS transistor is turned off.
9. The low dropout linear regulator circuit of claim 2, wherein the bandgap reference circuit comprises:
the fifth PMOS transistor, the eighth PMOS transistor, the sixth resistor, the first bipolar transistor and the fifth resistor are sequentially connected between the output node and the ground;
a sixth PMOS transistor, a ninth PMOS transistor, and a second bipolar transistor sequentially connected between the output node and ground, control terminals of the fifth PMOS transistor and the sixth PMOS transistor being connected to a first end of the sixth resistor, control terminals of the eighth PMOS transistor and the ninth PMOS transistor being connected to a second end of the sixth resistor, and control terminals of the first bipolar transistor and the second bipolar transistor being connected to an output terminal of the reference voltage;
a second NMOS transistor connected between the output node and an output terminal of the reference voltage, a control terminal being connected to a second end of the ninth PMOS transistor; and
a seventh PMOS transistor, a tenth PMOS transistor and a third NMOS transistor connected in sequence between the output node and ground, a control terminal of the seventh PMOS transistor being connected to a control terminal of the fifth PMOS transistor, a control terminal of the tenth PMOS transistor being connected to a control terminal of the eighth PMOS transistor,
the third NMOS transistor provides the bias current to the error amplifier in a mirrored manner.
10. The low dropout linear regulator circuit of claim 2, wherein the error amplifier comprises:
a fifth NMOS transistor and a sixth NMOS transistor, a control terminal of the fifth NMOS transistor being connected to the reference voltage, a control terminal of the sixth NMOS transistor being connected to the feedback voltage;
a first end of the fourth NMOS transistor is connected to second ends of the fifth NMOS transistor and the sixth NMOS transistor, a second end of the fourth NMOS transistor is grounded, and the fourth NMOS transistor obtains the bias current in a mirror image manner; and
the voltage regulating tube comprises an eleventh PMOS transistor and a twelfth PMOS transistor, the eleventh PMOS transistor is connected between the input voltage and the first end of the fifth NMOS transistor, the twelfth PMOS transistor is connected between the input voltage and the first end of the sixth NMOS transistor, control terminals of the eleventh PMOS transistor and the twelfth PMOS transistor are connected with the second end of the twelfth PMOS transistor, and a common end of the eleventh PMOS transistor and the fifth NMOS transistor is connected with the control terminal of the voltage regulating tube.
11. The low dropout linear regulator circuit of claim 10, wherein the error amplifier further comprises:
a seventh NMOS transistor connected between the eleventh PMOS transistor and the fifth NMOS transistor; and
an eighth NMOS transistor connected between the twelfth PMOS transistor and the sixth NMOS transistor,
wherein the seventh and eighth NMOS transistors are high voltage clamp transistors, and control terminals of the seventh and eighth NMOS transistors are connected to the output node.
12. The low dropout linear regulator circuit of claim 2, further comprising:
and the first PMOS transistor and the second PMOS transistor are sequentially connected between the input voltage and the voltage adjusting tube and are low-voltage clamping transistors.
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