CN107402594A - Realize the low-power consumption low pressure difference linear voltage regulator of high power supply voltage transformation - Google Patents

Abstract

The present invention relates to integrated circuit technology. The invention solves the problem of large power consumption of the existing low-dropout linear voltage regulator, and provides a low-power consumption low-dropout linear voltage regulator that realizes high power supply voltage conversion, and its technical scheme can be summarized as: realizing high power supply voltage Transformed low-power low-dropout linear regulator, including external power input terminal, voltage output terminal, PMOS tube 1, PMOS tube 2, NJFET withstand voltage tube 1, NJFET withstand voltage tube 2, NMOS tube 1, NMOS tube 2, Depletion NMOS tube, diode, resistor 1 and resistor 2. The beneficial effect of the present invention is that it avoids the use of error amplifiers and bandgap reference sources, has simple circuit structure, low power consumption, can realize the conversion of high-voltage power supplies, and is suitable for low-dropout linear regulators.

Description

Low Power Low Dropout Linear Regulator for High Supply Voltage Transitions

technical field

The invention relates to integrated circuit technology, in particular to a low-dropout linear regulator.

Background technique

Low dropout regulator (Low Dropout Regulator, LDO), as the main component of modern power management chips, is a miniature system-on-chip with very low self-power consumption. It is usually composed of a very low on-resistance R _DS(ON) Functional modules such as MOS adjustment tube, reference power supply, error amplifier and various protection circuits are integrated on the same chip. It is characterized in that there is no switching action during the working process, the noise is relatively low, the design of the whole unit is simple, the number of components is small, and the entire chip area is small and easy to integrate. The main technical indicators of LDO include: dropout voltage, linear regulation rate, load regulation rate, power supply rejection ratio (Power Supply Rejection, PSR), load transient response, etc.

The basic structure of the LDO is shown in Figure 1. It consists of an external voltage input terminal, a bandgap reference source BGR, an error amplifier A(S), an NMOS transistor MP, a resistor R1, a resistor R2, an oscillation resistor Rload, and a capacitor Cload. NMOS Tube two MP is the power tube; the bandgap reference source BGR provides the reference voltage for the inverting input terminal of the error amplifier A(S); the error amplifier A(S) divides the output voltage V _out through the resistance one R1 and the resistance two R2 Compared with the reference voltage, the difference between the two is amplified, and the gate voltage of the power transistor MP is adjusted to increase or decrease the current provided by the power transistor MP to charge and discharge the capacitor Cload, thereby stabilizing the output voltage V _out .

The above circuit structure generates a temperature-independent reference level through the bandgap reference source BGR, and adjusts the proportional relationship between resistor 1 R1 and resistor 2 R2, and the output voltage can be obtained as

Among them, Vref is the reference voltage output from the bandgap reference source BGR to the non-inverting input terminal of the error amplifier A(S).

This circuit structure can achieve a relatively high-precision regulated output, but the entire circuit structure includes the bandgap reference source BGR and the error amplifier A(s), and the number of transistors used is large, which will lead to a relatively high overall power consumption of the circuit. At the same time, the area of the layout is usually designed to be relatively large.

Contents of the invention

The purpose of the present invention is to solve the problem of large power consumption of the current low-dropout linear voltage regulator, and provide a low-power low-dropout linear voltage regulator that realizes high power supply voltage transition.

The present invention solves the technical problem, and the technical solution adopted is that a low-power low-dropout linear voltage regulator for realizing high power supply voltage conversion includes an external power supply input terminal and a voltage output terminal, and is characterized in that it also includes a PMOS transistor 1, a PMOS transistor Tube two, NJFET withstand voltage tube one, NJFET withstand voltage tube two, NMOS tube one, NMOS tube two, depletion NMOS tube, diode, resistor one and resistor two, the source of PMOS tube one, PMOS tube two The source and the drain of the NMOS transistor 2 are connected to the input terminal of the external power supply, the drain of the PMOS transistor 1 is connected to its own gate, and connected to the gate of the PMOS transistor 2 and the drain of the NJFET withstand voltage transistor 1, and the PMOS transistor The drain of the second is connected to the drain of the NJFET voltage-resistant tube 2, and is connected to the gate of the NMOS tube 2 and the cathode of the diode, and the gate of the NJFET voltage-resistant tube 1 is connected to the gate of the NJFET voltage-resistant tube 2, and is grounded , the source of the NJFET voltage-resistant tube 1 is connected to the drain of the depletion-type NMOS tube, the source of the NJFET voltage-resistant tube 2 is connected to the drain of the NMOS tube 1, and the source and gate of the depletion-type NMOS tube are respectively grounded , the source of NMOS transistor 1 is grounded, its gate is connected to one end of resistor 1, and connected to one end of resistor 2, the other end of resistor 2 is grounded, the other end of resistor 1 is connected to the source of NMOS transistor 2, and connected to The anode of the diode is connected to the voltage output terminal.

Specifically, the first PMOS transistor and the second PMOS transistor are enhanced PMOS transistors; the first NMOS transistor and the second NMOS transistor are enhanced NMOS transistors.

The beneficial effect of the present invention is that, through the above-mentioned low-power low-dropout linear regulator that realizes high power supply voltage conversion, it can be seen that it avoids the use of error amplifiers and bandgap reference sources, the circuit structure is simple, the power consumption is small, and it can Realize the conversion of high voltage power supply.

Description of drawings

Fig. 1 is the circuit schematic diagram of traditional low-dropout linear regulator;

Fig. 2 is the schematic circuit diagram of the high supply voltage low power consumption low dropout linear regulator of the present invention;

Among them, A(S) is the error amplifier, ME1 is the first NMOS tube, MP is the second NMOS tube, V _OUT is the output voltage, BGR is the bandgap reference source, R1 is the first resistor, R2 is the second resistor, Cload is the capacitor, Rload Is the oscillation resistor, M3 is the first NJFET withstand voltage tube, M4 is the second NJFET withstand voltage tube, M1 is the first PMOS tube, M2 is the second PMOS tube, MD is the depletion NMOS tube, D1 is the diode, Vout is the output of the voltage output terminal Voltage.

detailed description

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

The low-power low-dropout linear regulator for realizing high power supply voltage conversion according to the present invention, its circuit schematic diagram is shown in Fig. Pressure tube one M3, NJFET withstand voltage tube two M4, NMOS tube one ME1, NMOS tube two MP, depletion NMOS tube MD, diode D1, resistor one R1 and resistor two R2, wherein the source of PMOS tube M1, The source of the PMOS transistor M2 and the drain of the NMOS transistor MP are connected to the input terminal of the external power supply, and the drain of the PMOS transistor M1 is connected to its own gate, and is connected to the gate of the PMOS transistor M2 and the NJFET voltage-resistant tube The drain of one M3 is connected, the drain of PMOS tube two M2 is connected with the drain of NJFET withstand voltage tube two M4, and is connected with the gate of NMOS tube two MP and the cathode of diode D1, the gate of NJFET withstand voltage tube one M3 The pole is connected to the gate of NJFET voltage-resistant tube 2 M4 and grounded, the source of NJFET voltage-resistant tube 1 M3 is connected to the drain of depletion-type NMOS tube MD, and the source of NJFET voltage-resistant tube 2 M4 is connected to NMOS tube 1 The drain of ME1 is connected, the source and gate of the depletion-type NMOS transistor MD are grounded respectively, the source of NMOS transistor ME1 is grounded, and its gate is connected to one end of resistor one R1 and one end of resistor two R2, The other end of the resistor 2 R2 is grounded, and the other end of the resistor 1 R1 is connected to the source of the NMOS transistor 2 MP, and connected to the anode of the diode D1 and the voltage output terminal.

Example

In the embodiment of the present invention, the low-power low-dropout linear regulator that realizes high power supply voltage conversion, its circuit schematic diagram is shown in Figure 2, including an external power supply input terminal, a voltage output terminal, a PMOS transistor M1, a PMOS transistor M2, and an NJFET. Pressure-resistant tube 1 M3, NJFET voltage-resistant tube 2 M4, NMOS tube 1 ME1, NMOS tube 2 MP, depletion NMOS tube MD, diode D1, resistor 1 R1 and resistor 2 R2, among them, the source of PMOS tube 1 M1 1. The source of the PMOS tube M2 and the drain of the NMOS tube MP are connected to the input terminal of the external power supply, and the drain of the PMOS tube M1 is connected to its own grid, and is connected to the gate of the PMOS tube M2 and the NJFET withstand voltage The drain of tube 1 M3 is connected, the drain of PMOS tube 2 M2 is connected to the drain of NJFET voltage-resistant tube 2 M4, and is connected to the gate of NMOS tube 2 MP and the cathode of diode D1, and the drain of NJFET voltage-resistant tube 1 M3 The gate is connected to the gate of the NJFET voltage-resistant tube 2 M4 and grounded, the source of the NJFET voltage-resistant tube 1 M3 is connected to the drain of the depletion-type NMOS tube MD, and the source of the NJFET voltage-resistant tube 2 M4 is connected to the NMOS tube The drain of a ME1 is connected, the source and gate of the depletion-type NMOS transistor MD are grounded respectively, the source of the NMOS transistor ME1 is grounded, and its gate is connected to one end of the resistor R1 and connected to one end of the resistor R2 , the other end of the resistor 2 R2 is grounded, the other end of the resistor 1 R1 is connected to the source of the NMOS transistor 2 MP, and connected to the anode of the diode D1 and the voltage output terminal.

When in use, the external voltage Vin is input to the input terminal of the external power supply, and the voltage output terminal outputs the voltage V _OUT . The first PMOS transistor and the second PMOS transistor may be enhanced PMOS transistors; the first NMOS transistor and the second NMOS transistor may also be enhanced NMOS transistors.

Its working principle is:

PMOS tube 1 M1, PMOS tube 2 M2, NMOS tube 1 ME1, NMOS tube 2 MP, depletion NMOS tube MD, NJFET voltage-resistant tube 1 M3 and NJFET voltage-resistant tube 2 M4 form the low-power low-dropout linear regulator The reference source in the device circuit structure, the NMOS tube and the MP tube are used as adjustment tubes, and the resistor one R1 and the resistor two R2 are voltage dividing resistors. The PMOS current mirror composed of PMOS tube one M1 and PMOS tube two M2 provides current for the two branches, so that the currents flowing through NMOS tube one ME1 and depletion NMOS tube MD are the same, and the NMOS tube one ME1 and the depletion NMOS tube MD are the same. The characteristics of the different threshold voltages of the tube MD generate a reference voltage; at the same time, the NJFET withstand voltage tube 2 M4, the NMOS tube 1 ME1 and the NMOS tube 2 MP form a feedback path. When the output voltage V _out decreases, the output voltage V _out is sampled The voltage division of the resistor R1 decreases, that is, the gate voltage of the NMOS tube ME1 decreases, the drain voltage increases, and the drain voltage of the NJFET withstand voltage tube M4 also increases, so that the current Ids of the series NMOS tube MP increases and the voltage Vds decreases , so that the output voltage V _out rises; on the contrary, when the output voltage V _out rises, the output voltage V _out rises through the divided voltage of the sampled resistor-R1, that is, the gate voltage of the NMOS tube-ME1 rises, and its As the drain voltage decreases, the drain voltage of the NJFET voltage-resistant tube 2 M4 also decreases, so that the current Ids of the series-connected NMOS tube 2 MP decreases and the voltage Vds increases, thereby reducing the output voltage V _out . Diode D1 protects the circuit. When the circuit is working normally, the diode D1 is not conducting. When the input external voltage Vin is turned off, the output voltage V _out is higher than the drain voltage of the NMOS tube 2 MP, the diode D1 is turned on, and the current is discharged to the ground through the diode D1, the NJFET withstand voltage tube 2 M4 and the NMOS tube 1 ME1 , Play the role of protecting the NMOS tube 2 MP (that is, the power tube).

Through the introduction of the above principles, the calculation process of the output voltage of the low-power low-dropout linear regulator that realizes high power supply voltage transition is as follows:

When the PMOS transistor M1 and the PMOS transistor M2 are matched in the current mirror, the current formula of the depletion-type NMOS transistor MD and the NMOS transistor ME1 is as follows:

Among them, μ _n represents the electron mobility; Co _x represents the capacitance of the gate oxide layer per unit area; with Respectively represent the width-to-length ratio of the depletion-type NMOS transistor MD and NMOS transistor-ME1; V _THMD and V _THME1 represent the threshold voltages of the depletion-type NMOS transistor MD and NMOS transistor-ME1 respectively; V _G represents the gate of the NMOS transistor-ME1 Voltage.

V _THME1 has a negative temperature coefficient, and |V _THMD | has a positive temperature coefficient. By adjusting the width-to-length ratio of the depletion-type NMOS transistor MD and the enhancement-type NMOS transistor-ME1, a temperature-independent reference voltage can be obtained.

The output voltage is then:

According to the above description, it can be proved that the low-power low-dropout linear regulator for realizing high power supply voltage conversion can use a small number of transistors to realize the conversion of high-voltage power supply and maintain low power consumption.

Claims (2)

1. A low-power low-dropout linear regulator that realizes high power supply voltage transitions, including an external power supply input terminal and a voltage output terminal, and is characterized in that it also includes a PMOS tube 1, a PMOS tube 2, an NJFET withstand voltage tube 1, and an NJFET withstand voltage Pressure tube two, NMOS tube one, NMOS tube two, depletion type NMOS tube, diode, resistor one and resistor two, the source of the PMOS tube one, the source of the PMOS tube two and the drain of the NMOS tube two are all connected to The drain of PMOS transistor 1 is connected to its own gate, and is connected to the gate of PMOS transistor 2 and the drain of NJFET withstand voltage transistor 1. The drain of PMOS transistor 2 is connected to the drain of NJFET withstand voltage transistor 2. The drain is connected to the gate of the NMOS transistor 2 and the cathode of the diode. The gate of the NJFET voltage-resistant transistor 1 is connected to the gate of the NJFET voltage-resistant transistor 2 and grounded. The source of the NJFET voltage-resistant transistor 1 is connected to the drain. The drain of the depletion-type NMOS tube is connected, the source of the NJFET withstand voltage tube 2 is connected to the drain of the NMOS tube 1, the source and gate of the depletion-type NMOS tube are grounded respectively, the source of the NMOS tube 1 is grounded, and the gate of the NMOS tube 1 is grounded. The pole is connected to one end of the resistor one, and is connected to one end of the resistor two, and the other end of the resistor two is grounded, and the other end of the resistor one is connected to the source of the NMOS transistor two, and is connected to the anode of the diode and the voltage output terminal. 2. the low-power low-dropout linear voltage regulator realizing high power supply voltage transition according to claim 1, characterized in that, the first PMOS transistor and the second PMOS transistor are enhanced PMOS transistors; the first NMOS transistor and the NMOS transistor The second is an enhanced NMOS tube.