CN107359787B

CN107359787B - A kind of gate driving circuit of adaptive dead zone time

Info

Publication number: CN107359787B
Application number: CN201710803690.8A
Authority: CN
Inventors: 周泽坤; 袁*东; 袁东; 石跃; 李登维; 石旺; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2017-09-08
Filing date: 2017-09-08
Publication date: 2019-04-12
Anticipated expiration: 2037-09-08
Also published as: CN107359787A

Abstract

A gate drive circuit with self-adaptive dead time belongs to the technical field of electronic circuits. It is suitable for switching power supply circuits, and the drive logic control circuit controls the cross-conduction of high- and low-end drives to realize the function of adaptive dead time; the level shift circuit lifts the control signal generated by the drive logic control circuit to the power rail of the high-end drive. ; The bootstrap circuit generates a high-side drive power rail by means of a charge pump; the first drive boost circuit and the second drive boost circuit boost the drive control signal to a gate drive signal with an ampere level; the power drive stage of the switching power supply circuit is connected The gate drive circuit generates the gate drive signal and generates the output voltage Vout. The invention can adaptively adjust the dead time according to the size of the power tube to avoid the occurrence of punch-through; the control method is simple, the purpose of self-adaptive dead time control is achieved with minimal cost, and the invention has extremely high versatility.

Description

A kind of gate driving circuit of adaptive dead zone time

Technical field

The invention belongs to electronic circuit technology fields, are related to the gate driving circuit of adaptive dead zone time a kind of.

Background technique

Using in the switching power circuit of synchronous rectification, unlatching when in order to guarantee upper down tube difference avoids wearing Logical damage circuit needs to be arranged during switch conversion dead time to protect circuit safety to work.

It is as shown in Figure 1 the gate driving circuit for switching power circuit, power drive grade packet in switching power circuit Switching tube M1, rectifying tube M2, inductance L and capacitor C are included, switching tube M1 and rectifying tube M2 are NMOS power tube, switching tube M1's Drain electrode connection input voltage vin, source electrode connect the drain electrode of rectifying tube M2 and connection switch node SW, and the source electrode of rectifying tube M2 connects Ground；Inductance L and capacitor C forms LC filter network, and series connection is attempted by between the drain electrode and source electrode of rectifying tube M2, series connection point conduct The output end of power drive grade in switching power circuit.The driving signal of switching tube M1 is switching tube gate drive signal HDRV, The driving signal of rectifying tube M2 is rectifying tube gate drive signal LDRV.

In order to guarantee the case where switching tube M1 and rectifying tube M2 are not simultaneously turned on, need in switching tube M1 and rectifying tube Dead time is set during two power tube switched conductives of M2.In Fig. 2, when two MOS power tubes simultaneously close off, electric current It can be by the body diode afterflow of low side power pipe rectifying tube M2, so that body diode be caused to be connected.

When switching tube M1 is turned off, and rectifying tube M2 is opened, into the synchronous rectification stage.η_CHIn the case of being opened for metal-oxide-semiconductor Efficiency, η_BDFor the efficiency in the case of body diode conducting, η is the average efficiency in synchronous rectification stage,

Assuming that the when a length of T of entire commutation phase, a length of KT is (when K is that body diode is connected when wherein body diode is connected The long accounting to entire commutation phase duration T, K < 1), then the efficiency calculation formula in available entire synchronous rectification stage.V_DS Conduction voltage drop when being opened for metal-oxide-semiconductor, V_FFor the forward conduction voltage drop of body diode.Due to V_DS<V_F, so η_CH>η_BD, to reduce Loss in efficiency needs to minimize η_BDBring influences, that is, reduces the size of K, the appearance for avoiding body diode from being connected.

Although traditional fixation dead time is relatively simple in design, however, to ensure that not occurring under all conditions The case where lower power tube break-through, needs the considerably long of dead time design inevitably resulting from the long period in this way Body diode conducting, increase power loss.Dead band time setting it is unreasonable be generate power loss the main reason for it One, in order to minimize influence of this body diode conducting to circuit performance, it is excellent to need to introduce adaptive dead zone time technology Change dead time, improves transfer efficiency.

Summary of the invention

The present invention is directed to design defect existing for fixed dead time, and proposing one kind can be with automatic adjusument dead time Driving circuit, when the factors such as power pipe size change, which can adaptively carry out the adjustment of dead time, To obtain optimal dead time, transfer efficiency is improved.

The technical scheme is that

A kind of gate driving circuit of adaptive dead zone time is suitable for switching power circuit, the switching power circuit Including switching tube M1 and rectifying tube M2, the source electrode of the switching tube M1 connects the drain electrode of the rectifying tube M2 and as switching node SW,

The gate driving circuit includes the first output end and second output terminal, and first output end exports high side gate Driving signal HDRV is for driving the switching tube M1, and the second output terminal output low side gate driving signal LDRV is for driving Move the rectifying tube M2；

The gate driving circuit includes driving logic control circuit, level shift circuit, the first driving enhancing circuit, the Two driving enhancing circuits and boostrap circuit,

The input terminal of the driving logic control circuit connects pulse-width modulation control signal PWM_Ctrl, the first control terminal Connecting the high side gate driving signal HDRV, the second control terminal connects the low side gate driving signal LDRV, and first Output end connects the input terminal of the level shift circuit, and second output terminal connects the input of the second driving enhancing circuit End；

The output end of the second driving enhancing circuit connects the second output terminal of the gate driving circuit；Described first The input terminal of driving enhancing circuit connects the output end of the level shift circuit, and output end connects the gate driving circuit The first output end；

The input terminal of the boostrap circuit connects the switching node SW, for generating the level shift circuit and first The power rail of driving enhancing circuit；

The driving logic control circuit include the first phase inverter INV1, the second phase inverter INV2, third phase inverter INV3, First NAND gate NAND1, the second NAND gate NAND2, the first RS latch RS1, the 2nd RS latch RS2, rectifying tube state prison Module Block_A and switching tube state monitoring module Block_B is surveyed,

The input terminal of first phase inverter INV1 connect the second phase inverter INV2 input terminal and the first NAND gate NAND1 the One input terminal and as it is described driving logic control circuit input terminal, output end connect the 2nd RS latch RS2 R input End；

The input terminal of third phase inverter INV3 connect the second phase inverter INV2 output end and the second NAND gate NAND2 the One input terminal, output end connect the R input of the first RS latch RS1；

Second control of the input terminal of rectifying tube state monitoring module Block_A as the driving logic control circuit End, output end connect the second input terminal of the first NAND gate NAND1；

First control of the input terminal of switching tube state monitoring module Block_B as the driving logic control circuit End, output end connect the second input terminal of the second NAND gate NAND2；

The S input terminal of first RS latch RS1 connects the output end of the first NAND gate NAND1, described in output end is used as The first output end output high-side driver of logic control circuit is driven to control signal H_Ctrl；

The S input terminal of 2nd RS latch RS2 connects the output end of the second NAND gate NAND2, described in output end is used as The second output terminal of logic control circuit is driven to export low side driving control signal L_Ctrl；

Rectifying tube state monitoring module Block_A includes first resistor R1, second resistance R2,3rd resistor R3 and first NMOS tube MN1,

First resistor R1 and second resistance R2 series connection, series connection point connect the grid of the first NMOS tube MN1, first resistor R1 Input terminal of the other end as the rectifying tube state monitoring module Block_A, the other end of second resistance R2 and first The source electrode of NMOS tube MN1 is grounded PGND；

A termination supply voltage VCC of 3rd resistor R3, the other end connect the drain electrode of the first NMOS tube MN1 and as described The output end of rectifying tube state monitoring module Block_A；

Switching tube state monitoring module Block_B includes the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th electricity R7, the 8th resistance R8, the 9th resistance R9, the first PMOS tube MP1, the second NMOS tube MN2 and third NMOS tube MN3 are hindered,

One end of 4th resistance R4 connects the grid of the first PMOS tube MP1 and one end of the 5th resistance R5, and the other end connects Connect the source electrode of the first PMOS tube MP1 and the input terminal as the switching tube state monitoring module Block_B；

The other end of 5th resistance R5 connects the switching node SW；

One end of 6th resistance R6 connects the drain electrode of the first PMOS tube MP1, and the other end connects the leakage of the second NMOS tube MN2 Pole；

7th resistance R7 and the 8th resistance R8 series connection, series connection point connect supply voltage VCC, the other end of the 7th resistance R7 The grid of the second NMOS tube MN2 is connected, the drain electrode of the other end connection third NMOS tube MN3 of the 8th resistance R8 is simultaneously opened as described Close the output end of pipe state monitoring module Block_B；

The grid of third NMOS tube MN3 connects the source electrode of the second NMOS tube MN2 and by being grounded PGND after the 9th resistance R9, Its source electrode is grounded PGND.

Specifically, the level shift circuit includes the 4th phase inverter INV4, the 5th phase inverter INV5, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, Ten NMOS tube MN10, the second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5 and the 6th PMOS tube MP6,

Input terminal of the input terminal of 4th phase inverter INV4 as the level shift circuit, output end connection the 5th are anti- The input terminal of phase device INV5 and the grid of the 5th NMOS tube MN5；

The grid of 4th NMOS tube MN4 connects the output end of the 5th phase inverter INV5, and source electrode connects the 5th NMOS tube MN5 Source electrode and the 7th NMOS tube MN7 drain electrode, the grid and drain electrode and third PMOS tube of the second PMOS tube MP2 of drain electrode connection The grid of MP3；

The grid of 6th NMOS tube MN6 connects bias current I_BIAS with the grid of its drain electrode and the 7th NMOS tube MN7；

The grid leak of 8th NMOS tube MN8 is shorted and connects drain electrode and the grid of the 9th NMOS tube MN9 of third PMOS tube MP3 Pole；

The grid leak of 4th PMOS tube MP4 is shorted and connects drain electrode and the grid of the 5th PMOS tube MP5 of the 5th NMOS tube MN5 Pole；

Drain electrode and the tenth NMOS of grid connection the 5th PMOS tube MP5 and the 9th NMOS tube MN9 of 6th PMOS tube MP6 The grid of pipe MN10, the drain electrode of the tenth NMOS tube MN10 of drain electrode connection and the output end as the level shift circuit；

Second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5 and the 6th PMOS tube The source electrode of MP6 connects the output end of the boostrap circuit；

The source electrode of 6th NMOS tube MN6 and the 7th NMOS tube MN7 is grounded PGND, the 8th NMOS tube MN8, the 9th NMOS tube The source electrode of MN9 and the tenth NMOS tube MN10 meet the switching node SW.

Specifically, the first PMOS tube MP1, the second NMOS tube MN2, the 4th NMOS tube MN4 and the 5th NMOS tube MN5 are Pressure pipe.

Specifically, the second driving enhancing circuit includes hex inverter INV6, the 7th phase inverter INV7, the 8th reverse phase Device INV8, the 9th phase inverter INV9, the tenth phase inverter INV10, the 11st phase inverter INV11, the first nor gate NOR1, third with NOT gate NAND1, the 11st NMOS tube MN11 and the 7th PMOS tube MP7,

The first input end of the first input end connection third NAND gate NAND1 of first nor gate NOR1 and as described the The input terminal of two driving enhancing circuits, the second input terminal connect the output end of the 11st phase inverter INV11, output end connection The input terminal of hex inverter INV6；

The output end of the input terminal connection hex inverter INV6 of 7th phase inverter INV7, output end connect the 8th reverse phase The grid of the input terminal of device INV8 and the 11st NMOS tube MN11；

The second input terminal of third NAND gate NAND3 connects the output end of the 8th phase inverter INV8, output end connection the The input terminal of nine phase inverter INV9；

The input terminal of tenth phase inverter INV10 connects the output end of the 9th phase inverter INV9, output end connection the 11st The grid of the input terminal of phase inverter INV11 and the 7th PMOS tube MP7；

The source electrode of 7th PMOS tube MP7 meets supply voltage VCC, and drain electrode connects the drain electrode of the 11st NMOS tube MN11 and work For the output end of the second driving enhancing circuit, the source electrode of the 11st NMOS tube MN11 is grounded PGND.

Specifically, the circuit structure of the first driving enhancing circuit and the second driving enhancing circuit is identical, described first The power rail of driving enhancing circuit is the power rail that the boostrap circuit generates, i.e., the 7th in the described first driving enhancing circuit The source electrode of PMOS tube MP7 meets the output end of the boostrap circuit, the 11st NMOS tube MN11 in the first driving enhancing circuit Source electrode connect the switching node.

The operation principle of the present invention is that: it drives logic control circuit control to realize that high low side drives cross-conduction, realizes certainly Adapt to the function of dead time；The control signal for driving logic control circuit to generate is raised to high-side driver by level shift circuit Power rail on；Boostrap circuit generates the power rail of high-side driver by way of charge pump；First driving enhancing circuit and the Driving control signal is enhanced to the gate drive signal with ampere levels by two driving enhancing circuits；The function of switching power circuit The gate drive signal of rate driving stage connection gate driving circuit generation simultaneously generates output voltage Vout.

The invention has the benefit that the present invention can adaptively adjust dead time according to the size of power tube, guarantee The appearance prevented punch-through；Control mode is simple, and the purpose of adaptive dead-time control is realized with minimum cost, has pole High versatility.

Detailed description of the invention

Fig. 1 is the gate driving circuit topological diagram of adaptive dead zone time proposed by the present invention.

Fig. 2 is the voltage change situation of switching node SW in power tube handoff procedure.

Fig. 3 is the circuit diagram that logic control circuit is driven in the present invention.

Fig. 4 is the circuit diagram of level shift circuit in embodiment.

Fig. 5 is the circuit diagram of driving enhancing circuit in embodiment.

Fig. 6 is the basic sequential logic figure in the present invention.

Specific embodiment

Present invention is further described in detail with specific embodiment with reference to the accompanying drawing.

The gate driving circuit of adaptive dead zone time proposed by the present invention, functional block diagram is as shown in Figure 1, be suitable for opening Powered-down source circuit, driving the input end signal of logic control circuit is pulse-width modulation control signal PWM_Ctrl, control terminal letter Number be high side gate driving signal HDRV and low side gate driving signal LDRV；Pulse-width modulation control signal PWM_Ctrl and high-end The open and close of gate drive signal HDRV co- controlling rectifying tube M2, pulse-width modulation control signal PWM_Ctrl and low side grid The open and close of pole driving signal LDRV co- controlling switching tube M1.

Specifically, as shown in figure 4, in driving logic control circuit, pulse-width modulation control signal PWM_Ctrl is low And high side gate driving signal HDRV, when being low, low side driving control signal L_Ctrl is that rectifying tube M2 is opened in high control；Pulsewidth When modulation control signal PWM_Ctrl is height and low side gate driving signal LDRV is low, high-side driver control signal H_Ctrl is Switching tube M1 is opened in height control.

Driving logic control circuit is key of the invention, the first PMOS tube MP1 in the present embodiment, the second NMOS tube MN2, 4th NMOS tube MN4 and the 5th NMOS tube MN5 is pressure pipe, needs to bear the maximum voltage difference between BST to PGND, rectifies tubulose State monitoring modular Block_A and switching tube state monitoring module Block_B monitors the unlatching of rectifying tube M2 and switching tube M1 respectively Closed state.

In rectifying tube state monitoring module Block_A, rectifying tube is closed from high to low in low side gate driving signal LDRV During M2, low side gate driving signal LDRV signal is followed by first by first resistor R1 and second resistance R2 partial pressure The grid of NMOS tube MN1, low side gate driving signal LDRV are continued to decline, and the first NMOS tube MN1 is progressively closed off, and pass through third electricity It hinders R3 to charge to rear class parasitic capacitance, the output of control rectifying tube state detection module Block_A is height, and mark rectifying tube M2 is closed Close completion；When low side gate driving signal LDRV by it is low get higher open rectifying tube M2 when, the first NMOS tube MN1 is gradually opened, control Rectifying tube state detection module Block_A output processed is low, mark rectifying tube M2 unlatching completion.

In switching tube state monitoring module Block_B, pipe is turned off the switch from high to low in high side gate driving signal HDRV During M1, high side gate driving signal HDRV is followed by the first PMOS tube by the 4th resistance R4 and the 5th resistance R5 partial pressure The grid of MP1, high side gate driving signal HDRV are continued to decline, and the first PMOS tube MP1 is progressively closed off, and electric current is gradually reduced, the The grid of two NMOS tube MN2 meets supply voltage VCC, so the second NMOS tube MN2 is normally opened, the electric current on the first PMOS tube MP1 exists Voltage is generated on 9th resistance R9, is added in the grid of third NMOS tube MN3, control third NMOS tube MN3 is progressively closed off, power supply electricity VCC is pressed to charge by the 8th resistance R8 to rear class parasitic capacitance, control switch pipe state monitoring module Block_B output is height, Sign switch pipe M1, which is closed, to be completed；High side gate driving signal HDRV by it is low get higher open switching tube M1 when, the first PMOS tube MP1 It gradually opens, while third NMOS tube MN3 is gradually opened, control switch pipe state monitoring module Block_B output is low, mark Switching tube M1, which is opened, to be completed.

Additionally by point of first resistor R1 and second resistance R2 in artificial adjustment rectifying tube state detection module Block_A The intrinsic standoff ratio and 3rd resistor R3 of 4th resistance R4 and the 5th resistance R5 in pressure ratio, switching tube state monitoring module Block_B Required dead time can be set with the size of the 8th resistance R8.

The state that rectifying tube M2 is closed, which is opened, from switching tube M1 is transformed into the entire of switching tube M1 closing rectifying tube M2 unlatching Process are as follows: original state, pulse-width modulation control signal PWM_Ctrl signal are height, and switching tube M1 opens rectifying tube M2 and closes, high Holding gate drive signal HDRV is height, and low side gate driving signal LDRV is low；State switching, pulse-width modulation control signal PWM_ Ctrl switchs to low, and one of the first NAND gate NAND1 input is low, so output is height, the S input of the first RS latch RS1 End for height, R input be it is low, output high-side driver control signal H_Ctrl be it is low, control turn off the switch pipe M1, pay attention to Rectifying tube state monitoring module Block_A does not monitor that high side gate driving signal HDRV control turns off the switch pipe M1 and completes it Before, the R input and S input terminal of the 2nd RS latch RS2 is all height, controls locked low side driving control signal L_Ctrl and is Low, an input terminal of the second NAND gate NAND2 switchs to low, the S of the 2nd RS latch RS2 after the completion of switching tube M1 closing Input terminal switchs to low, control unlatching rectifying tube M2.

The state for opening switching tube M1 closing from rectifying tube M2 is transformed into rectifying tube M2 and turns off the switch the entire of pipe M1 unlatching Process are as follows: original state, pulse-width modulation control signal PWM_Ctrl signal is low, rectifying tube M2 unlatching switching tube M1 closing, high Hold gate drive signal HDRV be it is low, low side gate driving signal LDRV be height；State switching, pulse-width modulation control signal PWM_ Ctrl switchs to height, and an input of the second NAND gate NAND2 is low, so its output is height, the S of the 2nd RS latch RS2 is defeated Enter end for height, R input be it is low, output low side driving control signal L_Ctrl be it is low, control close rectifying tube M2, pay attention to Do not monitor that high side gate driving signal HDRV control is closed rectifying tube M2 and completed in switching tube state monitoring module Block_B Before, the R input of the first RS latch RS1 and S input terminal are all high, control locked high-side driver control signal H_Ctrl and are Low, an input terminal of the first NAND gate NAND1 switchs to low, the S of the first RS latch RS1 after the completion of rectifying tube M2 closing Input terminal switchs to low, control unlatching switching tube M1.

Fig. 4 is the circuit diagram of level shift circuit in the present embodiment, including the 4th phase inverter INV4, the 5th phase inverter INV5, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, Nine NMOS tube MN9, the tenth NMOS tube MN10, the second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS Pipe MP5 and the 6th PMOS tube MP6, input terminal of the input terminal of the 4th phase inverter INV4 as the level shift circuit are defeated Outlet connects the input terminal of the 5th phase inverter INV5 and the grid of the 5th NMOS tube MN5；The grid connection the of 4th NMOS tube MN4 The output end of five phase inverter INV5, source electrode connect the drain electrode of the source electrode and the 7th NMOS tube MN7 of the 5th NMOS tube MN5, leakage The grid of the grid of the second PMOS tube MP2 of pole connection and drain electrode and third PMOS tube MP3；The grid of 6th NMOS tube MN6 and It drains and the grid of the 7th NMOS tube MN7 connects bias current I_BIAS；The grid leak of 8th NMOS tube MN8 is shorted and connects The drain electrode of third PMOS tube MP3 and the grid of the 9th NMOS tube MN9；The grid leak of 4th PMOS tube MP4 is shorted and connects the 5th The drain electrode of NMOS tube MN5 and the grid of the 5th PMOS tube MP5；The grid of 6th PMOS tube MP6 connects the 5th PMOS tube MP5 and the The drain electrode of nine NMOS tube MN9 and the grid of the tenth NMOS tube MN10, drain electrode connect the drain electrode of the tenth NMOS tube MN10 and work For the output end of the level shift circuit；Second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS The source electrode of pipe MP5 and the 6th PMOS tube MP6 connect the output end of the boostrap circuit；6th NMOS tube MN6 and the 7th NMOS tube The source electrode of the source electrode ground connection PGND, the 8th NMOS tube MN8, the 9th NMOS tube MN9 and the tenth NMOS tube MN10 of MN7 connect the switch Node SW.

The working principle of level shift circuit in the present embodiment are as follows: when input signal, that is, high-side driver controls signal H_ Ctrl be it is low, i.e. when PGND, the 4th NMOS tube MN4 shutdown and the 5th NMOS tube MN5 is opened, the biasing introduced at this time by current mirror Electric current all flows through the 5th NMOS tube MN5, although the 5th PMOS tube MP5 unlatching at this time works due to not having electric current to flow through Deep linear zone, output signal H_Ctrl_h are low, i.e. switching node SW；When input signal H_Ctrl is height, i.e. when VCC, the 4th NMOS tube MN4 is opened and the 5th NMOS tube MN5 is turned off, the electric current being made of at this time the 6th NMOS tube MN6 and the 7th NMOS tube MN7 The bias current that mirror introduces all flows through the 4th NMOS tube MN4, although the 9th NMOS tube MN9 is opened due to not having electric current at this time It flows through and works in deep linear zone, output signal H_Ctrl_h is height, that is, the power rail BST after booting.In this way, being achieved that letter Number conversion of the power rail from VCC-GND to BST-SW.

Fig. 5 is the circuit diagram of the second driving enhancing circuit in the present embodiment, including hex inverter INV6, the 7th are instead Phase device INV7, the 8th phase inverter INV8, the 9th phase inverter INV9, the tenth phase inverter INV10, the 11st phase inverter INV11, first Nor gate NOR1, third NAND gate NAND1, the 11st NMOS tube MN11 and the 7th PMOS tube MP7, the of the first nor gate NOR1 One input terminal connects the first input end of third NAND gate NAND1 and the input terminal as the second driving enhancing circuit, Second input terminal connects the output end of the 11st phase inverter INV11, and output end connects the input terminal of hex inverter INV6；The The output end of the input terminal connection hex inverter INV6 of seven phase inverter INV7, output end connect the defeated of the 8th phase inverter INV8 Enter end and the grid of the 11st NMOS tube MN11；The second input terminal of third NAND gate NAND3 connects the 8th phase inverter INV8's Output end, output end connect the input terminal of the 9th phase inverter INV9；The input terminal of tenth phase inverter INV10 connects the 9th reverse phase The output end of device INV9, output end connect the input terminal of the 11st phase inverter INV11 and the grid of the 7th PMOS tube MP7；The The source electrode of seven PMOS tube MP7 meets supply voltage VCC, and drain electrode connects the drain electrode of the 11st NMOS tube MN11 and as described second The output end of driving enhancing circuit, the source electrode of the 11st NMOS tube MN11 are grounded PGND.

First driving enhancing circuit is also identical structure, and only power rail is different, the power rail of the first driving enhancing circuit For BST-SW, i.e., the source electrode that the first driving enhances the 7th PMOS tube MP7 in circuit meets the output end of boostrap circuit, the 11st NMOS The source electrode of pipe MN11 meets switching node SW.

Below by taking the second driving enhancing circuit as an example, the second driving enhancing circuit shown in fig. 5 mainly realizes two functions: It is driven firstly, being made up of hex inverter INV6, the 7th phase inverter INV7 and the 9th phase inverter INV9, the tenth phase inverter INV10 Dynamic chain, enhances driving capability step by step, so that the 11st NMOS tube MN11 and the 7th PMOS tube MP7 of larger size are respectively driven, And then the electric current of ampere levels is provided by the 11st NMOS tube MN11 and the 7th PMOS tube MP7, to drive external power pipe That is rectifying tube M2；Secondly as the 11st NMOS tube MN11 and the 7th PMOS tube MP7 provide the electric current of ampere levels, need Dead time is set to protect circuit, is controlled by ring logic, realizes fixed dead time, with the pass the 7th PMOS tube MP7 Break to the 11st NMOS tube MN11 open between dead zone for, when original state, input signal L_Ctrl is height, controls NG point (i.e. the grid signal of the 11st NMOS tube MN11) is the 11st NMOS tube MN11 of low closing, and PG point be (i.e. the 7th PMOS tube MP7's Grid signal) it is low unlatching PG point, input signal L_Ctrl switchs to low at this time, and the voltage of control PG point is overturn immediately as height, pass PG point is closed, and NG point then needs until the overturning of PG point is high can just overturn later to be high, and then opens the 11st NMOS tube MN11, To realize dead time.

Fig. 6 is basic logic control chart of the invention.Should be apparent that from logic control chart switching tube M1 with The mutual control planning of rectifying tube M2 state, the i.e. unlatching of the closing control switch pipe M1 of rectifying tube M2, the closing of switching tube M1 The unlatching of rectifying tube M2 is controlled, to form a dead time between the movement that mutual control is completed, guarantees that two pipes are different Shi Kaiqi prevents break-through from damaging circuit.

It is of the invention it is critical that power tube discharge time is elongated when the size of power tube changes, but due to setting The state grid voltage of judgement shutdown, the variation of discharge time will not influence the length of dead time, to realize oneself The purpose of adjustment is adapted to, and can realize artificial adjustment dead time by the way that the size of resistance is simply provided.

Those skilled in the art disclosed the technical disclosures can make various do not depart from originally according to the present invention Various other specific variations and combinations of essence are invented, these variations and combinations are still within the scope of the present invention.

Claims

1. An adaptive dead-time gate drive circuit, suitable for a switching power supply circuit, the switching power supply circuit comprising a switch tube (M1) and a rectifier tube (M2), and the source of the switch tube (M1) is connected to The drain of the rectifier (M2) serves as a switch node (SW),

The gate drive circuit includes a first output end and a second output end, the first output end outputs a high-side gate drive signal (HDRV) for driving the switch tube (M1), and the second output end outputs A low-side gate drive signal (LDRV) is used to drive the rectifier (M2);

The gate drive circuit includes a drive logic control circuit, a level shift circuit, a first drive enhancement circuit, a second drive enhancement circuit and a bootstrap circuit,

The input end of the drive logic control circuit is connected to the pulse width modulation control signal (PWM_Ctrl), the first control end thereof is connected to the high-side gate drive signal (HDRV), and the second control end of the drive logic control circuit is connected to the low-side gate drive signal (LDRV), the first output terminal of which is connected to the input terminal of the level shift circuit, and the second output terminal of which is connected to the input terminal of the second driving enhancement circuit;

The output end of the second drive enhancement circuit is connected to the second output end of the gate drive circuit; the input end of the first drive enhancement circuit is connected to the output end of the level shift circuit, and its output end is connected to the a first output terminal of the gate drive circuit;

An input end of the bootstrap circuit is connected to the switch node (SW) for generating a power rail of the level shift circuit and the first driving enhancement circuit;

It is characterized in that, the drive logic control circuit includes a first inverter (INV1), a second inverter (INV2), a third inverter (INV3), a first NAND gate (NAND1), a second AND Not gate (NAND2), first RS latch (RS1), second RS latch (RS2), rectifier tube state monitoring module (Block_A) and switch tube state monitoring module (Block_B),

The input end of the first inverter (INV1) is connected to the input end of the second inverter (INV2) and the first input end of the first NAND gate (NAND1) and serves as the input end of the driving logic control circuit, which The output end is connected to the R input end of the second RS latch (RS2);

The input end of the third inverter (INV3) is connected to the output end of the second inverter (INV2) and the first input end of the second NAND gate (NAND2), and its output end is connected to the first RS latch (RS1) ) of the R input;

The input end of the rectifier tube state monitoring module (Block_A) is used as the second control end of the driving logic control circuit, and the output end thereof is connected to the second input end of the first NAND gate (NAND1);

The input end of the switch tube state monitoring module (Block_B) is used as the first control end of the drive logic control circuit, and its output end is connected to the second input end of the second NAND gate (NAND2);

The S input end of the first RS latch (RS1) is connected to the output end of the first NAND gate (NAND1), and its output end is used as the first output end of the drive logic control circuit to output a high-end drive control signal (H_Ctrl);

The S input end of the second RS latch (RS2) is connected to the output end of the second NAND gate (NAND2), and its output end serves as the second output end of the drive logic control circuit to output a low-side drive control signal (L_Ctrl) ;

The rectifier tube state monitoring module (Block_A) includes a first resistor (R1), a second resistor (R2), a third resistor (R3) and a first NMOS tube (MN1),

The first resistor (R1) and the second resistor (R2) are connected in series, and the series point is connected to the gate of the first NMOS transistor (MN1), and the other end of the first resistor (R1) serves as the rectifier tube state monitoring module (Block_A) , the other end of the second resistor (R2) and the source of the first NMOS transistor (MN1) are grounded (PGND);

One end of the third resistor (R3) is connected to the power supply voltage (VCC), and the other end is connected to the drain of the first NMOS transistor (MN1) and used as the output end of the rectifier tube state monitoring module (Block_A);

The switch tube state monitoring module (Block_B) includes a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), an eighth resistor (R8), and a ninth resistor (R9) , the first PMOS transistor (MP1), the second NMOS transistor (MN2) and the third NMOS transistor (MN3),

One end of the fourth resistor (R4) is connected to the gate of the first PMOS transistor (MP1) and one end of the fifth resistor (R5), and the other end is connected to the source of the first PMOS transistor (MP1) and serves as the state of the switch The input terminal of the monitoring module (Block_B);

The other end of the fifth resistor (R5) is connected to the switch node (SW);

One end of the sixth resistor (R6) is connected to the drain of the first PMOS transistor (MP1), and the other end of the sixth resistor (R6) is connected to the drain of the second NMOS transistor (MN2);

The seventh resistor (R7) and the eighth resistor (R8) are connected in series, the series point is connected to the power supply voltage (VCC), the other end of the seventh resistor (R7) is connected to the gate of the second NMOS transistor (MN2), and the eighth resistor ( The other end of R8) is connected to the drain of the third NMOS transistor (MN3) and used as the output end of the switch state monitoring module (Block_B);

The gate of the third NMOS transistor (MN3) is connected to the source of the second NMOS transistor (MN2) and is grounded (PGND) through a ninth resistor (R9), and its source is grounded (PGND).

2 . The gate drive circuit with adaptive dead time according to claim 1 , wherein the level shift circuit comprises a fourth inverter (INV4), a fifth inverter (INV5), a fourth inverter (INV5), Four NMOS transistors (MN4), fifth NMOS transistor (MN5), sixth NMOS transistor (MN6), seventh NMOS transistor (MN7), eighth NMOS transistor (MN8), ninth NMOS transistor (MN9), tenth NMOS transistor tube (MN10), the second PMOS tube (MP2), the third PMOS tube (MP3), the fourth PMOS tube (MP4), the fifth PMOS tube (MP5) and the sixth PMOS tube (MP6),

The input end of the fourth inverter (INV4) is used as the input end of the level shift circuit, and the output end thereof is connected to the input end of the fifth inverter (INV5) and the gate of the fifth NMOS transistor (MN5);

The gate of the fourth NMOS transistor (MN4) is connected to the output end of the fifth inverter (INV5), and the source of the fourth NMOS transistor (MN5) is connected to the source of the fifth NMOS transistor (MN5) and the drain of the seventh NMOS transistor (MN7). The drain is connected to the gate and drain of the second PMOS transistor (MP2) and the gate of the third PMOS transistor (MP3);

The gate and drain of the sixth NMOS transistor (MN6) and the gate of the seventh NMOS transistor (MN7) are connected to the bias current (I_BIAS);

The gate-drain of the eighth NMOS transistor (MN8) is short-circuited and connected to the drain of the third PMOS transistor (MP3) and the gate of the ninth NMOS transistor (MN9);

The gate-drain of the fourth PMOS transistor (MP4) is short-circuited and connected to the drain of the fifth NMOS transistor (MN5) and the gate of the fifth PMOS transistor (MP5);

The gate of the sixth PMOS transistor (MP6) is connected to the drains of the fifth PMOS transistor (MP5) and the ninth NMOS transistor (MN9) and the gate of the tenth NMOS transistor (MN10), the drain of which is connected to the tenth NMOS transistor ( The drain of MN10) is used as the output terminal of the level shift circuit;

The sources of the second PMOS transistor (MP2), the third PMOS transistor (MP3), the fourth PMOS transistor (MP4), the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are connected to the output of the bootstrap circuit end;

The sources of the sixth NMOS transistor (MN6) and the seventh NMOS transistor (MN7) are grounded (PGND), and the sources of the eighth NMOS transistor (MN8), the ninth NMOS transistor (MN9) and the tenth NMOS transistor (MN10) are connected to the source. the switch node (SW).

3. The gate drive circuit with adaptive dead time according to claim 2, wherein the first PMOS transistor (MP1), the second NMOS transistor (MN2), the fourth NMOS transistor (MN4) and The fifth NMOS tube (MN5) is a pressure-resistant tube.

4 . The gate driving circuit with adaptive dead time according to claim 1 , wherein the second driving enhancement circuit comprises a sixth inverter (INV6), a seventh inverter (INV7), Eighth inverter (INV8), ninth inverter (INV9), tenth inverter (INV10), eleventh inverter (INV11), first NOR gate (NOR1), third NAND gate (NAND1), eleventh NMOS transistor (MN11) and seventh PMOS transistor (MP7),

The first input terminal of the first NOR gate (NOR1) is connected to the first input terminal of the third NAND gate (NAND1) and is used as the input terminal of the second driving enhancement circuit, and the second input terminal thereof is connected to the eleventh inverter. the output end of the inverter (INV11), the output end of which is connected to the input end of the sixth inverter (INV6);

The input end of the seventh inverter (INV7) is connected to the output end of the sixth inverter (INV6), and its output end is connected to the input end of the eighth inverter (INV8) and the gate of the eleventh NMOS transistor (MN11). pole;

The second input end of the third NAND gate (NAND3) is connected to the output end of the eighth inverter (INV8), and its output end is connected to the input end of the ninth inverter (INV9);

The input end of the tenth inverter (INV10) is connected to the output end of the ninth inverter (INV9), and the output end thereof is connected to the input end of the eleventh inverter (INV11) and the gate of the seventh PMOS transistor (MP7). pole;

The source of the seventh PMOS transistor (MP7) is connected to the power supply voltage (VCC), and the drain of the seventh PMOS transistor (MP7) is connected to the drain of the eleventh NMOS transistor (MN11) and is used as the output end of the second driving enhancement circuit. The eleventh NMOS transistor The source of (MN11) is grounded (PGND).

5 . The gate driving circuit with adaptive dead time according to claim 4 , wherein the first driving enhancement circuit and the second driving enhancement circuit have the same circuit structure, and the first driving enhancement circuit has the same circuit structure. 6 . The power rail is the power rail generated by the bootstrap circuit, that is, the source of the seventh PMOS transistor (MP7) in the first drive enhancement circuit is connected to the output end of the bootstrap circuit. The source of the eleventh NMOS transistor (MN11) is connected to the switch node.