CN108494234A - Floating power supply rail suitable for GaN high speed gate drive circuits - Google Patents

Abstract

Suitable for the floating power supply rail of GaN high speed gate drive circuits, belong to technical field of power management.The present invention can be realized using the design of double floating power supply rails while meet GaN device for power switching and work in safe voltage and turned the floating power supply rail that high voltage level shift circuit possesses enough dynamic ranges with low pressure；High pressure turns low voltage level shift circuit, voltage clamp circuit, logic control circuit and the first floating power supply rail generation circuit and constitutes closed loop; for generating power rails of the first power rail BST as the buffer circuit in GaN high speed gate drive circuits, GaN device for power switching gate source voltages can be protected to be operated in safe range；Second floating power supply rail generation circuit constitutes open loop, turns the power rail of high voltage level shift circuit for generating second source rail BSTA as the low pressure in GaN high speed gate drive circuits, it can be ensured with enough dynamic ranges.

Description

Floating Power Rail for GaN High Speed Gate Drive Circuits

technical field

The invention belongs to the technical field of power management, and in particular relates to a floating power rail suitable for a GaN high-speed gate drive circuit.

Background technique

With the development of power electronics in recent years, half-bridge drive circuits are developing towards high power and high frequency, which also brings new requirements to the selection of power tubes and circuit design. Traditional half-bridge drive circuits mainly use silicon power transistors as the power stage. In contrast, GaN power switch devices (such as GaN HEMT) have good physical characteristics such as high voltage resistance and no reverse recovery time, so GaN power switches are used. The half-bridge gate drive circuit of the device has excellent characteristics such as high speed and high power density. However, when an enhanced GaN power switching device (GaN HEMT is used as an example below) is used as the power tube of the half-bridge gate drive circuit, the following phenomena will occur, so that the traditional high-speed and high-power gate drive circuit suitable for Si power tubes cannot be used for enhancement type GaN power switching devices.

Figure 1 is a schematic diagram of the structure of an enhanced GaN power switching device applied to a half-bridge gate drive. In the figure ① indicates that due to the external load pumping, there is a situation where the bias voltage V _SW of the power stage is negative; in the figure ② Indicates that due to the low gate-source withstand voltage of the enhanced GaN power switching device, the voltage difference V _BST -V _SW between the upper and lower plates of the bootstrap capacitor C _boot must be clamped within the safe operating range in the circuit; The voltage difference V _BST -V _SW between the upper and lower plates of capacitor C _boot is clamped, and the BST voltage will decrease as SW enters negative pressure due to the capacitive coupling effect of C _boot in the dead time period, resulting in a level shift from low voltage to high voltage The dynamic range of the circuit (Level Up) is not enough; ④ in the figure indicates that the power rail of the low-voltage to high-voltage level shift circuit (Level Up) is BST and VSS, and the amplitude of the driving signal after the level shift is V _BST -V _SS ＝V _Cboot -|V _SW | will be reduced due to the pressure difference between the upper and lower plates of Cboot V _Cboot is clamped and SW enters negative pressure; the above four situations will lead to two consequences: first, low voltage turns high The dynamic range of the piezoelectric level shift circuit (Level Up) is not enough, which makes the speed of the level shift slower, and no longer meets the requirements of high-speed gate drive for transmission delay. The low-voltage to high-voltage level shift circuit (Level Up) in Figure 2 For example, the reduction of the floating power rail voltage V _BST makes the gate-source voltage V _GS of the power transistors M1 and M2 in the low-voltage to high-voltage level shift circuit smaller, and the low-voltage to high-voltage level shift circuit pulls up the output node And the pull-down ability becomes weaker, resulting in slower level shifting speed; second, the power rails of the logic circuit in the subsequent stage of the low-voltage to high-voltage level shift circuit (Level Up) are BST and SW, and the low-voltage to high-voltage level shift The power rails of the circuit (Level Up) are BST and VSS, and the reference grounds of the two are different, so the amplitude of the driving signal after level shifting is V _BST -V _SS =V _Cboot -|V _SW | When the value is small, it will gradually fail to touch the threshold level V _T of the logic of the subsequent stage, and eventually the problem of loss of the driving signal will occur.

When the GaN HEMT (GaN high electron mobility transistor) in Figure 1 is in the off state, when the current flows from the source terminal to the drain terminal, the drain-source voltage V _DS will have a negative voltage of -2~-3V, so in the half-bridge In the gate drive circuit, when the GaN HEMT is used as the lower power transistor, the bias voltage V _SW of the power stage is negative due to the load pumping of the external load during the dead time, and the higher the load current, the more serious the negative voltage situation; In the traditional design scheme of the bootstrap capacitor power supply module, the floating power supply rail BST is powered by the low-voltage power supply rail V _DD , which causes the upper plate of the bootstrap capacitor C _boot to be charged when the bootstrap capacitor C _boot is charged during the dead time. The bootstrap diode is clamped at the V _DD potential, and the voltage difference across the capacitor can reach up to (V _DD +3)V; however, since the gate-source breakdown voltage of the GaN HEMT is small (requires V _GS <6V, the optimal driving voltage is not If the voltage exceeds 5.5V), the upper power tube will easily break down due to the large voltage difference between the two ends of the bootstrap capacitor when it is turned on.

Therefore, in some bridge drive circuit designs, a clamping circuit must be added to the bootstrap capacitor charging path to clamp the voltage difference V _BST -V _SW between the upper and lower plates of the bootstrap capacitor C _boot , so as to prevent the upper power tube from being charged due to excessive gate-source voltage. Large and GaN tube dielectric layer breakdown occurs. However, because the voltage difference V _BST -V _SW between the upper and lower plates of the bootstrap capacitor C _boot is clamped within 5.5V to ensure safe operation, and the power stage bias voltage V _SW has a large negative value during the dead time, the self- Due to the coupling effect of the capacitor C _boot , the level of the floating power supply rail BST will follow the power stage bias voltage V _SW into a negative voltage and be much lower than 5V, which brings new problems: 1. Make the power tube control circuit connected to the bridge The dynamic range of the low-voltage to high-voltage level shift circuit (Level Up) of the low-voltage logic circuit is not enough (the power rail of the low-voltage to high-voltage level-shift circuit is generally a floating power rail BST and chip ground), resulting in low-voltage to high-voltage level The response speed of the displacement circuit (Level Up) does not meet the high-speed requirements, and the transmission delay of the driving signal increases; 2. The threshold level of the subsequent logic circuit will be synchronized with the potential of the floating power rail BST and the low-voltage power rail SW during the dead time At the same time, due to the reduction of the dynamic range of the low-voltage to high-voltage level shift circuit (Level Up), the amplitude of the driving signal after passing the level shift will decrease. These two phenomena will cause the input signal to be inconsistent during transmission. A signal loss occurs due to recognition by the subsequent logic circuit. The above problems have brought difficulties to the design of high-speed and high-power half-bridge gate drive circuits suitable for GaN power switching devices, making it difficult to implement GaN power switching devices that can work within a safe voltage and low-voltage to high-voltage level shift circuits ( Level Up) floating rail with sufficient dynamic range.

Contents of the invention

In view of the above shortcomings, the present invention proposes a floating power rail suitable for GaN high-speed and high-power half-bridge gate drive circuits. Under the premise of ensuring that the voltage difference between the upper and lower plates of the bootstrap capacitor C _boot is clamped within a safe voltage, The present invention adopts a double floating power supply rail generation circuit to supply power to the GaN half-bridge gate drive circuit, which eliminates the energy of the upper power tube dielectric layer caused by applying the traditional gate drive floating power supply rail generation circuit suitable for Si power tubes to GaN power switching devices. The negative problems of being breakdown and driving signal transmission delay increase or even loss.

Technical scheme of the present invention is:

Floating power rails suitable for GaN high-speed gate drive circuits, including high-voltage to low-voltage level shift circuits, voltage clamping circuits, logic control circuits, first floating power rail generation circuits and second floating power rail generation circuits,

The second floating power rail generation circuit includes a first diode D ₁ , a second diode D ₂ and a bootstrap capacitor C _boot , the anode of the first diode D ₁ is connected to the power supply voltage V _DD , and the cathode is connected to The cathode of the second diode _D2 and generates the second floating power rail BSTA; the upper plate of the bootstrap capacitor _Cboot is connected to the anode of the second diode _D2 and the output terminal of the first floating power rail generation circuit , the lower plate of which is connected to the half-bridge switch node SW of the GaN high-speed gate drive circuit;

The two input terminals of the voltage clamping circuit are respectively connected to the upper plate and the lower plate of the bootstrap capacitor C _boot , for detecting the voltage difference between the upper and lower plates of the bootstrap capacitor C _boot and outputting the first control Signal Ctrl1 to the input end of the high-voltage to low-voltage level shift circuit;

The high-voltage to low-voltage level shift circuit transfers the first control signal Ctrl1 to a low-voltage power rail, outputs a first logic control signal LV1 and a second logic control signal LV2, and connects the two input terminals of the logic control circuit;

The logic control circuit generates a second control signal Ctrl2 according to the first logic control signal LV1 and the second logic control signal LV2 and connects the input end of the first floating power rail generation circuit;

The first floating power supply rail generation circuit is used to generate the first floating power supply rail BST.

Specifically, it is characterized in that the GaN high-speed gate drive circuit includes a buffer circuit and a low-voltage to high-voltage level shift circuit, and the power rail of the buffer circuit is the first floating power rail BST and the half-bridge switch node power rail SW, The power rails of the low-voltage to high-voltage level shifting circuit are the second floating power rail BSTA and the half-bridge switching node power rail SW.

Specifically, the first floating power supply rail generating circuit includes a low-voltage switch tube PM0, a bootstrap diode D _BOOT , a first resistor R1, an NPN transistor, a Zener tube Zener, and a second resistor R2,

The gate of the low-voltage switching tube PM0 is used as the input terminal of the first floating power rail generating circuit to connect to the second control signal Ctrl2, and its source is connected to one end of the first resistor R1, the collector of the NPN transistor and the Zener tube The cathode of Zener is connected to the power supply voltage VDD, and its drain is connected to the other end of the first resistor R1, the emitter of the NPN transistor and the anode of the bootstrap diode D _BOOT ;

The base of the NPN triode is connected to the anode of the Zener tube and connected to the anode of the bootstrap diode D _BOOT through the second resistor R2, and the cathode of the bootstrap diode D _BOOT is used as the output terminal of the first floating power rail generating circuit to output the first A floating supply rail BST.

Specifically, the logic control circuit includes a latch protection module, an RS latch module and a buffer,

The latch protection module includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, and a sixth inverter INV6. One NAND gate NAND1 and the second NAND gate NAND2,

The input terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2 and connected to the second logic control signal LV2, and its output terminal is connected to the first input terminal of the first NAND gate NAND1; the third inverter The input terminal of the device INV3 is connected to the output terminal of the second inverter INV2, and its output terminal is connected to the first input terminal of the second NAND gate NAND2;

The input terminal of the sixth inverter INV6 is connected to the input terminal of the fourth inverter INV4 and connected to the first logic control signal LV1, and its output terminal is connected to the second input terminal of the second NAND gate NAND2; the fifth inverter The input terminal of the device INV5 is connected to the output terminal of the fourth inverter INV4, and its output terminal is connected to the second input terminal of the first NAND gate NAND1;

The RS latch includes a third NAND gate NAND3 and a fourth NAND gate NAND4, the first input end of the third NAND gate NAND3 is connected to the output end of the first NAND gate NAND1, and the second The output terminal is connected to the output terminal of the fourth NAND gate NAND4, and its output terminal is connected to the first input terminal of the fourth NAND gate NAND4 and the input terminal of the buffer; the second input terminal of the fourth NAND gate NAND4 is connected to the The output terminal of the second NAND gate NAND2 is described above, and the output terminal of the buffer is used as the output terminal of the logic control circuit to output the second control signal Ctrl2.

Specifically, the voltage clamping circuit includes a seventh inverter INV7, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first triode Q1, a Diode transistor Q2, first NMOS transistor NM1, second NMOS transistor NM2, third NMOS transistor NM3, fourth NMOS transistor NM4, fifth NMOS transistor NM5, sixth NMOS transistor NM6, seventh NMOS transistor NM7, first PMOS transistor PM1, second PMOS transistor PM2, third PMOS transistor PM3 and fourth PMOS transistor PM4;

The input end of the seventh inverter INV7 is connected to the gates of the fourth PMOS transistor PM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6, and the drains of the third PMOS transistor PM3 and the fourth NMOS transistor NM4, and its output end is connected to the gate of the first PMOS transistor PM1;

The gate of the first NMOS transistor NM1 is connected to the gate and drain of the second NMOS transistor NM2 and the collector of the first triode Q1, and its drain is connected to the gate and drain of the second PMOS transistor PM2 and the third PMOS The gate of the transistor PM3, the source of which is connected to the sources of the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4 and the sixth NMOS transistor NM6 and is connected as the first input terminal of the voltage clamping circuit The voltage V _SW at the half-bridge switch node of the GaN high-speed gate drive circuit;

The third resistor R3 is connected between the source and drain of the first PMOS transistor PM1, the fourth resistor R4 and the fifth resistor R5 are connected in series and connected between the drain of the first PMOS transistor PM1 and the source of the first NMOS transistor NM1 Between, the series point connects the bases of the first triode Q1 and the second triode Q2;

The sixth resistor R6 and the seventh resistor R7 are connected in series between the source of the first PMOS transistor PM1 and the emitter of the first transistor Q1, and the series connection point is connected to the emitter of the second transistor Q2;

The gate-drain of the third NMOS transistor NM3 is short-circuited and connected to the collector of the second transistor Q2 and the gate of the fourth NMOS transistor NM4;

The gate of the seventh NMOS transistor NM7 is connected to the drains of the fourth PMOS transistor PM4 and the fifth NMOS transistor NM5 as the output terminal of the voltage clamping circuit, and its source is connected to the source of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM5. The drain of the NMOS transistor NM6 is connected to the sources of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 and serves as the second input terminal of the voltage clamping circuit Connect to the voltage V _BST of the first floating supply rail.

Specifically, the high-voltage to low-voltage level shift circuit includes an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, and a tenth NMOS transistor. NM10, eleventh NMOS transistor NM11, twelfth NMOS transistor NH1, thirteenth NMOS transistor NH2, fifth PMOS transistor PM5, sixth PMOS transistor PM6, seventh PMOS transistor PM7, eighth PMOS transistor PM8, ninth PMOS transistor Tube PH1, tenth PMOS tube PH2, third triode Q3 and fourth triode Q4, the power rail of the high-voltage to low-voltage level shift circuit is the second floating power rail BSTA and the half-bridge switching node power rail SW ;

The gate of the eighth NMOS transistor NM8 is connected to the input end of the eighth inverter INV8 and serves as the input end of the high voltage to low voltage level shift circuit, and its drain is connected to the drain electrode of the fifth PMOS transistor PM5 and the sixth PMOS transistor The gate of PM6, its source is connected to the source of the ninth NMOS transistor NM9 and the voltage V _SW at the half-bridge switch node of the GaN high-speed gate drive circuit;

The gate of the ninth NMOS transistor NM9 is connected to the output terminal of the eighth inverter INV8, and its drain is connected to the gate of the fifth PMOS transistor PM5, the drain of the sixth PMOS transistor PM6, and the input terminal of the ninth inverter INV9 ;

The gate of the seventh PMOS transistor PM7 is connected to the output terminal of the ninth inverter INV9 and the input terminal of the tenth inverter INV10, its drain is connected to the source of the ninth PMOS transistor PH1, and its source is connected to the fifth PMOS transistor The sources of PM5, the sixth PMOS transistor PM6 and the eighth PMOS transistor PM8 are connected to the voltage V _BSTA of the second floating power supply rail;

The gate of the eighth PMOS transistor PM8 is connected to the output terminal of the tenth inverter INV10, and the drain thereof is connected to the source of the tenth PMOS transistor PH2;

The gate of the ninth PMOS transistor PH1 is connected to the gate of the tenth PMOS transistor PH2, and the drain thereof is connected to the drain of the twelfth NMOS transistor NH1;

The gate of the thirteenth NMOS transistor NH2 is connected to the gate of the twelfth NMOS transistor NH1, its drain is connected to the drain of the tenth PMOS transistor PH2, and its source is connected to the base and collector of the fourth transistor Q4, The gate of the tenth NMOS transistor NM10 and the drain of the eleventh NMOS transistor NM11 output the second logic control signal LV2; the emitter of the fourth triode Q4 is connected to the power supply voltage V _DD ;

The emitter of the third transistor Q3 is connected to the power supply voltage V _DD , its base is connected to the collector and connected to the source of the twelfth NMOS transistor NH1 , the drain of the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 The gate outputs the first logic control signal LV1; the sources of the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 are grounded.

The beneficial effects of the present invention are: the power supply rail provided by the present invention adopts the design of double floating power supply rails, which can realize the floating of the GaN power switching device working in a safe voltage and the low-voltage to high-voltage level shift circuit having a sufficient dynamic range. Power rail; the first floating power rail BST generated by the bootstrap capacitor Cboot voltage difference clamp protection is used as the power rail of the buffer circuit in the GaN high-speed gate drive circuit, which can protect the gate-source voltage of the GaN power switching device within a safe range ; The second floating power rail BSTA that is not protected by the voltage difference clamp of the bootstrap capacitor C _boot is used as the power rail of the low-voltage to high-voltage level shifting circuit in the GaN high-speed gate drive circuit, which can ensure that it has sufficient dynamic range .

Description of drawings

FIG. 1 is a schematic structural diagram of applying an enhancement mode GaN power switching device to a half-bridge gate driver in the prior art.

FIG. 2 is a schematic structural diagram of a floating power rail suitable for a GaN high-speed gate drive circuit in an embodiment.

FIG. 3 is a specific implementation manner of the voltage clamping circuit and the high voltage to low voltage level shift circuit Level Down in the embodiment.

FIG. 4 is a typical application topology construction method of applying the present invention to a high-speed gate driver IC in an embodiment.

Detailed ways

The technical scheme of the present invention is described in detail below in conjunction with accompanying drawing and specific embodiment:

The floating power rail suitable for the GaN high-speed gate drive circuit proposed by the present invention adopts the design of double floating power rails, and the high-voltage to low-voltage level shift circuit, the voltage clamping circuit, the logic control circuit and the first floating power rail generation circuit form a closed loop. It is used to generate the first power rail BST; the two floating power rail generating circuits form an open loop and is used to generate the second power rail BSTA.

The power rails of the snubber circuit in the GaN high-speed gate drive circuit are the first floating power rail BST and the half-bridge switching node power rail SW protected by the voltage difference clamp of the bootstrap capacitor Cboot, which can protect the gate-source voltage of the GaN power switching device working at Within the safe range; the power rail of the low-voltage to high-voltage level shift circuit is the second floating power rail BSTA and the half-bridge switching node power rail SW that are not clamped by the voltage difference clamp of the bootstrap capacitor C _boot , which can ensure that it has sufficient Dynamic Range.

As shown in Figure 2, an implementation of the first floating power rail generation circuit and logic control circuit is shown. The first floating power rail generation circuit has an active clamp protection function and an initialization power-on function, including a low-voltage switch tube PM0, The bootstrap diode D _BOOT , the first resistor R1, the NPN transistor, the Zener tube Zener and the second resistor R2, wherein the first resistor R1 is an initialization unit, and the NPN transistor, the Zener tube Zener and the second resistor R2 form an active clamping unit; the gate of the low-voltage switching tube PM0 is connected to the second control signal Ctrl2 as the input end of the first floating power supply rail generating circuit, and its source is connected to one end of the first resistor R1 and the collector of the NPN transistor and the cathode of the Zener tube Zener are connected to the power supply voltage V _DD , and its drain is connected to the other end of the first resistor R1, the emitter of the NPN transistor and the anode of the bootstrap diode D _BOOT ; the base of the NPN transistor is connected to the Zener The anode of the tube is connected to the anode of the bootstrap diode D _BOOT through the second resistor R2, and the cathode of the bootstrap diode D _BOOT is used as the output terminal of the first floating power rail generating circuit to output the first floating power rail BST.

The logic control circuit includes a latch protection module, an RS latch module and a buffer, and the latch protection module includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4, the fifth inverter INV5, the sixth inverter INV6, the first NAND gate NAND1 and the second NAND gate NAND2, the input end of the first inverter INV1 is connected to the input end of the second inverter INV2 and Connect the second logic control signal LV2, its output terminal is connected to the first input terminal of the first NAND gate NAND1; the input terminal of the third inverter INV3 is connected to the output terminal of the second inverter INV2, and its output terminal is connected to The first input terminal of the second NAND gate NAND2; the input terminal of the sixth inverter INV6 is connected to the input terminal of the fourth inverter INV4 and connected to the first logic control signal LV1, and its output terminal is connected to the second NAND The second input end of the gate NAND2; the input end of the fifth inverter INV5 is connected to the output end of the fourth inverter INV4, and its output end is connected to the second input end of the first NAND gate NAND1; the RS latch Including a third NAND gate NAND3 and a fourth NAND gate NAND4, the first input terminal of the third NAND gate NAND3 is connected to the output terminal of the first NAND gate NAND1, and its second output terminal is connected to the fourth NAND gate NAND4. The output end of NOT gate NAND4, its output end connects the first input end of the 4th NAND gate NAND4 and the input end of described buffer; The second input end of the 4th NAND gate NAND4 connects described second NAND gate The output terminal of NAND2 and the output terminal of the buffer are used as the output terminal of the logic control circuit to output the second control signal Ctrl2.

As shown in Figure 3, it is an implementation of the voltage clamping circuit and the high-voltage to low-voltage level shift circuit (Level Down). The voltage clamping circuit includes a seventh inverter INV7, a third resistor R3, a fourth resistor R4, Fifth resistor R5, sixth resistor R6, seventh resistor R7, first transistor Q1, second transistor Q2, first NMOS transistor NM1, second NMOS transistor NM2, third NMOS transistor NM3, fourth NMOS transistor Tube NM4, fifth NMOS tube NM5, sixth NMOS tube NM6, seventh NMOS tube NM7, first PMOS tube PM1, second PMOS tube PM2, third PMOS tube PM3, and fourth PMOS tube PM4; seventh inverter The input end of INV7 is connected to the gates of the fourth PMOS transistor PM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6, and the drains of the third PMOS transistor PM3 and the fourth NMOS transistor NM4, and its output end is connected to the first PMOS transistor PM1. The gate of the first NMOS transistor NM1 is connected to the gate and drain of the second NMOS transistor NM2 and the collector of the first triode Q1, and its drain is connected to the gate and drain of the second PMOS transistor PM2 And the gate of the third PMOS transistor PM3, the source of which is connected to the sources of the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4 and the sixth NMOS transistor NM6 and serves as the first voltage clamping circuit One input terminal is connected to the voltage V _SW at the half-bridge switch node of the GaN high-speed gate drive circuit; the third resistor R3 is connected between the source and drain of the first PMOS transistor PM1, the fourth resistor R4 and the fifth resistor R5 is connected in series and parallel between the drain of the first PMOS transistor PM1 and the source of the first NMOS transistor NM1, and its series point is connected to the bases of the first transistor Q1 and the second transistor Q2; the sixth resistor R6 It is connected in series with the seventh resistor R7 between the source of the first PMOS transistor PM1 and the emitter of the first transistor Q1, and its series connection point is connected with the emitter of the second transistor Q2; the gate of the third NMOS transistor NM3 The drain is short-circuited and connected to the collector of the second triode Q2 and the gate of the fourth NMOS transistor NM4; the gate of the seventh NMOS transistor NM7 is connected to the drains of the fourth PMOS transistor PM4 and the fifth NMOS transistor NM5 as the The output end of the voltage clamping circuit, its source is connected to the source of the fifth NMOS transistor NM5 and the drain of the sixth NMOS transistor NM6, and its drain is connected to the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor The sources of the transistor PM3 and the fourth PMOS transistor PM4 are connected to the voltage V _BST of the first floating power supply rail as the second input terminal of the voltage clamping circuit.

The voltage clamping circuit is mainly composed of a bandgap reference circuit and a current comparator. The first triode Q1 and the second triode Q2 constitute the reference core, and the bootstrap capacitor C _boot upper and lower plates BST-SW are collected through the voltage dividing resistor composed of the third resistor R3, the fourth resistor R4 and the fifth resistor R5 The voltage information of the first triode Q1 and the base area of the second triode Q2 are input into the base area of the first triode Q1 and the second triode Q2. Since the transconductance of the road where the first triode Q1 and the second triode Q2 are located is different, the reference core passes through The currents mirrored by the first triode Q1 and the second triode Q2 to the current comparator are inconsistent, and when the voltage difference of BST-SW is different, the first control signal Ctrl1 output by the voltage clamping circuit will be high or is low.

The high-voltage to low-voltage level shift circuit includes an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, and an eleventh NMOS transistor NM10. NMOS transistor NM11, twelfth NMOS transistor NH1, thirteenth NMOS transistor NH2, fifth PMOS transistor PM5, sixth PMOS transistor PM6, seventh PMOS transistor PM7, eighth PMOS transistor PM8, ninth PMOS transistor PH1, tenth PMOS transistor PMOS transistor PH2, third triode Q3 and fourth triode Q4, the power rail of the high-voltage to low-voltage level shift circuit is the second floating power rail BSTA and the half-bridge switch node power rail SW; the eighth NMOS transistor The gate of NM8 is connected to the input terminal of the eighth inverter INV8 and serves as the input terminal of the high-voltage to low-voltage level shift circuit, and its drain is connected to the drain of the fifth PMOS transistor PM5 and the gate of the sixth PMOS transistor PM6 , the source of which is connected to the source of the ninth NMOS transistor NM9 and the voltage V _SW at the half-bridge switch node of the GaN high-speed gate drive circuit; the gate of the ninth NMOS transistor NM9 is connected to the output terminal of the eighth inverter INV8 , the drain of which is connected to the gate of the fifth PMOS transistor PM5, the drain of the sixth PMOS transistor PM6 and the input terminal of the ninth inverter INV9; the gate of the seventh PMOS transistor PM7 is connected to the output of the ninth inverter INV9 terminal and the input terminal of the tenth inverter INV10, its drain is connected to the source of the ninth PMOS transistor PH1, its source is connected to the sources of the fifth PMOS transistor PM5, the sixth PMOS transistor PM6 and the eighth PMOS transistor PM8 and connected to the voltage V _BSTA of the second floating power rail; the gate of the eighth PMOS transistor PM8 is connected to the output terminal of the tenth inverter INV10, and its drain is connected to the source of the tenth PMOS transistor PH2; the ninth PMOS transistor PH1 The gate of the 10th PMOS transistor PH2 is connected to the gate of the tenth PMOS transistor PH2, and its drain is connected to the drain of the twelfth NMOS transistor NH1; the gate of the thirteenth NMOS transistor NH2 is connected to the gate of the twelfth NMOS transistor NH1, and its drain It is connected to the drain of the tenth PMOS transistor PH2, its source is connected to the base and collector of the fourth triode Q4, the gate of the tenth NMOS transistor NM10 and the drain of the eleventh NMOS transistor NM11 and outputs the first Two logic control signals LV2; the emitter of the fourth transistor Q4 is connected to the power supply voltage V _DD ; the emitter of the third transistor Q3 is connected to the power supply voltage V _DD , and its base is connected to the collector and connected to the twelfth NMOS transistor The source of NH1, the drain of the tenth NMOS transistor NM10 and the gate of the eleventh NMOS transistor NM11 output the first logic control signal LV1; the sources of the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 are grounded .

The working principle of the generation of the first power rail BST is as follows: the voltage clamping circuit is used for real-time voltage detection of the voltage difference V _BST -V _SW between the upper and lower plates of the bootstrap capacitor C _boot and generates the first control signal Ctrl1, from high voltage to low voltage The level shift circuit (Level Down) transfers the first control signal Ctrl1 to the low-voltage power supply rail for logic control, generates the first logic control signal LV1 and the second logic control signal LV2, and inputs the logic control circuit, and the logic control circuit generates the second control signal Ctrl2 controls the low-voltage switch PM0 between the positive terminal of the bootstrap diode D _BOOT and the low-voltage power rail V _DD in the first floating power rail generating circuit.

When detecting the voltage undervoltage on the bootstrap capacitor C _boot , the power supply voltage V _DD charges the bootstrap capacitor C _boot through the bootstrap diode D _BOOT ; when detecting the voltage overvoltage on the bootstrap capacitor C _boot , disconnect The charging path from the power supply voltage V _DD to the bootstrap capacitor C _boot . The first control signal Ctrl1 output by the voltage clamping circuit is transferred to the low voltage power supply rail through the high voltage to low voltage level shift circuit (LevelDown), and the second control signal Ctrl2 is output to control the logic control circuit. The truth table of the logic control circuit is shown below, where A represents the input signal of the first inverter INV1, B represents the input signal of the second inverter INV2, Set represents the output signal of the first NAND gate NAND1, and Reset represents The output signal of the second NAND gate NAND2, Q represents the output signal of the third NAND gate NAND3:

This logic design can make the RS latch in the logic control circuit still work normally under the influence of the common mode noise of the SW node.

A low-voltage switch PM0 is inserted between the positive terminal of the bootstrap diode D _BOOT and the bias of the V _DD power supply. When the voltage clamp circuit detects that the voltage difference BST-SW between the upper and lower plates of the bootstrap capacitor C _boot is overvoltage, the output The first control signal Ctrl1 is transferred to the low-voltage rail through the high-voltage to low-voltage level shift circuit (Level Down), which is used as the input of the logic control circuit; the output signal of the logic control circuit is controlled by the first control signal Ctrl1, and the second control signal Ctrl2 is generated quickly Turn off the low-voltage switch tube PM0 to disconnect the charging path from the power supply voltage V _DD to the bootstrap capacitor C _boot ; when the front-stage circuit detects that the voltage difference BST-SW between the upper and lower plates of the bootstrap capacitor C _boot is undervoltage, The logic control circuit outputs the second control signal Ctrl2 to turn on the low-voltage switching tube PM0, and the charging path is equivalent to the bootstrap charging path in which the bootstrap diode D _BOOT is cascaded with the _bootstrap capacitor C boot. When the upper transistor of the GaN high-speed gate drive circuit is turned off , after the half-bridge switch node SW voltage drops to the ground potential VSS and below, the charging branch is turned on and starts to charge the bootstrap capacitor C _boot .

The above workflow realizes the detection of the level at both ends of the bootstrap capacitor C _boot and the controlled charging process of the bootstrap capacitor C _boot . However, due to the access of the low-voltage switch tube PM0, when the low-voltage switch tube PM0 is turned off, its body diode and the bootstrap diode D _BOOT form a pair of back-to-back diode pairs, resulting in the V _A node (that is, the anode of the bootstrap diode D _BOOT ) It becomes a high-impedance node, which will make: 1. When the entire driver chip is powered on, the bootstrap capacitor C _boot to the power supply voltage V _DD is a high-impedance path, and it cannot be powered on normally; 2. After the entire driver chip works normally, the power tube quickly On and off, the dv/dt common-mode noise crosstalk of the first floating power rail BST is very severe, and the high-impedance node V _A is easily disturbed, affecting the normal operation of the circuit. Therefore, in the first floating power supply rail generation circuit, a large resistor, that is, the first resistor R1, is connected to initialize the bootstrap capacitor C _boot , so that the BST-SW reaches the working voltage; the Zener tube Zener, the second resistor R2 and the NPN transistor form An active clamping circuit is used to charge the V _A node, and the body diode of the low-voltage switching tube PM0 constitutes an active discharge path to discharge the V _A node, offsetting the dv/dt common-mode noise of the first floating power rail BST on the V _A node voltage crosstalk.

In the first floating power rail generation circuit, the working principle of the active clamp circuit is as follows: When the level at the first floating power rail BST drops rapidly, the V _A node is crosstalked to a very low voltage by negative dv/dt, and the Zener The tube Zenar reversely breaks down, and the resulting voltage drop causes the base and collector of the NPN transistor to be reverse-biased; at the same time, the current flowing through the second resistor R2 causes a voltage drop between the base and emitter regions of the NPN transistor, and the BE junction is positive Bias, the NPN transistor base region is turned on; at this time, the active clamping path is turned on, and there is

In the above formula, k is the Boltzmann constant, T is the ambient temperature, kT=26mV at room temperature, β is the amplification factor of the NPN transistor, I _Zenar and I _R2 are the currents flowing through the Zener tube Zenar and the second resistor R2 , (I _Zenar -I _R2 ) represents the current flowing into the base of the NPN transistor, and I _E is the collector current of the NPN transistor, which charges the V _A node when the active clamp path is turned on, offsetting the dv/ dt Crosstalk of common-mode noise on the voltage at the V _A node.

As shown in FIG. 1 , it is a schematic diagram of the second floating power rail generating circuit that can meet the high-speed and reliable transmission of driving signals provided by the present invention, including the first diode D1, the second diode D2 and the bootstrap capacitor C _boot , and the first The anode of a diode D1 is connected to the supply voltage V _DD , and its cathode is connected to the cathode of the second diode D2 and generates a second floating power supply rail BSTA; the upper plate of the bootstrap capacitor is connected to the anode of the second diode D2 and The output end of the first floating power rail generation circuit, the lower plate of which is connected to the half-bridge switch node SW of the GaN high-speed gate drive circuit.

In the turn-on stage of the upper transistor, the second diode D2 is forward-conducting, and the first diode D1 is turned off. At this time

V _BST - V _D2 = V _BSTA

Wherein V _D2 is the forward voltage drop of the second diode D2 when it is turned on.

In the dead time period when the upper transistor is turned off and the lower transistor is turned on, since the level of the first power rail BST will drop to 2V at the lowest level, at this time the second diode D2 is turned off, and the first diode D1 is turned on. The resulting potential of the second floating supply rail BSTA is provided by the supply voltage V _DD

V _BSTA = VDD-V _D1

Wherein V _D1 is the forward voltage drop of the first diode D1 when it is turned on.

The preferred implementation of the first diode D1 and the second diode D2 is as follows: D1 is a high-voltage diode, and its negative terminal to positive terminal needs to ensure the withstand voltage of Vin+VDD during bootstrap; D2 is a low-voltage diode, and its The withstand voltage from the negative terminal to the positive terminal will not exceed the negative voltage value of SW |V _SW |, but the negative terminal and the positive terminal must ensure the withstand voltage of Vin+VDD to the substrate. This method saves the most chip area and parasitic parameters. The smallest, the fastest circuit response.

FIG. 4 is a typical application topology construction of the present invention applied to a GaN high-speed gate driver IC. Among them, the voltage clamping circuit, the high-voltage to low-voltage level shift circuit (Level Down), the logic control circuit and the first floating power rail generation circuit jointly realize the functions of bootstrap charging and power supply to the gate drive circuit. Aiming at the problem that the potential at the first floating power rail BST drops to an excessively low level due to the source-drain negative pressure phenomenon of the GaN power switching device during the dead time, the present invention designs a power supply with a level range from BSTA to SW rail to supply power to the low-voltage to high-voltage level shift circuit (LevelUp) in the half-bridge gate drive circuit, because the level of the second power rail BSTA is not affected by the negative source-drain voltage of the GaN power switching device during the dead time The dynamic range of the low-voltage to high-voltage level shift circuit (Level Up) is guaranteed, and the traditional low-voltage to high-voltage level shift circuit (Level Up) and driving logic circuit can be applied to GaN high-speed gate drive applications.

Aiming at the physical characteristics of the enhanced GaN power switching device, the present invention designs a power supply scheme with double floating power rails, which eliminates the negative impact of the enhanced GaN power switching device on the work of the half-bridge gate drive circuit under high-speed and high-power applications. It is worth noting that the system control method and specific circuit design used in the present invention can also be applied to the driving circuits of Si power switching devices and other wide bandgap semiconductor switching devices (such as SiC power switching devices), specifically, for Si In the gate drive circuit of the power switching device, the body diode of the power transistor freewheels during the dead time, and the SW node voltage will drop to a negative voltage of -0.7V during the dead time. The present invention is also applicable to this application.

Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (6)

1. the floating power supply rail suitable for GaN high speed gate drive circuits, which is characterized in that turn low voltage level displacement electricity including high pressure Road, voltage clamp circuit, logic control circuit, the first floating power supply rail generation circuit and the second floating power supply rail generation circuit,

The second floating power supply rail generation circuit includes the first diode (D₁), the second diode (D₂) and bootstrap capacitor (C_boot), the first diode (D₁) anode connection supply voltage (V_DD), cathode connects the second diode (D₂) cathode and production Raw second floating power supply rail (BSTA)；Bootstrap capacitor (C_boot) top crown connect the second diode (D₂) anode and described The output end of first floating power supply rail generation circuit, bottom crown connect the half-bridge switch section of the GaN high speeds gate drive circuit Point (SW)；

Two input terminals of the voltage clamp circuit are separately connected the bootstrap capacitor (C_boot) top crown and bottom crown, use In the detection bootstrap capacitor (C_boot) polar plate voltage up and down difference and export first control signal (Ctrl1) to the high pressure turn The input terminal of low voltage level shift circuit；

The high pressure turns low voltage level shift circuit and the first control signal (Ctrl1) is gone to low-tension supply rail, output the One logic control signal (LV1) and the second logic control signal (LV2) and two input terminals for connecting the logic control circuit；

The logic control circuit is generated according to first logic control signal (LV1) and the second logic control signal (LV2) Second control signal (Ctrl2) and the input terminal for connecting the first floating power supply rail generation circuit；

The first floating power supply rail generation circuit is for generating the first floating power supply rail (BST).

2. the floating power supply rail according to claim 1 suitable for GaN high speed gate drive circuits, which is characterized in that described GaN high speed gate drive circuits include buffer circuit and low pressure turns high voltage level shift circuit, and the power rail of the buffer circuit is First floating power supply rail (BST) and half-bridge switch node power rail (SW), the low pressure turn the power supply of high voltage level shift circuit Rail is the second floating power supply rail (BSTA) and half-bridge switch node power rail (SW).

3. the floating power supply rail according to claim 1 suitable for GaN high speed gate drive circuits, which is characterized in that described First floating power supply rail generation circuit includes low tension switch pipe (PM0), bootstrap diode (D_BOOT), first resistor (R1), NPN type Triode, Zener (Zener) and second resistance (R2),

Input terminal connection second control of the grid of low tension switch pipe (PM0) as the first floating power supply rail generation circuit Signal (Ctrl2) processed, one end of source electrode connection first resistor (R1), the collector and Zener (Zener) of NPN type triode Cathode and connect supply voltage (VDD), drain electrode connection first resistor (R1) the other end, NPN type triode emitter With bootstrap diode (D_BOOT) anode；

The anode of the base stage connection Zener of NPN type triode simultaneously connects bootstrap diode (D afterwards by second resistance (R2)_BOOT) Anode, bootstrap diode (D_BOOT) cathode it is floating as the output end output first of the first floating power supply rail generation circuit Dynamic power rail (BST).

4. the floating power supply rail according to claim 1 suitable for GaN high speed gate drive circuits, which is characterized in that described Logic control circuit includes latch up protection module, RS latch modules and buffer,

The latch up protection module includes the first phase inverter (INV1), the second phase inverter (INV2), third phase inverter (INV3), the Four phase inverters (INV4), the 5th phase inverter (INV5), hex inverter (INV6), the first NAND gate (NAND1) and second with it is non- Door (NAND2),

The input terminal of first phase inverter (INV1) connects the input terminal of the second phase inverter (INV2) and connects the second logic control Signal (LV2) processed, output end connect the first input end of the first NAND gate (NAND1)；The input of third phase inverter (INV3) The output end of end the second phase inverter of connection (INV2), output end connect the first input end of the second NAND gate (NAND2)；

The input terminal of hex inverter (INV6) connects the input terminal of the 4th phase inverter (INV4) and connects the first logic control Signal (LV1) processed, output end connect the second input terminal of the second NAND gate (NAND2)；The input of 5th phase inverter (INV5) The output end of the 4th phase inverter (INV4) of end connection, output end connect the second input terminal of the first NAND gate (NAND1)；

The RS latch includes third NAND gate (NAND3) and the 4th NAND gate (NAND4), the third NAND gate (NAND3) first input end connects the output end of first NAND gate (NAND1), second output terminal connection the 4th with it is non- The output end of door (NAND4), output end connect the input of the first input end and the buffer of the 4th NAND gate (NAND4) End；Second input terminal of the 4th NAND gate (NAND4) connects the output end of second NAND gate (NAND2), buffer it is defeated Output end output second control signal (Ctrl2) of the outlet as the logic control circuit.

5. the floating power supply rail according to claim 1 suitable for GaN high speed gate drive circuits, which is characterized in that described Voltage clamp circuit includes the 7th phase inverter (INV7), 3rd resistor (R3), the 4th resistance (R4), the 5th resistance (R5), the 6th Resistance (R6), the 7th resistance (R7), the first triode (Q1), the second triode (Q2), the first NMOS tube (NM1), the 2nd NMOS Manage (NM2), third NMOS tube (NM3), the 4th NMOS tube (NM4), the 5th NMOS tube (NM5), the 6th NMOS tube (NM6), the 7th NMOS tube (NM7), the first PMOS tube (PM1), the second PMOS tube (PM2), third PMOS tube (PM3) and the 4th PMOS tube (PM4)；

The input terminal of 7th phase inverter (INV7) connects the 4th PMOS tube (PM4), the 5th NMOS tube (NM5) and the 6th NMOS tube (NM6) drain electrode of grid and third PMOS tube (PM3) and the 4th NMOS tube (NM4), output end connect the first PMOS tube (PM1) grid；

The grid of first NMOS tube (NM1) connects the grid and drain electrode and the first triode (Q1) of the second NMOS tube (NM2) Collector, the grid and the grid of drain electrode and third PMOS tube (PM3) of drain electrode the second PMOS tube of connection (PM2), source electrode Connect the source electrode of the second NMOS tube (NM2), third NMOS tube (NM3), the 4th NMOS tube (NM4) and the 6th NMOS tube (NM6) simultaneously First input end as the voltage clamp circuit connects the electricity at the half-bridge switch node of the GaN high speeds gate drive circuit Press (V_SW)；

3rd resistor (R3) is connected between the source electrode and drain electrode of the first PMOS tube (PM1), the 4th resistance (R4) and the 5th resistance (R5) series connection is attempted by between the drain electrode of the first PMOS tube (PM1) and the source electrode of the first NMOS tube (NM1), series connection point connection the The base stage of one triode (Q1) and the second triode (Q2)；

6th resistance (R6) and the 7th resistance (R7) connect and connect the source electrode and the first triode (Q1) of the first PMOS tube (PM1) Emitter between, series connection point connect the second triode (Q2) emitter；

The grid leak short circuit of third NMOS tube (NM3) and the collector and the 4th NMOS tube (NM4) for connecting the second triode (Q2) Grid；

The grid of 7th NMOS tube (NM7) connects the drain electrode of the 4th PMOS tube (PM4) and the 5th NMOS tube (NM5) and as described The output end of voltage clamp circuit, source electrode connect the drain electrode of the source electrode and the 6th NMOS tube (NM6) of the 5th NMOS tube (NM5), Its drain the first PMOS tube of connection (PM1), the second PMOS tube (PM2), third PMOS tube (PM3) and the 4th PMOS tube (PM4) Source electrode and the second input terminal as the voltage clamp circuit connect the voltage (V of the first floating power supply rail_BST)。

6. the floating power supply rail according to claim 1 suitable for GaN high speed gate drive circuits, which is characterized in that described It includes the 8th phase inverter (INV8), the 9th phase inverter (INV9), the tenth phase inverter that high pressure, which turns low voltage level shift circuit, (INV10), the 8th NMOS tube (NM8), the 9th NMOS tube (NM9), the tenth NMOS tube (NM10), the 11st NMOS tube (NM11), 12nd NMOS tube (NH1), the 13rd NMOS tube (NH2), the 5th PMOS tube (PM5), the 6th PMOS tube (PM6), the 7th PMOS Manage (PM7), the 8th PMOS tube (PM8), the 9th PMOS tube (PH1), the tenth PMOS tube (PH2), third transistor (Q3) and the 4th Triode (Q4), the power rail that the high pressure turns low voltage level shift circuit are the second floating power supply rail (BSTA) and half-bridge switch Node power rail (SW)；

The grid of 8th NMOS tube (NM8) connects the input terminal of the 8th phase inverter (INV8) and turns low voltage level as the high pressure The input terminal of shift circuit, the grid of the drain electrode and the 6th PMOS tube (PM6) of drain electrode the 5th PMOS tube (PM5) of connection, source Pole connects the voltage (V at the source electrode of the 9th NMOS tube (NM9) and the half-bridge switch node of the GaN high speeds gate drive circuit_SW)；

The grid of 9th NMOS tube (NM9) connects the output end of the 8th phase inverter (INV8), drain electrode the 5th PMOS tube of connection (PM5) input terminal of the drain electrode and the 9th phase inverter (INV9) of grid, the 6th PMOS tube (PM6)；

The grid of 7th PMOS tube (PM7) connect the 9th phase inverter (INV9) output end and the tenth phase inverter (INV10) it is defeated Enter end, the source electrode of drain electrode the 9th PMOS tube (PH1) of connection, source electrode connects the 5th PMOS tube (PM5), the 6th PMOS tube (PM6) and the source electrode of the 8th PMOS tube (PM8) and the voltage (V for connecting the second floating power supply rail_BSTA)；

The grid of 8th PMOS tube (PM8) connects the output end of the tenth phase inverter (INV10), drain electrode the tenth PMOS tube of connection (PH2) source electrode；

The grid of 9th PMOS tube (PH1) connects the grid of the tenth PMOS tube (PH2), drain electrode the 12nd NMOS tube of connection (NH1) drain electrode；

The grid of 13rd NMOS tube (NH2) connects the grid of the 12nd NMOS tube (NH1), drain electrode the tenth PMOS tube of connection (PH2) drain electrode, source electrode connect the 4th triode (Q4) base stage and collector, the tenth NMOS tube (NM10) grid and The drain electrode of 11st NMOS tube (NM11) simultaneously exports second logic control signal (LV2)；The transmitting of 4th triode (Q4) Pole connects supply voltage (V_DD)；

The emitter connection supply voltage (V of third transistor (Q3)_DD), base stage is connected with collector and connects the 12nd NMOS It manages source electrode, the drain electrode of the tenth NMOS tube (NM10) and the grid of the 11st NMOS tube (NM11) of (NH1) and exports described first Logic control signal (LV1)；The source electrode of tenth NMOS tube (NM10) and the 11st NMOS tube (NM11) is grounded.