CN113659813B - Driving circuit - Google Patents

Abstract

The present application provides a driving circuit, comprising: a signal processing unit and a main circuit; the signal processing unit is used for generating driving signals with different driving capacities and time sequences based on the control signals of the driving circuit, and applying each driving signal to a corresponding MOS tube in the main circuit; when the control signal changes under the action of each driving signal, the main circuit generates corresponding transient compensation so that the output current of the main circuit reaches a preset value within preset time and no overshoot or low current phenomenon occurs; the pull-up tube and the pull-down tube of the main circuit are controlled to be not conducted simultaneously through time sequence.

Description

a driving circuit

Technical field

The present invention belongs to the technical field of power electronics, and more specifically, relates to a driving circuit.

Background technique

Referring to Figure 1, it shows a driving circuit provided by the prior art; in this driving circuit: the reference current Iref is directly connected to the drain end and gate end of the MOS transistor MP1, the gate end of the MOS transistor MP2, and the gate end of the MOS transistor MP4. terminal; at the same time, the MOS tube MN7 is connected in series with the MOS tube MP2 between the low-voltage power supply VDD and the ground, and the MOS tube MP5 is connected in series with the MOS tube MP4 between the low-voltage power supply VDD and the ground. The two MOS tubes The gate terminals receive the signals (g1 and g2 shown in Figure 1) after the control signals of the drive circuit pass through the corresponding inverters (INV1 and INV2 as shown in Figure 1). MOS tubes MP_HV2, MN_HV4, and MN6 are connected in series between the high-voltage power supply and ground.

In the structure shown in Figure 1, when the control signal changes between on and off, the output current of the drive circuit has an overshoot or low current phenomenon. Secondly, the pull-up tube MP_HV2 and the pull-down tubes MN_HV4 and MN6 may appear at the same time. to conduction, causing great power loss.

Contents of the invention

In view of this, the object of the present invention is to provide a drive circuit that can realize the output current of the drive circuit to quickly reach a predetermined value without overshoot or low current phenomenon, while avoiding power loss, improving the stable operation of the circuit and reducing power consumption.

The invention discloses a driving circuit, which is characterized in that it includes: a signal processing unit and a main circuit;

The signal processing unit is used to generate drive signals with different drive capabilities and timing based on the control signal of the drive circuit, and apply each drive signal to the corresponding MOS tube in the main circuit;

Under the action of each of the driving signals, the main circuit generates corresponding transient compensation when the control signal changes, so that the output current of the main circuit reaches a predetermined value within a preset time. , no overshoot or low current phenomenon occurs.

Optionally, the signal processing unit generates 6 driving signals.

Optionally, each of the driving signals acts on the gate terminals of different MOS transistors in the main circuit.

Optionally, the signal processing unit includes: eight inverters;

The first inverter, the second inverter, the third inverter and the fourth inverter are connected in series in sequence;

The output terminal of the fourth inverter serves as the second output terminal of the signal processing unit and outputs a second driving signal;

The input end of the fifth inverter is connected to the output end of the first inverter and the input end of the second inverter respectively, and the connection point serves as the fourth output end of the signal processing unit and the fourth output end of the signal processing unit. drive signal;

The output terminal of the fifth inverter serves as the first output terminal of the signal processing unit and outputs a first driving signal;

The sixth inverter, the seventh inverter and the eighth inverter are connected in series in sequence;

The input end of the sixth inverter is connected to the output end of the second inverter and the input end of the third inverter respectively, and the connection point serves as the third output end and the output end of the signal processing unit. third drive signal;

The connection point between the seventh inverter and the eighth inverter serves as the fifth output terminal of the signal processing unit and outputs a fifth driving signal;

The output terminal of the eighth inverter serves as the sixth output terminal of the signal processing unit and outputs a sixth driving signal.

Optionally, the eight inverters have different driving capabilities and timings.

Optionally, the closing speed of the first driving signal and the second driving signal is faster than the preset closing speed, and the opening speed is slower than the preset opening speed;

The fifth driving signal has a preset delay;

The driving capability of the sixth driving signal is greater than the preset driving capability.

Optional, in the main circuit:

Its eighth MOS tube and its ninth MOS tube constitute a current mirror circuit;

The tenth MOS tube and the eleventh MOS tube constitute a current mirror circuit;

Its twelfth MOS tube and its thirteenth MOS tube constitute a current mirror circuit;

Its fifth MOS tube and its sixth MOS tube constitute a current mirror circuit;

The fourteenth MOS tube, the fifteenth MOS tube, the sixteenth MOS tube and the seventeenth MOS tube constitute a current mirror circuit.

Optionally, the main circuit includes: a first resistor, a second resistor, a first capacitor, a second capacitor, and first to twentieth MOS transistors; wherein:

The fifth MOS transistor, the first MOS transistor and the eighth MOS transistor are arranged in series between the high-voltage power supply and the ground;

The sixth MOS transistor, the fourth MOS transistor and the thirteenth MOS transistor are arranged in series between the high-voltage power supply and ground;

The connection point between the sixth MOS tube and the fourth MOS tube serves as the output end of the main circuit;

The first resistor, seventh MOS transistor and second MOS transistor are arranged in series between the high-voltage power supply and ground;

The connection point between the first resistor and the seventh MOS transistor is respectively connected to the gate end of the fifth MOS transistor, the gate end of the sixth MOS transistor and the drain end of the nineteenth MOS transistor;

The gate end of the seventh MOS transistor is connected to the connection point between the fifth MOS transistor and the first MOS transistor;

The second resistor, the third MOS transistor and the eleventh MOS transistor are arranged in series between the high-voltage power supply and ground;

The connection point between the second resistor and the third MOS tube is connected to the gate terminal of the nineteenth MOS tube; the source terminal of the nineteenth MOS tube is connected to the high-voltage power supply;

The fifteenth MOS transistor, the twentieth MOS transistor and the ninth MOS transistor are arranged in series between the low-voltage power supply and the ground;

The sixteenth MOS transistor and the tenth MOS transistor are arranged in series between the low-voltage power supply and ground;

The seventeenth MOS transistor, the eighteenth MOS transistor and the twelfth MOS transistor are arranged in series between the low-voltage power supply and ground;

The source end of the fourteenth MOS tube is connected to the low-voltage power supply;

The drain end of the fourteenth MOS transistor is connected to the gate end of the fourteenth MOS transistor to the seventeenth MOS transistor respectively, and one end of the first capacitor and one end of the second capacitor, and the connection point is used to receive the reference current;

The other end of the first capacitor is connected to the low-voltage power supply;

The other end of the second capacitor is connected to the connection point between the fifteenth MOS transistor and the twentieth MOS transistor;

The connection point between the ninth MOS transistor and the twentieth MOS transistor is respectively connected to the gate end of the ninth MOS transistor and the gate end of the eighth MOS transistor;

The connection point between the sixteenth MOS transistor and the tenth MOS transistor is respectively connected to the gate end of the tenth MOS transistor and the gate end of the eleventh MOS transistor;

The connection point between the eighteenth MOS transistor and the twelfth MOS transistor is respectively connected to the gate end of the twelfth MOS transistor and the gate end of the thirteenth MOS transistor;

The gate terminal of the first MOS transistor serves as the first control terminal of the main circuit;

The gate terminal of the second MOS transistor serves as the second control terminal of the main circuit;

The gate terminal of the twentieth MOS transistor serves as the third control terminal of the main circuit;

The gate terminal of the third MOS transistor serves as the fourth control terminal of the main circuit;

The gate terminal of the eighteenth MOS transistor serves as the fifth control terminal of the main circuit;

The gate terminal of the fourth MOS transistor serves as the sixth control terminal of the main circuit.

Optionally, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube, the twelfth MOS tube, the thirteenth MOS tube and all The twentieth MOS transistors mentioned above are all low-voltage NMOS;

The fourteenth MOS tube, the fifteenth MOS tube, the sixteenth MOS tube, the seventeenth MOS tube, the eighteenth MOS tube and the nineteenth MOS tube are all low voltage PMOS;

The first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all high-voltage NMOS;

The fifth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are all high-voltage PMOS transistors.

Optionally, when the eighteenth MOS transistor is turned off, the seventeenth MOS transistor is disconnected.

As can be seen from the above technical solution, the present invention provides a driving circuit, including: a signal processing unit and a main circuit; the signal processing unit is used to generate driving signals with different driving capabilities and timing based on the control signal of the driving circuit, and convert each driving The signal acts on the corresponding MOS tube in the main circuit; under the action of each drive signal, when the control signal changes, the main circuit generates corresponding transient compensation, so that the output current of the main circuit reaches the predetermined value within the preset time. value, and there is no overshoot or low current phenomenon; the pull-up tube and the pull-down tube of the main circuit are not turned on at the same time through timing control.

Description of the drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are: For some embodiments of the present invention, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of a driving circuit provided by the prior art;

Figure 2 is a schematic diagram of a driving circuit provided by an embodiment of the present invention;

Figure 3 is a schematic diagram of another driving circuit provided by an embodiment of the present invention;

FIG. 4 is a timing diagram of the output current of a driving circuit provided by an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

In this application, the terms "comprises," "comprises," or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements not only includes those elements, but also includes none. Other elements expressly listed, or elements inherent to such process, method, article or equipment. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article, or apparatus that includes the stated element.

The embodiment of the present invention provides a driving circuit to solve the problem that when the driving circuit in the prior art changes between on and off, the output current of the driving circuit has overshoot or low current, and then the above may occur. Pull tube MP_HV2 and pull-down tubes MN_HV4 and MN6 are turned on at the same time, causing circuit power loss.

Referring to FIG. 2 , the driving circuit includes: a signal processing unit 10 and a main circuit 20 .

The signal processing unit 10 is used to generate drive signals with different drive capabilities and timing based on the input signal CMD of the drive circuit, and apply each drive signal to the corresponding MOS transistor in the main circuit 20 .

The signal processing unit 10 can use multiple inverters to generate multiple driving signals with different driving capabilities and timings. Of course, it is not limited to the above method, which will not be repeated here, as long as it can generate multiple different driving signals. The capability and timing of the drive signal interface are all within the scope of protection of this application.

Specifically, the input terminal of the signal processing unit 10 is used to receive the input signal CMD, and each output terminal of the signal processing unit 10 is respectively connected to the corresponding gate terminal of the main circuit 20 .

Under the action of each driving signal, when the input signal CMD changes, the main circuit 20 generates corresponding transient compensation, so that the output current of the main circuit 20 reaches a predetermined value within a preset time without overshoot. Or low current phenomenon.

When the input signal CMD indicates that the MOS tubes in the main circuit 20 need to switch states, the driving signal processing unit 10 generates multiple driving signals based on the input signal CMD, and the multiple driving signals act on the corresponding MOS tubes in the main circuit 20. Then, transient compensation is generated in the main circuit 20, which avoids overshoot or low current in the output current of the main circuit 20 when the switch state needs to be switched, and the pull-up tube and the pull-down tube in the main circuit 20 are simultaneously conducted. phenomenon, improve the stability of the output current and reduce losses.

It should be noted that the number, driving capabilities and timing of the driving signals with different driving capabilities and timings generated by the signal processing unit 10 are related to the corresponding MOS transistors in the main circuit 20 .

Specifically, the signal processing unit 10 generates six driving signals with different driving capabilities and timings. Of course, it can also be other numerical values, which will not be described one by one this time, and they are all within the protection scope of this application.

Each driving signal acts on the gate terminals of different MOS transistors in the main circuit 20 respectively; that is, it acts on different gate terminals of the main circuit 20 .

In practical applications, referring to Figure 3, the signal processing unit 10 includes: eight inverters; respectively: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter Inverter INV4, fifth inverter INV5, sixth inverter INV6, seventh inverter INV7 and eighth inverter INV8.

The first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 are connected in series in this order.

Specifically, the input terminal of the first inverter INV1 serves as the input terminal of the signal processing unit 10 and receives the input signal CMD; the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2; the second inverter INV2 The output terminal of the inverter INV2 is connected to the input terminal of the third inverter INV3, and the output terminal of the third inverter INV3 is connected to the input terminal of the fourth inverter INV4.

The output terminal of the fourth inverter INV4 serves as the second output terminal of the signal processing unit 10 and outputs the second driving signal g2.

The input terminal of the fifth inverter INV5 is connected to the output terminal of the first inverter INV1 and the input terminal of the second inverter INV2 respectively. The connection point serves as the fourth output terminal of the signal processing unit 10 and outputs the fourth driving signal. g4.

The output terminal of the fifth inverter INV5 serves as the first output terminal of the signal processing unit 10 and outputs the first driving signal g1.

The sixth inverter INV6, the seventh inverter INV7 and the eighth inverter INV8 are connected in series in sequence.

Specifically, the output terminal of the sixth inverter INV6 is connected to the input terminal of the seventh inverter INV7, and the output terminal of the seventh inverter INV7 is connected to the input terminal of the eighth inverter INV8.

The input terminal of the sixth inverter INV6 is connected to the output terminal of the second inverter INV2 and the input terminal of the third inverter INV3 respectively. The connection point serves as the third output terminal of the signal processing unit 10 and outputs the third driving signal. g3.

The connection point between the seventh inverter INV7 and the eighth inverter INV8 serves as the fifth output terminal of the signal processing unit 10 and outputs the fifth driving signal g5.

The output terminal of the eighth inverter INV8 serves as the sixth output terminal of the signal processing unit 10 and outputs the sixth driving signal g6.

It should be noted that the driving capabilities and timing of the eight inverters are different; the driving capabilities and timing of each inverter will not be described one by one here, and they are all within the protection scope of this application.

In practical applications, the closing speed of the first driving signal g1 and the second driving signal g2 is fast and the opening speed is slow; the fifth driving signal g5 has a preset delay; the driving capability of the sixth driving signal g6 is greater than the preset driving capability.

In any of the above embodiments, referring to Figure 3, the main circuit 20 includes: a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and the first to twentieth MOS transistors; wherein:

The fifth MOS transistor MP_HV1, the first MOS transistor MN_HV1 and the eighth MOS transistor MN1 are arranged in series between the high-voltage power supply VBAT and the ground.

Specifically, the source end of the fifth MOS transistor MP_HV1 is connected to the high-voltage power supply VBAT; the drain end of the fifth MOS transistor MP_HV1 is connected to the drain end of the first MOS transistor MN_HV1; the source end of the first MOS transistor MN_HV1 is connected to the drain end of the eighth MOS transistor MN1. The drain end is connected, and the source end of the eighth MOS transistor MN1 is connected to ground.

The sixth MOS transistor MP_HV2, the fourth MOS transistor MN_HV4 and the thirteenth MOS transistor MN6 are arranged in series between the high-voltage power supply VBAT and the ground.

Specifically, the source end of the sixth MOS transistor MP_HV2 is connected to the high-voltage power supply VBAT; the drain end of the sixth MOS transistor MP_HV2 is connected to the drain end of the fourth MOS transistor MN_HV4; the source end of the fourth MOS transistor MN_HV4 is connected to the thirteenth MOS transistor MN6 The drain end is connected, and the source end of the thirteenth MOS transistor MN6 is connected to the ground.

The connection point between the sixth MOS transistor MP_HV2 and the fourth MOS transistor MN_HV4 serves as the output terminal OUT of the main circuit 20 .

The first resistor R1, the seventh MOS transistor MP_HV3 and the second MOS transistor MN_HV2 are arranged in series between the high-voltage power supply VBAT and the ground.

Specifically, one end of the first resistor R1 is connected to the high-voltage power supply VBAT; the other end of the first resistor R1 is connected to the source end of the seventh MOS transistor MP_HV3; the drain end of the seventh MOS transistor MP_HV3 is connected to the drain end of the second MOS transistor MN_HV2. connected, the source end of the second MOS transistor MN_HV2 is connected to ground.

The connection point between the first resistor R1 and the seventh MOS transistor MP_HV3 is respectively connected to the gate end of the fifth MOS transistor MP_HV1, the gate end of the sixth MOS transistor MP_HV2 and the drain end of the nineteenth MOS transistor MP6.

The gate terminal of the seventh MOS transistor MP_HV3 is connected to the connection point between the fifth MOS transistor MP_HV1 and the first MOS transistor MN_HV1.

The second resistor R2, the third MOS transistor MN_HV3 and the eleventh MOS transistor MN4 are arranged in series between the high-voltage power supply VBAT and the ground.

Specifically, one end of the second resistor R2 is connected to the high-voltage power supply VBAT; the other end of the second resistor R2 is connected to the drain end of the third MOS transistor MN_HV3; the source end of the third MOS transistor MN_HV3 is connected to the drain end of the eleventh MOS transistor MN4. terminals are connected, and the source terminal of the eleventh MOS transistor MN4 is grounded.

The connection point between the second resistor R2 and the third MOS transistor MN_HV3 is connected to the gate end of the nineteenth MOS transistor MP6; the source end of the nineteenth MOS transistor MP6 is connected to the high-voltage power supply VBAT.

The fifteenth MOS transistor MP2, the twentieth MOS transistor MN7 and the ninth MOS transistor MN2 are arranged in series between the low-voltage power supply VDD and the ground.

Specifically, the source end of the fifteenth MOS transistor MP2 is connected to the low-voltage power supply VDD; the drain end of the fifteenth MOS transistor MP2 is connected to the drain end of the twentieth MOS transistor MN7; the source end of the twentieth MOS transistor MN7 is connected to the drain end of the twentieth MOS transistor MN7. The drain ends of the ninth MOS transistor MN2 are connected; the source end of the ninth MOS transistor MN2 is connected to the ground.

The sixteenth MOS transistor MP3 and the tenth MOS transistor MN3 are arranged in series between the low-voltage power supply VDD and the ground.

Specifically, the source end of the sixteenth MOS transistor MP3 is connected to the low-voltage power supply VDD, the drain end of the sixteenth MOS transistor MP3 is connected to the drain end of the tenth MOS transistor MN3, and the source end of the tenth MOS transistor MN3 is connected to the ground.

The seventeenth MOS transistor MP4, the eighteenth MOS transistor MP5 and the twelfth MOS transistor MN5 are arranged in series between the low-voltage power supply VDD and the ground.

Specifically, the source end of the seventeenth MOS transistor MP4 is connected to the low-voltage power supply VDD; the drain end of the seventeenth MOS transistor MP4 is connected to the source end of the eighteenth MOS transistor MP5; the drain end of the eighteenth MOS transistor MP5 is connected to the source end of the eighteenth MOS transistor MP5. The drain ends of the twelve MOS transistors MN5 are connected; the source end of the twelfth MOS transistor MN5 is connected to the ground.

The source end of the fourteenth MOS transistor MP1 is connected to the low-voltage power supply VDD.

The drain end of the fourteenth MOS transistor MP1 is connected to the gate end of the fourteenth MOS transistor MP1 to the seventeenth MOS transistor MP4 respectively, and one end of the first capacitor C1 and one end of the second capacitor C2. The connection point is used for receiving Reference current Iref.

The other end of the first capacitor C1 is connected to the low-voltage power supply VDD.

The other end of the second capacitor C2 is connected to the connection point between the fifteenth MOS transistor MP2 and the twentieth MOS transistor MN7.

The connection point between the ninth MOS transistor MN2 and the twentieth MOS transistor MN7 is connected to the gate terminal of the ninth MOS transistor MN2 and the gate terminal of the eighth MOS transistor MN1 respectively.

The connection point between the sixteenth MOS transistor MP3 and the tenth MOS transistor MN3 is respectively connected to the gate end of the tenth MOS transistor MN3 and the gate end of the eleventh MOS transistor MN4.

The connection point between the eighteenth MOS transistor MP5 and the twelfth MOS transistor MN5 is respectively connected to the gate end of the twelfth MOS transistor MN5 and the gate end of the thirteenth MOS transistor MN6.

The gate terminal of the first MOS transistor MN_HV1 serves as the first control terminal of the main circuit 20 and receives the first driving signal g1 of the signal processing unit 10 .

The gate terminal of the second MOS transistor MN_HV2 serves as the second control terminal of the main circuit 20 and receives the second driving signal g2 of the signal processing unit 10 .

The gate terminal of the twentieth MOS transistor MN7 serves as the third control terminal of the main circuit 20 and receives the third driving signal g3 of the signal processing unit 10 .

The gate terminal of the third MOS transistor MN_HV3 serves as the fourth control terminal of the main circuit 20 and receives the fourth driving signal g4 of the signal processing unit 10 .

The gate terminal of the eighteenth MOS transistor MP5 serves as the fifth control terminal of the main circuit 20 and receives the fifth driving signal g5 of the signal processing unit 10 .

The gate terminal of the fourth MOS transistor MN_HV4 serves as the sixth control terminal of the main circuit 20 and receives the sixth driving signal g6 of the signal processing unit 10 .

It should be noted that six MOS tubes: the first MOS tube MN_HV1, the second MOS tube MN_HV2, the twentieth MOS tube MN7, the third MOS tube MN_HV3, the eighteenth MOS tube MP5 and the fourth MOS tube MN_HV4 are used as the control main Circuit 20 is a MOS tube that switches on and off.

The sixth MOS transistor MP_HV2 serves as the output pull-up transistor in the main circuit 20; the fourth MOS transistor MN_HV4 and the thirteenth MOS transistor MN6 serve as the output pull-down transistor in the main circuit 20.

The eighth MOS transistor MN1 and the ninth MOS transistor MN2 constitute a current mirror circuit; the tenth MOS transistor MN3 and the eleventh MOS transistor MN4 constitute a current mirror circuit; the twelfth MOS transistor MN5 and the thirteenth MOS transistor MN6 constitute a current mirror circuit ; The fifth MOS transistor MP_HV1 and the sixth MOS transistor MP_HV2 constitute a current mirror circuit; the fourteenth MOS transistor MP1 and the fifteenth MOS transistor MP2 and the sixteenth MOS transistor MP3 and the seventeenth MOS transistor MP4 constitute a current mirror circuit.

In practical applications, the eighth MOS tube MN1, the ninth MOS tube MN2, the tenth MOS tube MN3, the eleventh MOS tube MN4, the twelfth MOS tube MN5, the thirteenth MOS tube MN6 and the twentieth MOS tube MN7 All are low voltage NMOS.

The fourteenth MOS tube MP1, the fifteenth MOS tube MP2, the sixteenth MOS tube MP3, the seventeenth MOS tube MP4, the eighteenth MOS tube MP5 and the nineteenth MOS tube MP6 are all low-voltage PMOS.

The first MOS transistor MN_HV1, the second MOS transistor MN_HV2, the third MOS transistor MN_HV3, and the fourth MOS transistor MN_HV4 are all high-voltage NMOS.

The fifth MOS transistor MP_HV1, the sixth MOS transistor MP_HV2, and the seventh MOS transistor MP_HV3 are all high-voltage PMOS.

It should be noted that the seventeenth MOS transistor MP4 has a large current during use. Therefore, when it is not in use, the seventeenth MOS transistor MP4 is disconnected by turning off the eighteenth MOS transistor MP5 to save power consumption.

Specifically, when the input signal CMD changes from low level to high level, the first MOS tube MN_HV1, the second MOS tube MN_HV2 and the twentieth MOS tube MN7 are turned on; the third MOS tube MN_HV3, the eighteenth MOS tube MP5 and The fourth MOS transistor MN_HV4 is turned off. At this time, the fourth MOS transistor MN_HV4 is turned off and the sixth MOS transistor MP_HV2 is turned on; so that the main circuit 20 can provide a stable output driving current.

When the input signal CMD changes from high level to low level, the first MOS transistor MN_HV1, the second MOS transistor MN_HV2 and the twentieth MOS transistor MN7 are turned off; the third MOS transistor MN_HV3, the eighteenth MOS transistor MP5 and the fourth MOS transistor are turned off. Tube MN_HV4 is turned on. At this time, the fourth MOS transistor MN_HV4 is turned on and the sixth MOS transistor MP_HV2 is turned off; so that the main circuit 20 can provide a stable output driving current.

It should be noted that the first capacitor C1 and the second capacitor C2 can keep the gate-source voltage VGS of the fourteenth MOS transistor MP1 unchanged when each MOS tube is turned off and on, thereby effectively ensuring that the main circuit is turned off and on. The output current of 20 does not cause overshoot or low current. When the twentieth MOS transistor and the eighteenth MOS transistor MP5 are turned off and on, they have an impact on the gate-source voltage VGS of the fourteenth MOS transistor MP1, but these two effects are opposite. In addition, the current magnitudes of the fifteenth MOS transistor MP2 and the seventeenth MOS transistor MP4 are different, and their influences are different. The second capacitor C2 is introduced to increase the influence of the twentieth MOS transistor MN7, making it different from the eighteenth MOS transistor MP4. The effects of MOS tube MP5 cancel each other out.

Referring to Figure 4, it should be noted that the closing speed of the first driving signal g1 and the second driving signal g2 is fast and the opening speed is slow; the fifth driving signal g5 has a preset delay; the driving capability of the sixth driving signal g6 is greater than the preset delay. Set the driving capability. The first resistor R1 and the third MOS transistor MN_HV3 can accelerate the opening of the sixth MOS transistor MP_HV2, and the second resistor R2 and the nineteenth MOS transistor MP6 can accelerate the closing of the sixth MOS transistor MP_HV2, thereby ensuring the output pull-up tube and the output The pull-down tubes will not be turned on at the same time, and at the same time, the output of the main circuit 20 will not experience overshoot or low current.

The features recorded in each embodiment in this specification can be replaced or combined with each other. The same and similar parts between the various embodiments can be referred to each other. Each embodiment focuses on its differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For relevant details, please refer to the partial description of the method embodiment. The system and system embodiments described above are only illustrative, in which the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, It can be located in one place, or it can be distributed over multiple network elements. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Persons of ordinary skill in the art can understand and implement the method without any creative effort.

The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (6)

1. A driving circuit, characterized by comprising: a signal processing unit and a main circuit;

the signal processing unit is used for generating driving signals with different driving capacities and time sequences based on the control signals of the driving circuit, and applying each driving signal to a corresponding MOS tube in the main circuit; the signal processing unit generates 6 driving signals; the closing speed of the first driving signal and the second driving signal is higher than the preset closing speed, and the opening speed of the first driving signal and the second driving signal is lower than the preset opening speed; the fifth driving signal has a preset delay; the driving capability of the sixth driving signal is larger than the preset driving capability;

when the control signals change under the action of the driving signals, the main circuit generates corresponding transient compensation so that the output current of the main circuit reaches a preset value within preset time, overshoot or low current phenomenon does not occur, and the output pull-up tube and the output pull-down tube of the main circuit are controlled to be not conducted simultaneously through time sequence;

the main circuit comprises:

an eighth MOS tube and a ninth MOS tube form a current mirror circuit;

the tenth MOS tube and the eleventh MOS tube form a current mirror circuit;

the twelfth MOS tube and the thirteenth MOS tube form a current mirror circuit;

the fifth MOS tube and the sixth MOS tube form a current mirror circuit;

a fourteenth MOS tube, a fifteenth MOS tube and a sixteenth MOS tube thereof form a current mirror circuit;

the main circuit includes: the first resistor, the second resistor, the first capacitor, the second capacitor and the first to twentieth MOS transistors; wherein:

the fifth MOS tube, the first MOS tube and the eighth MOS tube are sequentially connected in series between a high-voltage power supply and the ground;

the sixth MOS tube, the fourth MOS tube and the thirteenth MOS tube are sequentially connected in series between the high-voltage power supply and the ground;

the connection point between the sixth MOS transistor and the fourth MOS transistor is used as the output end of the main circuit;

the first resistor, the seventh MOS tube and the second MOS tube are sequentially connected in series between the high-voltage power supply and the ground;

the connection point between the first resistor and the seventh MOS tube; the gate terminal of the fifth MOS tube, the gate terminal of the sixth MOS tube and the drain terminal of the nineteenth MOS tube are respectively connected;

the gate end of the seventh MOS tube is connected with a connection point between the fifth MOS tube and the first MOS tube;

the second resistor, the third MOS tube and the eleventh MOS tube are sequentially connected in series between the high-voltage power supply and the ground;

the connection point between the second resistor and the third MOS tube is connected with the gate end of the nineteenth MOS tube; the source end of the nineteenth MOS tube is connected with the high-voltage power supply;

the fifteenth MOS tube, the twenty-second MOS tube and the ninth MOS tube are sequentially connected in series between a low-voltage power supply and the ground;

the sixteenth MOS tube and the tenth MOS tube are sequentially connected in series between the low-voltage power supply and the ground;

the seventeenth MOS tube, the eighteenth MOS tube and the twelfth MOS tube are sequentially connected in series between the low-voltage power supply and the ground;

the source end of the fourteenth MOS tube is connected with the low-voltage power supply;

the drain end of the fourteenth MOS tube is respectively connected with the gate ends of the fourteenth to seventeenth MOS tubes, one end of the first capacitor is connected with one end of the second capacitor, and the connection point is used for receiving reference current;

the other end of the first capacitor is connected with the low-voltage power supply;

the other end of the second capacitor is connected with a connection point between the fifteenth MOS tube and the twentieth MOS tube;

the connection point between the ninth MOS tube and the twentieth MOS tube is respectively connected with the gate end of the ninth MOS tube and the gate end of the eighth MOS tube;

the connection point between the sixteenth MOS tube and the tenth MOS tube is respectively connected with the gate end of the tenth MOS tube and the gate end of the eleventh MOS tube;

the connection point between the eighteenth MOS tube and the twelfth MOS tube is respectively connected with the gate end of the twelfth MOS tube and the gate end of the thirteenth MOS tube;

the gate end of the first MOS tube is used as a first control end of the main circuit;

the gate end of the second MOS tube is used as a second control end of the main circuit;

the grid end of the twentieth MOS tube is used as a third control end of the main circuit;

the gate end of the third MOS tube is used as a fourth control end of the main circuit;

the gate end of the eighteenth MOS tube is used as a fifth control end of the main circuit;

and the gate end of the fourth MOS tube is used as a sixth control end of the main circuit.

2. The driving circuit according to claim 1, wherein each of the driving signals acts on a gate terminal of a different MOS transistor in the main circuit.

3. The drive circuit according to claim 1, wherein the signal processing unit includes: eight inverters;

the first inverter, the second inverter, the third inverter and the fourth inverter are sequentially connected in series;

the output end of the fourth inverter is used as a second output end of the signal processing unit and outputs a second driving signal;

the input end of the fifth inverter is respectively connected with the output end of the first inverter and the input end of the second inverter, and the connection point is used as a fourth output end of the signal processing unit and outputs a fourth driving signal;

the output end of the fifth inverter is used as a first output end of the signal processing unit and outputs a first driving signal;

the sixth inverter, the seventh inverter and the eighth inverter are sequentially connected in series;

the input end of the sixth inverter is respectively connected with the output end of the second inverter and the input end of the third inverter, and the connection point is used as a third output end of the signal processing unit and outputs a third driving signal;

a connection point between the seventh inverter and the eighth inverter as a fifth output terminal of the signal processing unit, outputting a fifth driving signal;

the output end of the eighth inverter is used as a sixth output end of the signal processing unit and outputs a sixth driving signal.

4. A driving circuit according to claim 3, wherein the driving capability and timing of the eight inverters are different.

5. The drive circuit of claim 1, wherein the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, and the twentieth MOS transistor are low-voltage NMOS;

the fourteenth MOS tube, the fifteenth MOS tube, the sixteenth MOS tube, the seventeenth MOS tube, the eighteenth MOS tube and the nineteenth MOS tube are all low-voltage PMOS;

the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all high-voltage NMOS;

the fifth MOS tube, the sixth MOS tube and the seventh MOS tube are all high-voltage PMOS.

6. The drive circuit of claim 5, wherein the seventeenth MOS transistor is turned off when the eighteenth MOS transistor is turned off.