CN107016962B - Pixel circuit, driving method thereof and display panel - Google Patents

Abstract

The present invention relates to a pixel circuit, comprising: an organic light emitting diode, including an anode terminal and a cathode terminal; a driving transistor, including a first node, a second node and a third node; a first transistor, including a first terminal connected to a data driving line, a second terminal connected to a first control signal source, and a third terminal connected to the second node; a second transistor, including a first terminal, a second terminal connected to a second control signal source, and a third terminal connected to the anode terminal and the third node; a storage capacitor, including a first terminal connected to a third voltage source and a second terminal connected to the first terminal of the second transistor; and a coupling capacitor, including a first terminal connected to the first terminal of the second transistor and a second terminal connected to the second node.

Description

Pixel circuit and driving method thereof, and display panel

This application is a divisional application, the application number of the parent case: 201410090454.2, the application date: March 12, 2014, and the title: Pixel circuit and its driving method and display panel.

technical field

The present invention relates to a pixel circuit and a driving method thereof, in particular to an active matrix organic light emitting diode pixel circuit and a driving method thereof suitable for compensation of transistor threshold voltage and organic light emitting diode voltage.

Background technique

The driving transistors of active matrix organic light emitting diodes (AMOLEDs) can be divided into P-type and N-type transistors according to the backplane technology. Please refer to FIG. 1 and FIG. 2 , which are schematic diagrams of a P-type driving circuit of a known active matrix organic light emitting diode and a schematic diagram of an N-type driving circuit of a known active matrix organic light emitting diode. As shown in FIG. 2 , for the N-type driving circuit, there is still the problem of the offset of the threshold voltage of the N-type transistor. Due to the difference in the process and the degradation of the long-term operation, the threshold voltage will be offset. Shift, that is, unable to output the same current as the original, resulting in regional unevenness or brightness attenuation. In addition, the operating voltage of the organic light emitting diode increases with time due to long-term operation. Therefore, an N-type compensation driving circuit is proposed to solve the above problems. Please refer to FIG. 3 and FIG. 4 at the same time, which are schematic diagrams and timing diagrams of the N-type compensation driving circuit of the known active matrix organic light emitting diode. As shown in FIG. 3 and FIG. 4 , due to the excessive number of elements (6T2C) in the pixel circuit design and the excessive complexity of the driving signals (Sn, Sn', En, Xen), the requirements of high definition and high aperture ratio cannot be achieved.

Therefore, in the spirit of the active invention, the inventors urgently devised a pixel circuit and a driving method thereof, so as to use an N-type driving transistor to drive an organic light emitting diode, and combine a plurality of transistors and capacitors to compensate the threshold voltage of the N-type transistor, The voltage of the active-matrix organic light-emitting diode, as well as meeting the requirements of high precision and high aperture ratio, were finally completed after several research experiments.

SUMMARY OF THE INVENTION

The present invention provides a pixel circuit, comprising: an organic light emitting diode (OLED), comprising an anode terminal and a cathode terminal, the cathode terminal is connected to a first voltage source; a driving transistor is used to drive the organic light emitting diode, driving the The transistor includes a first node, a second node and a third node, the first node is connected to a second voltage source, and the third node is connected to the anode terminal; a first transistor includes a first terminal connected to a data driving line , a second end connected to a first control signal source, and a third end connected to the second node; a second transistor comprising a first end, a second end connected to a second control signal source, and a third terminal connected to the anode terminal and the third node; a storage capacitor including a first terminal connected to a third voltage source and a second terminal connected to the first terminal of the second transistor; and a coupling capacitor , comprising a first end connected to the first end of the second transistor, and a second end connected to the second node.

In addition, in a reset stage, the first control signal source provides a first control signal to turn on the first transistor, and the data driving line inputs a reference voltage to the driving transistor to reset the second node, the third node and the coupling capacitor. The first end, in a compensation stage, the second node and the storage capacitor store a threshold voltage of the driving transistor, the driving transistor is turned from an on state to an off state, and in a data writing stage, the second control signal source provides a first Two control signals to turn off the second transistor, the data driving line inputs a data voltage to the driving transistor, a voltage of the coupling capacitor is coupled to the first end of the coupling capacitor, in a light-emitting stage, the threshold voltage and a voltage of the organic light emitting diode is coupled to the second node.

Furthermore, the driving transistor, the first transistor and the second transistor are N-type transistors.

In addition, the pixel circuit includes a third transistor including a first end connected to a fourth voltage source, a second end connected to a third control signal source, and a third end connected to the second node, the fourth The voltage source provides a reference voltage, and the third transistor is turned on according to a third control signal to input the reference voltage to the second node.

In addition, the pixel circuit includes a fourth transistor including a first end connected to the anode end and the third node, a second end connected to a fourth control signal source, and a third end connected to a fifth voltage source .

Furthermore, in a reset stage, the first control signal source provides a first control signal to turn on the first transistor, the second control signal source provides a second control signal to turn on the second transistor, and the fourth control signal source provides A fourth control signal turns on the fourth transistor, the data driving line inputs a first reference voltage to the driving transistor to reset the second node, and the fifth voltage source inputs a second reference voltage to the fourth transistor to reset the third node and the first end of the coupling capacitor, in a compensation stage, the data drive line inputs a third reference voltage to the second node, the third node and the storage capacitor store the difference between the third reference voltage of the drive transistor and a threshold voltage, The driving transistor changes from an on state to an off state. In a data writing stage, the data driving line inputs a data voltage to the driving transistor, and the difference between the third reference voltage and the data voltage is coupled to the first end of the coupling capacitor, and the In the light-emitting stage, the threshold voltage and a voltage of the organic light emitting diode are coupled to the second node.

In addition, the present invention provides a method for driving a pixel circuit, the pixel circuit includes an organic light emitting diode (OLED), a driving transistor, a first transistor, a second transistor, a storage capacitor and a coupling capacitor, The organic light emitting diode has an anode terminal and a cathode terminal connected to a first voltage source, the first voltage source provides a first voltage, and the driving transistor has a first node connected to a second voltage source, a second node and the connection A third node of the anode terminal, the second voltage source provides a second voltage, the first transistor has a first terminal connected to a data driving line, a second terminal connected to a first control signal source, and a second terminal connected to the A third terminal of the node, the first control signal source provides a first control signal, the second transistor has a first terminal, a second terminal connected to a second control signal source, and a terminal connected to the anode terminal and the third node. a third terminal, the second control signal source provides a second control signal, the storage capacitor has a first terminal connected to a third voltage source and a second terminal connected to the first terminal of the second transistor, the coupling capacitor has a connection A first end of the first end of the second transistor and a second end connected to the second node, the method includes the steps: (A) during a reset stage, turning on the first transistor through a first control signal, and inputting a reference The voltage is applied to the driving transistor to reset the second node, the third node and the first end of the coupling capacitor; (B) in a compensation stage, a threshold voltage of the driving transistor is stored to the third node and the storage capacitor, and the driving transistor is composed of The on state is changed to the off state; (C) during a data writing stage, the second transistor is turned off by the second control signal, a data voltage is input to the driving transistor, and a voltage of the coupling capacitor is coupled to the first end of the coupling capacitor and (D) coupling the threshold voltage and a voltage of the organic light emitting diode to the second node during a light-emitting stage.

In addition, the present invention provides another method for driving a pixel circuit. The pixel circuit includes an organic light emitting diode (OLED), a driving transistor, a first transistor, a second transistor, a fourth transistor, and a storage capacitor. and a coupling capacitor, the organic light emitting diode has an anode terminal and a cathode terminal connected to a first voltage source, the first voltage source provides a first voltage, the driving transistor has a first node connected to a second voltage source, a The second node and a third node connected to the anode terminal, the second voltage source provides a second voltage, the first transistor has a first terminal connected to a data driving line, and a second terminal connected to a first control signal source , and a third end connected to the second node, the first control signal source provides a first control signal, the second transistor has a first end, a second end connected to a second control signal source, and connected to the anode The terminal and a third end of the third node, the second control signal source provides a second control signal, the storage capacitor has a first end connected to a third voltage source and a first end connected to the second transistor The second end, the coupling capacitor has a first end connected to the first end of the second transistor and a second end connected to the second node, the fourth transistor has a first end connected to the anode end and the third node, and a first end connected to the second node. A second terminal of the fourth control signal source, and a third terminal connected to a fifth voltage source, the method includes the steps: (A) in a reset stage, the data driving line inputs a first reference voltage to the driving transistor To reset the second node, the fifth voltage source inputs a second reference voltage to the fourth transistor to reset the third node and the first end of the coupling capacitor; (B) in a compensation stage, the data driving line inputs a first Three reference voltages are applied to the driving transistor to reset the second node, the third node and the storage capacitor store the difference between the third reference voltage of the driving transistor and a threshold voltage, and the driving transistor is turned from an on state to an off state; (C) in a In the data writing stage, the data driving line inputs a data voltage to the driving transistor, and the difference between the third reference voltage and the data voltage is coupled to the first end of the coupling capacitor; and (D) in a light-emitting stage, the threshold voltage and the organic A voltage of the light emitting diode is coupled to the second node.

In addition, the present invention provides a display panel, comprising: a plurality of pixel circuits arranged in a matrix of pixel circuits according to a plurality of rows and columns; a data driver having a plurality of data driving lines for connecting the pixels a plurality of pixel circuits in the row of the circuit matrix to provide at least one input voltage; a scan driver, which has a plurality of scan driving lines perpendicularly intersecting with a plurality of data driving lines, and is used to connect the plurality of pixel circuits in the column of the pixel circuit matrix to provide at least one switching voltage; a voltage generator has a plurality of voltage supply lines disposed between a plurality of scan driving lines for connecting a plurality of pixel circuits to provide at least a voltage source; and a timing controller, which is Connect and control the data driver, scan driver and voltage generator respectively.

In addition, the present invention provides another display panel, comprising: a plurality of pixel circuits arranged in a matrix of pixel circuits according to a plurality of rows and columns; a data driver having a plurality of data driving lines for connecting A plurality of pixel circuits in a row of the pixel circuit matrix provide at least one input voltage; a scan driver has a plurality of scan driving lines perpendicularly intersecting with the plurality of data driving lines, and is used to connect the columns of the pixel circuit matrix a plurality of pixel circuits for providing at least one switching voltage; and a timing controller respectively connecting and controlling the data driver and the scan driver, wherein each pixel circuit includes: an organic light emitting diode (OLED) including an anode terminal and a cathode terminal, the cathode terminal is connected to a first voltage source; a driving transistor for driving the organic light emitting diode, the driving transistor includes a first node, a second node and a third node, the first node a second voltage source is connected, the third node is connected to the anode terminal; a first transistor includes a first end connected to one of the data driving lines of the plurality of data driving lines, and a first control signal source connected to a second end, and a third end connected to the second node; a second transistor including a first end, a second end connected to a second control signal source, and the anode end and the third node a third end of the ; a storage capacitor including a first end connected to a third voltage source and a second end connected to the first end of the second transistor; a coupling capacitor including a connection to the second transistor a first end of the first end and a second end connected to the second node; and a fourth transistor including a first end connected to the anode end and the third node and connected to a fourth control signal source a second end of the , and a third end connected to a fifth voltage source.

The foregoing summary and the following detailed description are exemplary in nature and are intended to further illustrate the scope of the present invention. The other objects and advantages of the present invention will be explained in the following description and accompanying drawings.

Description of drawings

In order to further illustrate the technical content of the present invention, the following detailed description is as follows in conjunction with the embodiments and the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a P-type driving circuit of a known active matrix organic light emitting diode.

FIG. 2 is a schematic diagram of an N-type driving circuit of a known active matrix organic light emitting diode.

FIG. 3 is a schematic diagram of an N-type compensation driving circuit of a known active matrix organic light emitting diode.

FIG. 4 is a timing diagram of the compensation driving circuit of FIG. 3 .

FIG. 5 is a schematic diagram of a pixel circuit according to a preferred embodiment of the present invention.

FIG. 6 is a timing diagram of a preferred embodiment of the pixel circuit of FIG. 5 .

FIG. 7 is a timing diagram of another preferred embodiment of the pixel circuit of FIG. 5 .

FIG. 8 is a schematic diagram of a display panel according to a preferred embodiment of the present invention.

FIG. 9 is a timing diagram of a preferred embodiment of the display panel of FIG. 8 with three columns of a pixel circuit matrix as a display unit.

FIG. 10 is a timing diagram of another preferred embodiment of the display panel of FIG. 8 with three columns of a pixel circuit matrix as a display unit.

FIG. 11 is a schematic diagram of a pixel circuit according to another preferred embodiment of the present invention.

FIG. 12 is a timing diagram of a preferred embodiment of the pixel circuit of FIG. 11 .

FIG. 13 is a timing diagram of another preferred embodiment of the pixel circuit of FIG. 11 .

FIG. 14 is a schematic diagram of a pixel circuit according to another preferred embodiment of the present invention.

FIG. 15 is a timing diagram of a preferred embodiment of the pixel circuit of FIG. 14 .

FIG. 16 is a schematic diagram of a display panel according to another preferred embodiment of the present invention.

FIG. 17 is a timing diagram of a preferred embodiment of the display panel of FIG. 16 in which column 1 of the pixel circuit matrix is a display unit.

FIG. 18 is a timing diagram of a preferred embodiment of the display panel of FIG. 16 with three columns of a pixel circuit matrix as a display unit.

FIG. 19 is a timing diagram of a preferred embodiment of the display panel of FIG. 16 with n columns of a pixel circuit matrix as a display unit.

Detailed ways

First, please refer to FIG. 5 , which is a schematic circuit diagram of a preferred embodiment of the present invention. FIG. 5 shows a pixel circuit including: a driving transistor 50 , an organic light emitting diode 51 , and a voltage control unit 52 . The organic light emitting diode 51 includes an anode terminal 511 and a cathode terminal 512, wherein the cathode terminal 512 is connected to a first voltage source VSS for providing a first voltage Vss. The driving transistor 50 is preferably an N-type transistor, which includes a first node 501 , a second node 502 and a third node 503 , wherein the first node 501 is the drain terminal, the second node 502 is the gate terminal, and the third node 502 The node 503 is the source terminal, the first node 501 is electrically connected to a second voltage source VDD for providing a second voltage Vdd, and the third node 503 is connected to the anode terminal 511 .

The aforementioned voltage control unit 52 includes a first transistor 57 , a second transistor 58 , a storage capacitor 56 and a coupling capacitor 55 . The first transistor 57 has a first end 571 connected to a data driving line Data, a second end 572 connected to a first control signal source SN for providing a first control signal, and a second node 502 The third end 573. The second transistor 58 has a first terminal 581 , a second terminal 582 connected to a second control signal source SW for providing a second control signal, and a third terminal connected to the anode terminal 511 and the third node 503 583. The first and second transistors 57 and 58 are preferably N-type transistors. The storage capacitor 56 has a first terminal 561 connected to a third voltage source REF and a second terminal 562 connected to the first terminal 581 of the second transistor 58 . The coupling capacitor 55 has a first terminal 551 connected to the first terminal 581 of the second transistor 58 and a second terminal 552 connected to the second node 502 . Accordingly, when the pixel circuit is in a reset stage, the first transistor 57 is turned on by the first control signal, and a reference voltage Vref is input to the driving transistor 50 to reset the second node 502 , the third node 503 and the second transistor 58 The first terminal 581 of the pixel circuit stores a threshold voltage Vt of the driving transistor 50 to the third node 503 and the storage capacitor 56 when the pixel circuit is in a compensation stage, and the driving transistor 50 changes from an on state to an off state. When the pixel circuit is in a During the data writing stage, the second transistor 58 is turned off by the second control signal, a data voltage is input to the driving transistor 50, and a voltage of the coupling capacitor 55 is coupled to the first end 581 of the second transistor 58. When the pixel circuit is in a During the light-emitting stage, the threshold voltage Vt and the voltage Voled of the organic light emitting diode 51 are coupled to the second node 502 , wherein the aforementioned reset stage, compensation stage, data writing stage and light-emitting stage are sequentially repeated.

Please also refer to FIG. 6 , which is a working timing diagram of a preferred embodiment of the pixel circuit of FIG. 5 . Its circuit operation is divided into a reset (Reset) stage, a compensation (Comp.) stage, a data writing (Prog.) stage and an emitting (Emitting) stage, and the driving transistor 50, the first transistor 57, the second transistor 58 and the organic The on or off state of the light emitting diode 51 is shown in Table 1, as well as the voltage (V _G ) of the second node 502 of the driving transistor 50 , the voltage (V _S ) of the anode terminal 511 of the organic light emitting diode 51 , and the first voltage of the coupling capacitor 55 . The voltage at one end 551 (V _N ), the voltage difference between the second node 502 and the anode end 511 (V _GS ), and the voltage difference between the second node 502 and the first end 551 of the coupling capacitor 55 (V _GN ) are shown in Table 2 Show.

Table 1

cycle drive transistor first transistor second transistor Organic Light Emitting Diode reset phase turn on turn on turn on closure Compensation stage closure turn on turn on closure data writing stage turn on turn on closure closure glow stage turn on closure turn on turn on

Table 2

Accordingly, in the reset stage, the driving transistor 50 , the first transistor 57 , and the second transistor 58 are turned on, and the organic light emitting diode 50 is turned off, and the data driving line (Data) inputs a reference voltage Vref to the first transistor The first terminal 571 of 57 and the third terminal 573 of the first transistor 57 reset the second node 502 to the reference voltage Vref, while the second voltage Vdd is a reset voltage Vrst and satisfies Vref>Vrst+Vt, so that The third node 503 is reset to the reset voltage Vrst, and the first terminal 551 of the coupling capacitor 55 is also reset to the reset voltage Vrst.

During the compensation stage, the first transistor 57 and the second transistor 58 are turned on, and the organic light emitting diode 50 is turned off, the second node 502 is still the reference voltage Vref, and the second voltage Vdd is transformed into a high-level voltage ELVDD, The driving transistor 50 is gradually discharged from the on state to the off state, so that the anode terminal 511 of the organic light emitting diode 51 is discharged to Vref-Vt, and the threshold voltage Vt of the driving transistor 50 is measured and stored in the storage capacitor 56 accordingly.

As shown in FIG. 6 , there is an interval time (T_space) after the compensation phase, which is an interval time between the compensation phase and the data writing phase, and the interval time is greater than or equal to zero.

During the data writing stage, the driving transistor 50 and the first transistor 57 are turned on, and the second transistor 58 and the organic light emitting diode 50 are turned off. The data driving line (Data) inputs a data voltage Vdata to the first transistor 57 . The first terminal 571 and the third terminal 573 of the first transistor 57 make the second node 502 the data voltage Vdata, while the second voltage Vdd is the reset voltage Vrst, and the voltage V _N of the first terminal 551 of the coupling capacitor 55 Coupling via coupling capacitor 55 to:

V _N =Vref-Vt+(Vdata-Vref)*f1

=Vref*(1-f1)+Vdata*f1-Vt, -----(1)

The voltage difference between the second node 502 and the first end 551 of the coupling capacitor 55 is:

V _GN =Vdata-(Vref(1-f1)+Vdata*f1-Vt)

=(Vdata-Vref)*(1-f1)+Vt, -----(2)

where f1=Ccp/(Ccp+Cst), Ccp is the capacitance value of the coupling capacitor 55 and Cst is the capacitance value of the storage capacitor 56, and the storage capacitor 56 has both the threshold voltage Vt and the data voltage Vdata of the previous stage, so that the second The voltage difference VGN between the node 502 and the first end 551 of the coupling capacitor 55 is greater than or equal to the threshold voltage Vt. At the same time, the organic light emitting diode 51 cannot be turned on, so the following conditions must also be met:

Vrst≤Vss+Voled(0), -----(3)

Wherein Voled(0) is the turn-on voltage of the organic light emitting diode 51 .

In the light-emitting stage, the driving transistor 50 , the second transistor 58 and the organic light emitting diode 51 are turned on, and the first transistor 57 is turned off. At this time, the anode terminal 511 and the first terminal 551 of the coupling capacitor 55 are both organic light emitting diodes. The voltage Voled of 51, and the coupling capacitor 55 couples the voltage Voled of the organic light emitting diode 51 to the second node 502:

V _G =Vdata+(Voled-(Vref*(1-f1)+Vdata*f1-Vt))

=(Vdata-Vref)*(1-f1)+Vt+Voled, -----(4)

The voltage difference between the second node 502 and the anode terminal 511 is:

V _GS =(Vdata-Vref)*(1-f1)+Vt, -----(5)

Therefore, the output current I _oled of the driving transistor 50 can be expressed as:

I _oled =Kp*(V _GS -Vt) ²

=Kp*[(Vdata-Vref)*(1-f1)] ² , -----(6)

Wherein, Kp=1/2(μ*COX)(W/L), μ is the carrier mobility of the driving transistor 50 , COX is the capacitance per unit area of the driving transistor 50 , (W/L) is the width of the driving transistor 50 length ratio, and it can be seen from formula (6) that the output current of the driving transistor 50 has nothing to do with the threshold voltage Vt and the voltage Voled of the organic light emitting diode 51, and not only compensates the threshold voltage of the transistor, the voltage of the active matrix organic light emitting diode, At the same time, it also meets the needs of high precision and high aperture ratio.

It should be noted that, during the light-emitting stage, there is charge distribution between the first end 551 of the coupling capacitor 55 and the third node 503 due to the instant turn-on of the second transistor 58 . At the moment when the second transistor 58 is turned on, the voltage of the first terminal 551 of the coupling capacitor 55 can be expressed as:

V _N ={V _{N_pro} *Cst+V _{S_pro} *Coled}/(Cst+Coled), -----(7)

Wherein, Coled is the capacitance value of the organic light emitting diode 51, V _{N_pro} is the voltage of the first end 551 of the coupling capacitor 55 in the compensation stage (ie Vref*(1-f1)+Vdata*f1-Vt), and V _{S_pro} is The voltage of the third node 503 (ie Vref) during the compensation phase. If the capacitance value Coled of the organic light emitting diode 51 is negligible (that is, Coled is much smaller than the capacitance value Cst of the storage capacitor 56 ), Equation (7) can be simplified as

V _N =Vref*(1-f1)+Vdata*f1-Vt, -----(8)

It can be seen that the voltage of the first terminal 551 of the coupling capacitor 55 remains unchanged, and the threshold voltage Vt and the voltage Voled of the organic light emitting diode 51 are still stored. However, if the capacitance value Coled of the organic light emitting diode 51 is not negligible, the first terminal 551 of the coupling capacitor 55 may lose the stored threshold voltage Vt due to the charge distribution between the first terminal 551 and the third node 503 .

Please refer to FIG. 5 and FIG. 7 at the same time. FIG. 7 is a working timing diagram of another preferred embodiment of the pixel circuit of FIG. 5 . The difference from FIG. 6 is that in the data writing stage, the second voltage Vdd is the high-level voltage ELVDD and the driving transistor 50 is not reset, and the rest are the same. The operation timing diagram shown in FIG. 7 is preferably used when the capacitance value Coled of the organic light emitting diode 51 is not negligible (ie, Coled is not much smaller than the capacitance value Cst of the storage capacitor 56 ). The third node 503 is reset to Vdata-Vt during the data write phase. At the moment when the second transistor 58 is turned on, the voltage V _N of the first terminal 551 of the coupling capacitor 55 becomes:

V _N ={[Vref*(1-f1)+Vdata*f1-Vt]*Cst+[Data-Vt]*Coled}/

(Cst+Coled)={[Vref*(1-f1)+Vdata*f1]*Cst+(Data*Coled)}/

(Cst+Coled)-Vt

=Func(Vref, Vdata, Ccp, Cst, Coled)-Vt, -----(9)

Wherein Func(Vref, Vdata, Ccp, Cst, Coled) is a function related to Vref, Vdata, Ccp, Cst and Coled. It can be known from equation (9) that the threshold voltage Vt stored in the first terminal 551 of the coupling capacitor 55 is not lost at the moment when the second transistor 58 is turned on. Under the operating timing diagram shown in FIG. 7 , the voltage of the second node 502 (V _G ), the voltage of the anode terminal 511 of the organic light emitting diode 51 (V _S ), and the voltage of the first terminal 551 of the coupling capacitor 55 (V _{N )} ), the voltage difference (V _GS ) between the second node 502 and the anode terminal 511 , and the voltage difference (V _GN ) between the second node 502 of the driving transistor 50 and the first terminal 551 of the coupling capacitor 55 (V GN ) are shown in Table 3.

table 3

The present invention also provides a method for driving a pixel circuit. Referring to the pixel circuit shown in FIG. 5, the method includes the steps of: (A) during a reset stage, turning on the first transistor through a first control signal 57. Input a reference voltage Vref to the driving transistor 50 to reset the second node 502, the third node 503 and the first terminal 581 of the second transistor 58; (B) in a compensation stage, store the threshold voltage of the driving transistor 50 Vt to the third node 503 and the storage capacitor 56, the driving transistor 50 is turned from the on state to the off state; (C) The second transistor 58 is turned off by the second control signal, the data voltage Vdata is input to the driving transistor 50, and the coupling capacitor 55 is coupled to the first end 551 of the coupling capacitor 55 ; and (D) coupling the threshold voltage Vt and the voltage Voled of the organic light emitting diode 51 to the second node 502 in a light-emitting stage.

Please refer to FIG. 8 , which is a schematic diagram of a display panel using the aforementioned pixel circuit according to a preferred embodiment of the present invention. It includes: a plurality of pixel circuits 80 , a data driver 81 , a scan driver 82 , a voltage generator 83 , and a timing controller 84 . The plurality of pixel circuits 80 are arranged in a pixel circuit matrix according to a plurality of rows and columns; the data driver 81 has a plurality of data driving lines (Data_1, Data_2, Data_3, . . . ) for connecting the pixel circuit matrix A plurality of pixel circuits 80 in a row to provide at least one input voltage; the scan driver 82 has a plurality of scan driving lines (SN_1, SW_1, SN_2, SW_2, SN_3, SW_3, . . . ) for connecting a plurality of pixel circuits 80 in a row of the pixel circuit matrix to provide at least one switching voltage; the voltage generator 83 has a plurality of voltage supply lines (VDD_1, VDD_2) disposed between the plurality of scan driving lines , VDD_3, . In one embodiment, the display panel is a display unit with three columns of a pixel circuit matrix. The reset phase, the compensation phase, the data writing phase, and the light-emitting phase of each display unit are performed sequentially, and each display unit is performed sequentially.

Please refer to FIG. 9 at the same time, which is a working timing diagram of a preferred embodiment of the display panel of FIG. 8 with three columns of a pixel circuit matrix as a display unit. An embodiment is shown in FIG. 9 , the difference from FIG. 6 is that in the data writing stage, the scan driver 82 sequentially turns on the plurality of pixel circuits 80 in each column of the display unit through the scan driving lines (SN_1, SN_2, SN_3). The first transistor 57 simultaneously inputs a data voltage group Vdata(1, 2, 3) to the data driving line Data(m), and the data voltage group Vdata(1, 2, 3) sequentially inputs a data voltage to a plurality of each row When the first transistors 57 of the pixel circuits 80, the data voltage group Vdata(1, 2, 3) corresponds to the first transistors 57 of the pixel circuits 80 in each column that are sequentially turned on by the scan driving lines (SN_1, SN_2, SN_3) A data voltage is sequentially input to the first transistors 57 of the plurality of pixel circuits 80 in each row, and the rest are the same. After the display unit completes the reset phase, the compensation phase, the data writing phase and the light-emitting phase, the next display unit proceeds in sequence.

Please refer to FIG. 8 and FIG. 10 at the same time. FIG. 10 is a timing diagram of another preferred embodiment of the display panel of FIG. 8 with three columns of a pixel circuit matrix as a display unit. As shown in FIG. 10 , the difference from FIG. 7 is that in the data writing stage, the scan driver 82 sequentially turns on a plurality of pixel circuits in each of the three columns of the pixel circuit matrix via the scan driving lines (SN_1, SN_2, SN_3). The first transistor 57 of 80, while the data driving line Data(m) inputs a data voltage group Vdata(1, 2, 3), and the data voltage group Vdata(1, 2, 3) sequentially inputs a data voltage to each row The first transistors 57 of the plurality of pixel circuits 80, the data voltage group Vdata (1, 2, 3) corresponds to the first transistors of each column of the plurality of pixel circuits 80 that are sequentially turned on by the scan driving lines (SN_1, SN_2, SN_3) At 57, a data voltage is sequentially input to the first transistors 57 of the plurality of pixel circuits 80 in each row, and the rest are the same. The difference from FIG. 9 is only that in the data writing stage, the second voltages Vdd_1, 2, 3 provided by the plurality of voltage supply lines of the voltage generator 83 are maintained at a high voltage ELVDD and the driving transistor 50 is not reset. , and the rest are the same.

Please refer to FIG. 11 , which is a schematic diagram of a pixel circuit according to another preferred embodiment of the present invention. The difference from FIG. 5 is that a third transistor 119 is added, which has a first terminal 1191 connected to a fourth voltage source and a second terminal connected to a third control signal source Rst providing a third control signal 1192, and a third terminal 1193 connected to the second node 502, wherein the fourth voltage source is used to provide a reference voltage Vref. Please also refer to FIG. 12 , which is a working timing diagram of a preferred embodiment of the pixel circuit of FIG. 11 . The purpose is only to reduce the turn-on frequency of the first control signal in FIG. 6 , and the third transistor 119 is turned on by the third control signal to input the reference voltage Vref, and the rest are the same.

Please refer to FIG. 11 and FIG. 13 at the same time. FIG. 13 is a working timing diagram of another preferred embodiment of the pixel circuit of FIG. 11 . As shown in FIG. 13 , the difference from FIG. 7 is that the turn-on frequency of the first control signal in FIG. 7 is reduced, and the third transistor 119 is turned on by the third control signal to input the reference voltage Vref, and the rest are the same. The difference from FIG. 12 is that during the data writing stage, the second voltage Vdd provided by the plurality of voltage supply lines of the voltage generator 83 is maintained at a high potential voltage ELVDD and the driving transistor 50 is not reset. same.

Please refer to FIG. 14 , which is a schematic circuit diagram of another preferred embodiment of the present invention. The implementation of this pixel circuit can be used for large-sized panels and can be used for mesh routing and effectively reduce signal delay and voltage drop (IR drop). )And other issues. FIG. 14 shows a circuit diagram of the pixel circuit of this embodiment, including: a driving transistor 60 , an organic light emitting diode 61 , and a voltage control unit 62 . The organic light emitting diode 61 includes an anode terminal 611 and a cathode terminal 612, wherein the cathode terminal 612 is connected to a first voltage source VSS for providing a first voltage Vss. The driving transistor 60 is preferably an N-type transistor, which includes a first node 601 , a second node 602 and a third node 603 , wherein the first node 601 is the drain terminal, the second node 602 is the gate terminal, and the third node 602 The node 603 is the source terminal, the first node 601 is electrically connected to a second voltage source VDD for providing a second voltage Vdd, and the third node 603 is connected to the anode terminal 611 .

The aforementioned voltage control unit 62 includes a first transistor 67 , a second transistor 68 , a fourth transistor 69 , a storage capacitor 66 and a coupling capacitor 65 . The first transistor 67 has a first end 671 connected to a data driving line Data, a second end 672 connected to a first control signal source SN for providing a first control signal, and a second node 602 third end 673. The second transistor 68 has a first terminal 681 , a second terminal 682 connected to a second control signal source SW for providing a second control signal, and a third terminal connected to the anode terminal 611 and the third node 603 683. The first and second transistors 67 and 68 are preferably N-type transistors. The storage capacitor 66 has a first terminal 661 connected to a third voltage source REF and a second terminal 662 connected to the first terminal 681 of the second transistor 68 . The coupling capacitor 65 has a first terminal 651 connected to the first terminal 681 of the second transistor 68 and a second terminal 652 connected to the second node 602 . The fourth transistor 69 has a first terminal 691 connected to the anode terminal 611 and the third node 603, a second terminal 692 connected to a fourth control signal source RST, and a third terminal 693 connected to a fifth voltage source. Accordingly, when the pixel circuit is in a reset stage, the first control signal source SN provides a first control signal to turn on the first transistor 67 , and the second control signal source SW provides a second control signal to turn on the second transistor 68 , the fourth control signal source RST provides a fourth control signal to turn on the fourth transistor 69, the data driving line Data inputs a first reference voltage VR1 to the driving transistor 60 to reset the second node 602, the fifth voltage source inputs a first reference voltage VR1 The two reference voltages Vref are applied to the fourth transistor 69 to reset the third node 603 and the first end 651 of the coupling capacitor 65. When the pixel circuit is in a compensation stage, the data driving line Data inputs a third reference voltage VR2 to the second node 602, the third node 603 and the storage capacitor 66 store the difference between the third reference voltage VR2 of the driving transistor 60 and a threshold voltage Vt, the driving transistor 60 is turned from the on state to the off state, when the pixel circuit is in a data writing stage , the data driving line Data inputs a data voltage to the driving transistor 60, the difference between the third reference voltage VR2 and the data voltage is coupled to the first end 651 of the coupling capacitor 65, when the pixel circuit is in a light-emitting stage, the threshold voltage Vt and the organic A voltage of the light emitting diode 61 is coupled to the second node 602, wherein the aforementioned reset phase, compensation phase, data writing phase and light-emitting phase are sequentially repeated.

Please also refer to FIG. 15 , which is a working timing diagram of a preferred embodiment of the pixel circuit of FIG. 14 . Its circuit operation is divided into a reset (Reset) stage, a compensation (Comp.) stage, a data writing (Prog.) stage and an emitting (Emitting) stage, and the driving transistor 60, the first transistor 67, the second transistor 68, the first The on or off states of the four transistors 69 and the organic light emitting diode 61 are shown in Table 4, as well as the voltage (V _G ) of the second node 602 of the driving transistor 60 and the voltage (V _S ) of the anode terminal 611 of the organic light emitting diode 61 , the voltage of the first terminal 651 of the coupling capacitor 65 (V _N ), the voltage difference between the second node 602 and the anode terminal 611 (V _GS ), and the voltage difference between the second node 602 and the first terminal 651 of the coupling capacitor 65 (V _GN ) as shown in Table 5.

Table 4

table 5

Accordingly, in the reset stage, the first transistor 67 , the second transistor 68 and the fourth transistor 69 are turned on, the driving transistor 60 and the organic light emitting diode 60 are turned off, and the data driving line (Data) is input with a first The reference voltage VR1 is at the first terminal 671 of the first transistor 67, and the second node 602 is reset to the first reference voltage VR1 through the third terminal 673 of the first transistor 67, while the fifth voltage source inputs a second reference voltage Vref (may also be Vdata) goes to the third terminal 693 of the third transistor 695, and passes through the first terminal 691 of the third transistor 695 to reset the third node 603 and the first terminal 651 of the coupling capacitor 65 and satisfy VR1<Vref +Vt so that no DC current path occurs during the reset phase.

During the compensation stage, the first transistor 67 and the second transistor 68 are turned on, and the driving transistor 60, the fourth transistor 69 and the organic light emitting diode 61 are turned off. The data driving line (Data) inputs a third reference voltage VR2 at The first terminal 671 of the first transistor 67 resets the second node 602 to the third reference voltage VR2 through the third terminal 673 of the first transistor 67, so that the driving transistor 50 is gradually discharged from the on state to the off state, so that the organic The anode terminal 611 of the light emitting diode 61 is discharged to VR2-Vt to measure the threshold voltage Vt of the driving transistor 60 and the third node 603 and the storage capacitor 66 store the difference between the third reference voltage VR2 of the driving transistor 60 and the threshold voltage Vt .

As shown in FIG. 15 , there is an interval time (T_space) after the compensation phase, which is an interval time between the compensation phase and the data writing phase, and the interval time is greater than or equal to zero.

During the data writing stage, the first transistor 67 is on, and the driving transistor 60, the second transistor 68, the fourth transistor 69, and the organic light emitting diode 61 are off, and a data voltage Vdata is input to the data driving line (Data). At the first end 671 of the first transistor 67 and through the third end 673 of the first transistor 67, the second node 602 is reset to the data voltage Vdata, and the voltage VN of the first end 651 of the coupling capacitor 65 passes through the coupling capacitor 65 coupled to:

V _N =VR2-Vt+(Vdata-VR2)*f1

=VR2*(1-f1)+Vdata*f1-Vt, -----(10)

The voltage difference between the second node 602 and the first end 651 of the coupling capacitor 65 is:

V _GN =Vdata-(VR2(1-f1)+Vdata*f1-Vt)

=(Vdata-VR2)*(1-f1)+Vt, -----(11)

where f1=Ccp/(Ccp+Cst), Ccp is the capacitance value of the coupling capacitor 65 and Cst is the capacitance value of the storage capacitor 66 . At the same time, the organic light emitting diode 61 cannot be turned on, so the anode terminal (V _S ) of the organic light emitting diode should be smaller than the turn-on voltage Voled (0) of the organic light emitting diode 61 and the first terminal (V _N ) of the coupling capacitor should be smaller than the anode terminal of the organic light emitting diode 61. extreme (V _S ), so the following conditions can be deduced:

Voled(0)+Vt>Vdata>VR2, -----(12).

In the light-emitting stage, the driving transistor 60 , the second transistor 68 and the organic light emitting diode 61 are in an on state, and the first transistor 67 and the fourth transistor 69 are in an off state, at this time the anode terminal 611 and the first terminal 651 of the coupling capacitor 65 Both are the voltage Voled of the organic light emitting diode 61 , and the coupling capacitor 65 couples the voltage Voled of the organic light emitting diode 61 to the second node 602 :

V _G =Vdata+(Voled-(VR2*(1-f1)+Vdata*f1-Vt))

=(Vdata-VR2)*(1-f1)+Vt+Voled, -----(13)

The voltage difference between the second node 602 and the anode terminal 611 is:

V _GS = (Vdata-VR2)*(1-f1)+Vt, -----(14)

Therefore, the output current I _oled of the driving transistor 60 can be expressed as:

I _oled =Kp*(VGS-Vt) ²

=Kp*[(Vdata-Vref)*(1-f1)] ² , -----(15)

Wherein, Kp=1/2(μ*COX)(W/L), μ is the carrier mobility of the driving transistor 60 , COX is the capacitance per unit area of the driving transistor 60 , (W/L) is the width of the driving transistor 60 length ratio, and it can be seen from equation (15) that the output current of the driving transistor 60 has nothing to do with the threshold voltage Vt and the voltage Voled of the organic light emitting diode 61, and not only compensates the threshold voltage of the transistor, the voltage of the active matrix organic light emitting diode, At the same time, it also meets the needs of high precision and high aperture ratio.

The present invention also provides another method for driving a pixel circuit. Referring to the pixel circuit shown in FIG. 14, the method includes the steps of: (A) in a reset stage, the data driving line Data inputs a first reference The voltage VR1 is applied to the driving transistor 60 to reset the second node 602, and the fifth voltage source inputs a second reference voltage Vref to the third transistor 69 to reset the third node 603 and the first terminal 651 of the coupling capacitor 65; (B) In a compensation stage, the data driving line Data inputs a third reference voltage VR2 to the driving transistor 60 to reset the second node 602 . The third node 603 and the storage capacitor 66 store the third reference voltage VR2 and the threshold voltage of the driving transistor 60 The difference value of Vt, the driving transistor 60 changes from the ON state to the OFF state; (C) During a data writing stage, the data driving line Data inputs a data voltage Vdata to the driving transistor 60, the third reference voltage VR2 and the data voltage are The difference is coupled to the first terminal 651 of the coupling capacitor 65 ; and (D) in a light-emitting stage, the threshold voltage Vt and a voltage of the organic light emitting diode 61 are coupled to the second node 602 .

Please refer to FIG. 16 , which is a schematic diagram of a display panel using the pixel circuit of FIG. 14 according to another preferred embodiment of the present invention. It includes: a plurality of pixel circuits 90 , a data driver 91 , a scan driver 92 and 93 , and a timing controller 84 . The plurality of pixel circuits 90 are arranged into a pixel circuit matrix according to a plurality of rows and columns; the data driver 91 has a plurality of data driving lines (Data_1, Data_2, Data_3, . . . ) for connecting the pixel circuit matrix A plurality of pixel circuits 90 in a row to provide at least one input voltage; the scan driver 92 has a plurality of scan driving lines (SN_1, SW_1, SN_2, SW_2, SN_3, SW_3, . . . ) for connecting a plurality of pixel circuits 90 in a row of the pixel circuit matrix to provide at least one switching voltage; the scan driver 93 has a plurality of reset signal driving lines (RST_1, RST_1, RST_2, RST_3, . . An embodiment is shown in FIG. 17 , which is a timing diagram of a preferred embodiment of the display panel of FIG. 16 with row 1 of the pixel circuit matrix as a display unit, wherein the display panel is a display unit with row 1 of the pixel circuit matrix. The reset phase, the compensation phase, the data writing phase, and the light-emitting phase of each display unit are performed sequentially, and each display unit is performed sequentially.

Please refer to FIG. 18 at the same time, which is a working timing diagram of a preferred embodiment of the display panel of FIG. 16 with three columns of a pixel circuit matrix as a display unit. An embodiment is shown in FIG. 18 , the difference from FIG. 15 is that in the data writing stage, the scan driver 92 sequentially turns on the plurality of pixel circuits 90 in each column of the display unit via the scan driving lines (SN_1, SN_2, SN_3). The first transistor 97 simultaneously inputs a data voltage group Vdata(1, 2, 3) to the data driving line Data(m), and the data voltage group Vdata(1, 2, 3) sequentially inputs a data voltage to a plurality of each row The first transistor 67 of the pixel circuit 90, the data voltage group Vdata (1, 2, 3) corresponds to the first transistors 67 of the pixel circuits 90 in each column that are sequentially turned on by the scan driving lines (SN_1, SN_2, SN_3). A data voltage is sequentially input to the first transistors 67 of the plurality of pixel circuits 90 in each row, and the rest are the same. After the display unit completes the reset phase, the compensation phase, the data writing phase and the light-emitting phase, the next display unit proceeds in sequence.

Please refer to FIG. 19 at the same time, which is a working timing diagram of a preferred embodiment of the display panel of FIG. 16 with n columns of the pixel circuit matrix as a display unit, which is similar to the working timing of FIG. For a display unit, the n columns of the pixel circuit matrix are changed into a display unit, and the rest are the same and will not be repeated here.

The above-mentioned embodiments are only examples for convenience of description, and the scope of the rights claimed in the present invention should be based on the scope of the claims, rather than being limited to the above-mentioned embodiments.

Claims (1)

1. A display panel, comprising:

a plurality of pixel circuits arranged in a pixel circuit matrix in a plurality of rows and columns;

a data driver having a plurality of data driving lines for connecting a plurality of pixel circuits of the columns of the pixel circuit matrix to provide at least one input voltage;

a first scan driver having a plurality of scan driving lines perpendicularly intersecting the plurality of data driving lines for connecting a plurality of pixel circuits of a row of the pixel circuit matrix to provide at least one switching voltage;

a second scan driver having a plurality of reset signal driving lines perpendicularly intersecting the plurality of data driving lines for connecting a plurality of pixel circuits of a row of the pixel circuit matrix to provide at least one switching voltage; and

a timing controller connected to and controlling the data driver, the first scan driver and the second scan driver, respectively,

each pixel circuit includes:

an organic light emitting diode including an anode terminal and a cathode terminal, the cathode terminal being connected to a first voltage source;

a driving transistor for driving the organic light emitting diode, the driving transistor including a first node, a second node and a third node, the first node being connected to a second voltage source, the third node being connected to the anode terminal;

a first transistor including a first terminal connected to one of the data driving lines, a second terminal connected to a first control signal source, and a third terminal connected to the second node;

a second transistor including a first terminal, a second terminal connected to a second control signal source, and a third terminal connected to the anode terminal and the third node;

a storage capacitor including a first terminal connected to a third voltage source and a second terminal connected to the first terminal of the second transistor;

a fourth transistor including a first terminal connected to the anode terminal and the third node, a second terminal connected to a fourth control signal source, and a third terminal connected to a fifth voltage source; and

a coupling capacitor including a first terminal connected to the first terminal of the second transistor and a second terminal connected to the second node;

wherein, during a reset phase, the first control signal source provides a first control signal to turn on the first transistor, the second control signal source provides a second control signal to turn on the second transistor, the fourth control signal source provides a fourth control signal to turn on the fourth transistor, the data driving line inputs a first reference voltage to the driving transistor to reset the second node, the fifth voltage source inputs a second reference voltage to the fourth transistor to reset the third node and the first end of the coupling capacitor, during a compensation phase, the data driving line inputs a third reference voltage to the second node, the third node and the storage capacitor store a difference between the third reference voltage of the driving transistor and the threshold voltage of the driving transistor, the driving transistor is turned from on state to off state, the data driving line inputs a data voltage to the driving transistor during a data writing phase, a difference between the third reference voltage and the data voltage is coupled to the first end of the coupling capacitor, and the threshold voltage and a voltage of the organic light emitting diode are coupled to the second node during a light emitting phase.

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