KR20170007574A - OLED driving current compensation circuit and Organic Light Emitting Display device comprising the same - Google Patents

Abstract

In an OLED driving circuit compensation circuit according to the present invention, as can be seen from a relationship equation of a final driving current (I_(OLED)) flowing through an OLED during a light emitting period of I_(OLED)=k(Vsg-Vth)^2=k(V_(data)+Vth-V_(OLED)-Vth)^2=k(Vdata-V_(OLED))^2, the driving current (I_(OLED)) is proportional to a difference between a source electrode voltage (Vs) and a gate electrode voltage (Vg) of a driving TFT and a difference between threshold voltages (Vth) so that the final driving current (I_(OLED_) relationship becomes k(Vdata-V_(OLED)) through a sampling period (Ps). Through this, the driving current (I_(OLED)) is influenced only by k and a difference between a data voltage (Vdata) and an OLED driving voltage (V_(OLED)) and is not influenced by a first external voltage (ELVDD). The OLED driving current compensation circuit includes first to sixth TFTs and a storage capacitor.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an OLED driving current compensation circuit and an organic light emitting display including the OLED driving current compensation circuit,

The present invention relates to an active matrix type OLED driving current compensation circuit and an organic light emitting display including the OLED driving current compensation circuit.

The active matrix type organic light emitting display device includes an organic light emitting diode (OLED) which emits light by itself, has a high response speed, and has a high luminous efficiency, luminance, and viewing angle.

The OLED, which is a self-luminous element, has the structure shown in FIG. The OLED includes an anode electrode and a cathode electrode, and organic compound layers (HIL, HTL, EML, ETL, EIL) formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

The organic light emitting display device arranges the OLED driving current compensation circuits including the OLEDs in a matrix form and adjusts the luminance of the OLED driving current compensation circuits according to the gradation of the video data. Each of the OLED driving current compensation circuits includes a driving TFT (Thin Film Transistor) for controlling the driving current I _OLED flowing in the OLED according to the gate-source voltage, a constant gate-source voltage of the driving TFT for one frame And at least one switch TFT for setting the gate-source voltage of the driving TFT in response to the gate signal. Driving current (I _OLED) is a relational expression _{(I OLED = k (Vsg-} Vth) 2) unknown, as the gate of a driving TFT according to the data voltage in-and-source voltage and the threshold voltage of the driving TFT, and the electron mobility of the driving TFT (K indicates the proportionality constant determined by the electron mobility, parasitic capacitance, channel capacity, etc. of the TFT).

As the OLED is driven, the threshold voltage of the TFT is uneven, which causes a change in the driving current, as can be seen from the driving current relation. To compensate for such unevenness characteristics, an OLED driving current compensation circuit is used. Such an OLED driving current compensation circuit includes a plurality of TFTs in a pixel.

FIG. 2 is a view showing a structure of a conventional compensation circuit, and FIG. 3 is a diagram showing driving signals provided to the OLED driving current compensation circuit shown in FIG.

Referring to FIGS. 2 and 3, the operation of the conventional OLED driving current compensation circuit is as follows.

One frame period includes a setup period data [m-1] for initializing the node A, a sampling period data [m] for sampling the threshold voltage of the drive TFT (D-TFT) Source voltage of the driving TFT (D-TFT) including the threshold voltage to be set, and a light emission period (data [m + 1]) for emitting the OLED by the driving current according to the set gate- Can be divided.

T4 and T6 are turned on in the initialization period (data [m-1]) to initialize the node A to the initializing voltage Vint. T1 and T3 are turned ON in the sampling period (data [m]), and A node is sampled at Vdata-Vth. T2 and T5 are turned on in the light emission period data [m + 1], and consequently the driving current I _OLED flowing through the _OLED satisfies the following formula (1).

[Equation 1]

I _OLED = k (Vsg-Vth) ² = k (Vs-Vg-Vth) ² = k (ELVDD-Vdata + Vth-Vth) ²

= k (ELVDD-Vdata) ²

The conventional OLED driving current compensation circuit is not influenced by the threshold voltage Vth as shown in Equation (1), but the OLED driving current compensation circuit of the related art does not affect the driving current flowing in the OLED The current I _OLED is affected by the first external voltage ELVDD and the driving current I _OLED is uneven and the luminance is proportional to the driving current I _OLED , do. In addition, as shown in FIG. 2, since seven TFTs, one capacitor, and initialization voltage (Vint) wiring are required, high integration is required.

Therefore, an OLED driving current compensation circuit which realizes a high degree of integration by reducing the number of TFTs in each OLED driving current compensation circuit and whose driving current is not influenced by the first external voltage ELVDD in the light emission period, Emitting display device.

The driving current I _OLED flowing through the OLED during the light emission period is affected only by the difference between k and the data voltage Vdata and the OLED driving voltage V _OLED , The first and second electrodes of the first TFT T1 are connected to the mth data line data [m] and the node N2, respectively, and the gate electrode of the first TFT T1 is connected to the nth scan line Scan [n] The first and second electrodes of the second TFT T2 are connected to the third TFT T3 and the node N2 respectively and the gate electrode thereof is connected to the node N1 and the first and second electrodes of the third TFT T3, Are connected to the node N1 and the second TFT T2 respectively and the gate electrode thereof is connected to the nth scan line Scan [n], and the first and second electrodes of the fourth TFT T4 are connected to the first external voltage And the gate electrodes are connected to the nth emission line EM [n], and the first and second electrodes of the fifth TFT T5 are connected to the nodes N2 and N3, respectively, Connected to the anode electrode of the OLED, The first and second electrodes of the sixth TFT T6 are connected to the first external voltage ELVDD, the second external voltage ELVSS, or the initialization voltage ELV [n] 1) and the storage capacitor Cst is connected between the node N1 and the first external voltage ELVDD line, and the storage capacitor Cst is connected between the node N1 and the first external voltage ELVDD line. .

During the initialization period, only the (n-1) th scan signal is input as the high level voltage and the sixth TFT is turned on to charge the node N1 with the first external voltage ELVDD.

During the sampling period, only the nth scan signal is input as a high level voltage and the first and third TFTs are turned on to charge Vdata + Vth at the node N1 and the data voltage Vdata at the node N2, respectively.

Only the nth emission signal is input as the high level voltage and the fourth and fifth TFTs are turned on so that the node N1 is held at Vdata + Vth and the node N2 is charged with the OLED driving voltage V _OLED .

Since the present invention has a compensation circuit composed of six transistors and one capacitor, it is easy to realize high integration. In addition, by configuring the OLED driving current compensation circuit which is not influenced by the first external voltage ELVDD, it is possible to compensate for the unevenness of the driving current I _OLED and finally to compensate for the unevenness of the luminance.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing an OLED and its luminescence principle. Fig.
2 is an equivalent circuit diagram showing a structure of a compensation circuit of the prior art.
FIG. 3 is a waveform diagram showing a driving signal applied to the compensation circuit of FIG. 2; FIG.
4 is an organic light emitting display according to an embodiment of the present invention.
5 is an equivalent circuit diagram showing one compensation circuit structure of the present invention.
6 is a waveform diagram showing a driving signal applied to the compensation circuit of FIG. 5;
7, 8 and 9 are equivalent circuit diagrams of a compensation circuit according to the drive signal of Fig. 6, respectively.
10 is a diagram showing the potential of each node corresponding to the operation period of the compensation circuits;
Figs. 11 and 12 are equivalent circuit diagrams showing one modification of the compensation circuit structure shown in Fig. 5; Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In the embodiment of the present invention, only the transistors constituting the compensation circuit are all of the N type. However, the technical idea of the present invention is not limited to this, but may be applied to the case of the P type.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 to 12. FIG.

FIG. 4 illustrates an organic light emitting display according to an embodiment of the present invention.

4, the OLED display includes a display panel 10 having compensation circuits PXL, a data driving circuit 12 for driving the data lines 14, A gate driving circuit 13 for driving the gate lines 15 and a timing controller 11 for controlling the driving timing of the data driving circuit 12 and the gate driving circuit 13. [

In the display panel 10, a plurality of data lines 14 and a plurality of gate lines 15 cross each other, and the compensation circuits PXL are arranged in a matrix form for each of the intersection areas. The compensation circuits PXL arranged on the same horizontal line form one compensation circuit row. The compensation circuits PXL arranged in the one-compensation circuit row are connected to one gate line 15, and one gate line 15 may include at least one scan line and at least one emission line. That is, each compensation circuit PXL may be connected to one data line 14 and at least one scan line and an emission line. The compensation circuits PXL may receive the high potential and the second external voltages ELVDD and ELVSS and the initialization voltage Vinit in common from a power source not shown. The initialization voltage Vinit is preferably selected within a voltage range sufficiently lower than the operating voltage of the OLED so that unnecessary light emission of the OLED is prevented in the initialization period and the sampling period and can be set to be equal to or lower than the second external voltage ELVSS have.

The TFTs constituting the compensation circuit PXL may be implemented as an oxide TFT including an oxide semiconductor layer. The oxide TFT is advantageous for large-sized display panel 10 when considering both electron mobility and process variations. However, the present invention is not limited to this, and the semiconductor layer of the TFT may be formed of amorphous silicon, polysilicon, or the like.

Each compensation circuit PXL includes a plurality of TFTs and a storage capacitor for compensating for a change in threshold voltage of the driving TFT. The present invention is a compensation circuit for increasing the degree of integration and easily compensating the IR drop of the first external voltage We propose a circuit structure. This will be described in detail later with reference to FIG. 4 to FIG.

The timing controller 11 rearranges the digital video data RGB input from the outside in accordance with the resolution of the display panel 10 and supplies the digital video data RGB to the data driving circuit 12. The timing controller 11 is also connected to the data driving circuit 12 based on timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock signal DCLK and a data enable signal DE, A data control signal DDC for controlling the operation timing of the gate driving circuit 13 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13. [

The data driving circuit 12 converts the digital video data RGB input from the timing controller 11 into an analog data voltage based on the data control signal DDC.

The gate driving circuit 13 may generate a scan signal and an emission signal based on the gate control signal GDC. The gate drive circuit 13 may include a scan driver and an emission driver. The scan driver may generate a scan signal in a row sequential manner to supply at least one scan line connected to each compensation circuit row to the scan lines. The emission driving unit may generate an emission signal in a row-sequential manner to supply at least one emission line connected to each compensation circuit row to the emission lines.

The gate drive circuit 13 may be formed directly on the non-display area of the display panel 10 in accordance with a GIP (Gate-Driver In Panel) method.

5 is an equivalent circuit diagram showing a compensation circuit structure of the present invention. 6 is a waveform diagram showing signals applied to the compensation circuit of FIG. 5. FIG.

5, each compensation circuit PXL disposed in the n-th (n is a natural number) compensation circuit row includes an OLED, a first TFT T1, a second TFT T2, a third TFT T3, A fourth TFT T4, a fifth TFT T5, a sixth TFT T6, and a storage capacitor Cst.

As shown in FIG. 1, a multi-layer organic compound layer is formed between the anode electrode and the cathode electrode of the OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). The anode electrode of the OLED is connected to the fifth TFT (T5), and its cathode electrode is connected to the input terminal of the second external voltage ELVSS.

The first and second electrodes of the first TFT T1 are connected to the mth data line data [m] and the node N2, respectively, and the gate electrode thereof is connected to the nth scan line Scan [n]. That is, the first TFT T1 connects the mth data line data [m] and the node N2 in response to the nth scan signal.

The first and second electrodes of the second TFT T2 are connected to the third TFT T3 and the node N2, respectively, and the gate electrode thereof is connected to the node N1.

The first and second electrodes of the third TFT T3 are connected to the node N1 and the second TFT T2 respectively and the gate electrode thereof is connected to the nth scan line Scan [n]. That is, the third TFT T3 connects the node N1 and the first electrode of the second TFT T2 in response to the n-th scan signal.

The first and second electrodes of the fourth TFT T4 are connected to the first external voltage ELVDD line and the third TFT T3 respectively and the gate electrode thereof is connected to the nth emission line EM [n] do. That is, the fourth TFT T4 provides the first external voltage ELVDD to the second electrode of the third TFT T3 in response to the nth emission signal.

The first and second electrodes of the fifth TFT T5 are respectively connected to the node N2 and the anode electrode of the OLED, and the gate electrode thereof is connected to the nth emission line EM [n]. That is, the fifth TFT T5 provides current to the OLED in response to the nth emission signal.

The first and second electrodes of the sixth TFT T6 are respectively connected to the first external voltage ELVDD line and the node N1 and the gate electrode thereof is connected to the n-1th scan line Scan [n-1] . That is, the sixth TFT T6 provides the first external voltage ELVDD to the node N1 in response to the (n-1) th scan signal.

The storage capacitor Cst is connected between the node N1 and the first external voltage ELVDD line. The storage capacitor Cst is used to sample the threshold voltage of the second TFT T2 according to a source-follower scheme.

In the first embodiment, the operation of the compensation circuit arranged in the nth compensation circuit row will be described with reference to Fig. 6, Figs. 7 to 9, and Fig. Figs. 7 to 9 are equivalent circuit diagrams of the compensation circuit according to the driving signals, and Fig. 10 is a diagram showing potentials of the respective nodes corresponding to the operation periods of the compensation circuits.

Since the first TFT (T1) to the sixth TFT (T6) of the first embodiment are implemented as N-type TFTs, the high level voltage of each driving signal means the turn-on signal of the TFTs, The voltage means the turn-off voltage of the TFTs.

One frame period includes an initializing period Pi for initializing the node N1, a sampling period Ps for sampling the threshold voltage of the driving TFT T2 and storing the sampled threshold voltage at the node N1, And a light emission period Pe for driving the OLED by a driving current corresponding to the set gate-source voltage.

the initialization period Pi of the compensation circuits arranged in the n compensation circuit rows is performed during the (n-1) th horizontal period (1H) for supplying the data voltage to the (n-1) th compensation circuit row.

During the initialization period Pi, the (n-1) th scan signal is input to the high level voltage, and the nth scan signal and the nth emission signal are input to the low level voltage. Accordingly, the sixth TFT T6 is turned on by the (n-1) th scan signal to charge the first external voltage ELVDD to the node N1.

The sampling period Ps is performed during the n-th horizontal period (1H) for inputting the data voltage to the compensation circuits arranged in the n-th compensation circuit row.

During the sampling period Ps, the n-1 scan signal is inverted to the low level voltage, the nth scan signal is inverted to the high level voltage, and the nth emission signal is maintained at the low level voltage.

As the n-1 scan signal is inverted to a low level, the sixth TFT (T6) is turned off, and the current path between the first external voltage (ELVDD) line and the node N1 is cut off.

During the sampling period Ps, the first TFT T1 is turned on by the n-th scan signal and the m-th data line data [m] is connected to the node N2. Accordingly, the data voltage Vdata is charged to the node N2.

During the sampling period Ps, the third TFT T3 is turned on by the nth scan signal, and the Vdata corresponding to the sum of the data voltage Vdata of the node N2 and the threshold voltage Vth of the driving TFT T2 A voltage of + Vth level is charged to the node N1.

The light emission period Pe continues from the sampling period Ps to the initialization period Pi of the next frame.

During the light emission period Pe, the (n-1) th scan signal is maintained at the low level voltage, and the n th scan signal and the n th emission signal are inverted to the low level voltage and the high level voltage, respectively.

The fourth TFT T4 and the fifth TFT T5 are turned on by the nth emission signal to charge the OLED driving voltage V _OLED to the node N2. Therefore, the node N2 charged with the data voltage Vdata during the sampling period Ps is changed from the light emitting period Pe to the OLED driving voltage V _OLED . On the other hand, the node N1 is still maintained at Vdata + Vth in the light emission period Pe.

As a result, a relational expression for the driving current I _OLED flowing through the OLED during the light emission period Pe is expressed by the following equation (2).

&Quot; (2) "

_{I OLED = k (Vsg-Vth} ) 2 = k (Vdata + Vth- V OLED -Vth) 2 = k (Vdata-V OLED) 2

In Equation (2), k indicates a proportional constant determined by electron mobility, parasitic capacitance, channel capacitance, and the like of the driving TFT (T2).

The OLED can display a desired gradation by emitting light according to this driving current relationship. That is, with reference to the k (Vsg-Vth) the driving current (I _OLED) relationship of the OLED ² driving current of the OLED is different from the threshold voltage between the source electrode voltage (Vs) and a gate electrode voltage (Vg) of the driving TFT (Vth ) driving current (I _OLED) found to be proportional to the difference, and a final driving current (I _OLED) relation with the sampling period (Ps) is the k (Vdata-V _OLED) through which between the voltage k and data ( Vdata and the OLED driving voltage V _OLED and is not influenced by the first external voltage ELVDD.

11 is a diagram showing a compensation circuit structure according to the second embodiment.

Referring to Fig. 11, the compensation circuit PXL [n, m] arranged in the mth compensation circuit row in the nth compensation circuit row will be described below. Hereinafter, a detailed description of a configuration substantially the same as that of the above-described embodiment in the second embodiment will be omitted.

Referring to Fig. 11, the compensation circuit PXL [n, m] arranged in the mth compensation circuit row in the nth compensation circuit row will be described below.

The compensation circuit PXL [n, m] includes an OLED, a first TFT T1 to a sixth TFT T6, and a storage capacitor Cst. In the embodiment of the present invention, each transistor is implemented as N type, but the semiconductor type of each transistor is not limited thereto. If the first transistor T1 through the sixth transistor T6 are implemented as a P type, the driving signals shown in FIG. 6 must be inverted.

The difference from the first embodiment of the second embodiment is that the sixth TFT T6 is connected to the second external voltage ELVSS instead of the first external voltage ELVDD.

The operation according to the initialization period Pi, the sampling period Ps, and the light emission period Pe will be described with reference to FIG.

During the initialization period Pi, the (n-1) th scan signal is input to the high level voltage, and the nth scan signal and the nth emission signal are input to the low level voltage. Accordingly, the sixth TFT T6 is turned on by the (n-1) th scan signal to charge the second external voltage ELVSS to the node N1.

During the sampling period Ps, the n-1 scan signal is inverted to the low level voltage, the nth scan signal is inverted to the high level voltage, and the nth emission signal is maintained at the low level voltage.

As the n-1 scan signal is inverted to a low level, the sixth TFT (T6) is turned off, and the current path between the second external voltage (ELVSS) line and the node N1 is cut off.

The operation of the following sampling period Ps and the light emission period Pe is the same as that of the first embodiment and consequently the drive current Ioled flowing in the OLED during the light emission period Te also has the same relation.

12 is a diagram showing a compensation circuit structure according to the third embodiment.

Referring to Fig. 12, the compensation circuit PXL [n, m] arranged in the mth compensation circuit row in the nth compensation circuit row will be described below. Hereinafter, detailed descriptions of the substantially same configurations as those of the above-described embodiments in the first and second embodiments will be omitted.

The compensation circuit PXL [n, m] includes an OLED, a first TFT T1 to a sixth TFT T6, and a storage capacitor Cst. In the embodiment of the present invention, each transistor is implemented as N type, but the semiconductor type of each transistor is not limited thereto. If the first transistor T1 through the sixth transistor T6 are implemented as a P type, the driving signals shown in FIG. 6 must be inverted.

The difference from the first and second embodiments of the third embodiment is that the sixth TFT T6 is connected to the initialization drive voltage Vinit.

The operation according to the initialization period Pi, the sampling period Ps, and the light emission period Pe will be described with reference to FIG.

During the initialization period Pi, the (n-1) th scan signal is input to the high level voltage, and the nth scan signal and the nth emission signal are input to the low level voltage. Accordingly, the sixth TFT T6 is turned on by the (n-1) th scan signal to charge the initialization voltage Vinit to the node N1.

During the sampling period Ps, the n-1 scan signal is inverted to the low level voltage, the nth scan signal is inverted to the high level voltage, and the nth emission signal is maintained at the low level voltage.

As the n-1 scan signal is inverted to a low level, the sixth TFT (T6) is turned off, and the current path between the initialization voltage (Vinit) line and the node N1 is cut off.

The operation of the following sampling period Ps and the light emission period Pe is the same as that of the first embodiment. As a result, the same relationship is obtained also in the driving current Ioled flowing in the OLED during the light emission period Pe.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
14: Data line 15: Gate line

Claims (9)

A first TFT connected to the data line and switched by the nth scan signal;
A driving TFT connected to a first node connected to the first TFT;
A third TFT connected to a second node connected to the driving TFT and switched by the nth scan signal;
A fourth TFT connected to the first external voltage and switched by the nth emission signal;
A fifth TFT connected to the first node and switched by the nth emission signal;
A sixth TFT connected to the first node and the second node and switched by an n-1 scan signal;
And a storage capacitor coupled to the first external voltage and the second node.
The method according to claim 1,
And the sixth TFT charges the first external voltage to the second node by the (n-1) th scan signal during the initialization period.
3. The method of claim 2,
And the first TFT charges the data voltage to the first node by the nth scan signal during a sampling period.
The method of claim 3,
And the third TFT charges the sum of the threshold voltage of the driving TFT and the data voltage to the second node by the nth scan signal during the sampling period.
5. The method of claim 4,
And the fifth TFT charges the OLED driving voltage to the first node by the nth emission signal during a light emission period.
A first TFT connected to the data line and switched by the nth scan signal;
A driving TFT connected to a first node connected to the first TFT;
A third TFT connected to a second node connected to the driving TFT and switched by the nth scan signal;
A fourth TFT connected to the first external voltage and switched by the nth emission signal;
A fifth TFT connected to the first node and switched by the nth emission signal;
A sixth TFT connected to the second node and the second node and switched by an n-1 scan signal;
And a storage capacitor coupled to the first external voltage and the second node.
A first TFT connected to the data line and switched by the nth scan signal;
A driving TFT connected to a first node connected to the first TFT;
A third TFT connected to a second node connected to the driving TFT and switched by the nth scan signal;
A fourth TFT connected to the first external voltage and switched by the nth emission signal;
A fifth TFT connected to the first node and switched by the nth emission signal;
A sixth TFT connected to the second node and switched by an n-1 scan signal;
And a storage capacitor coupled to the first external voltage and the second node.
During the initialization period, the first node is charged with the first external voltage ELVDD,
The data voltage is charged to the second node sequentially during the sampling period, and the first node is charged with the voltage obtained by adding the threshold voltage of the driving TFT to the data voltage,
And the driving current flowing through the OLED is not affected by the first external voltage (ELVDD) by charging the OLED driving voltage to the first node during the light emitting period.
An OLED driving current compensation circuit according to any one of claims 1 to 8;
A display panel having the OLED driving current compensation circuit;
A gate driving circuit for driving scan lines and emission lines of the display panel; And
And a data driving circuit for driving the data lines of the display panel.

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