KR102723500B1 - Display device - Google Patents

Abstract

A display device includes a display panel, a data driving circuit, a gate driving circuit, and a timing controller, wherein a pixel of the display panel includes a compensation circuit for compensating a first threshold voltage of a driving transistor, the data driving circuit generates sensing data according to an electric signal transmitted from the pixel through a data line, the timing controller generates a control signal for controlling operations of the data driving circuit and the gate driving circuit to drive a data frame by dividing it into a display stage for supplying data voltages to a plurality of pixels and a sensing stage for generating electric signals, and the gate driving circuit can adjust a second gate-on voltage of a first scan signal supplied to a gate electrode of the switching transistor in the sensing stage to be different from a first gate-on voltage of the first scan signal in the display stage so that the electric signal reflects a second threshold voltage of the switching transistor.

Description

DISPLAY DEVICE

This specification relates to a display device, and more particularly, to a display device that detects a threshold voltage of a switching transistor constituting a pixel circuit.

Flat panel displays include liquid crystal displays (LCDs), electroluminescence displays (ELDs), field emission displays (FEDs), and quantum dot display panels (QDs). Electroluminescence displays are divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. The pixels of an organic light emitting display include organic light emitting diodes (OLEDs), which are self-luminous light emitting elements, and emit light to display images.

An organic light-emitting display device arranges pixels, each including an OLED, in a matrix form and controls the amount of light emitted by the OLED according to the gradation of image data to adjust brightness. Each pixel circuit includes an OLED as a light-emitting element, a switching transistor or TFT (Thin Film Transistor) for controlling the application of a data voltage corresponding to the gradation, a driving transistor for controlling a pixel current flowing in the OLED according to a voltage applied between a gate electrode and a source electrode, and a capacitor for storing the data voltage, and may further include a plurality of switching transistors for detecting a threshold voltage of the driving transistor, controlling light emission, controlling initialization, etc.

Not only the driving transistor, but also the switching transistor that supplies the data voltage to the driving transistor may deteriorate. If the degree of deterioration of the switching transistor is different for each pixel and the threshold voltage is different, even if image data of the same grayscale is input, a problem may occur where the grayscale is not expressed uniformly because different data voltages are supplied to the driving transistor for each pixel.

The embodiments disclosed in this specification take this situation into account, and an object of this specification is to provide a display device for detecting and compensating for the threshold voltage of a switching transistor.

A display device according to one embodiment comprises: a display panel having a plurality of pixels, the display panel including a driving transistor for generating a current corresponding to a data voltage, a light-emitting element that emits light by the current, and a switching transistor for supplying the data voltage to the driving transistor, and a compensation circuit including a capacitor for compensating a first threshold voltage of the driving transistor; a data driving circuit for converting image data into data voltages and supplying the data voltages to the plurality of pixels through a plurality of data lines and generating sensing data according to electric signals transmitted from the pixels through the data lines; a gate driving circuit for supplying scan signals to the plurality of gate lines; and a timing controller for generating a control signal for controlling operations of the data driving circuit and the gate driving circuit so as to drive a data frame by dividing it into a display step for supplying the data voltages to the plurality of pixels and a sensing step for generating electric signals, wherein the gate driving circuit is characterized in that a second gate-on voltage of a first scan signal supplied to a gate electrode of the switching transistor during the sensing step is adjusted differently from a first gate-on voltage of a first scan signal during the display step so that the electric signal reflects a second threshold voltage of the switching transistor.

Therefore, it becomes possible to compensate for the deterioration of a switching transistor implemented with an oxide semiconductor element.

In addition, the threshold voltage of the switching transistor can be easily and accurately detected by voltage sensing through the data line.

In addition, it is possible to improve the display quality of an organic light-emitting display device by compensating for deterioration of the switching transistor.

Figure 1 is a block diagram of an organic light-emitting display device.
Figure 2 illustrates a pixel circuit using an oxide semiconductor for a switching transistor.
Figures 3 to 6 illustrate each step of driving the pixel circuit of Figure 2 while compensating for the threshold voltage of the driving transistor.
Fig. 7 illustrates a sensing circuit that detects the threshold voltage of a switching transistor included in the pixel circuit of Fig. 2.
Fig. 8 illustrates the operation of a switch connecting the pixel circuit of Fig. 2 and the sensing circuit of Fig. 7.
Fig. 9 illustrates the operation of the display stage for displaying an image on a pixel circuit in the circuit of Fig. 7.
Fig. 10 illustrates the operation of a sensing step for sensing a switching transistor included in a pixel circuit in the circuit of Fig. 7.
Figure 11 illustrates a timing chart for the control signal controlling the switching transistor in the sensing step of Figure 10 and the voltage of each node.
Figure 12 illustrates the operation of the first charging section in the timing chart of Figure 11, charging the data line to the V1 voltage.
Figure 13 illustrates the operation of the second charging section in which the data line is charged to the threshold voltage of the third switching transistor in the timing chart of Figure 11.
Figure 14 illustrates the operation of a sampling interval for sampling the threshold voltage of a third switching transistor charged to a data line.
Figure 15 illustrates the operation of sensing the threshold voltage of the second switching transistor.
Figure 16 illustrates the level of the control signal for controlling the second and third switching transistors in the display stage and the sensing stage and the configuration for generating the control signal.
Figure 17 illustrates an example of sensing the threshold voltage of a switching transistor included in a pixel connected to a data line arranged at the outermost end.
Figures 18a and 18b illustrate examples of sensing the threshold voltage of a switching transistor included in a pixel circuit while displaying part of the screen in a constant display mode.

Hereinafter, preferred embodiments will be described in detail with reference to the attached drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In the following description, if it is judged that a detailed description of a known function or configuration related to the contents of this specification may unnecessarily obscure or hinder the understanding of the contents, the detailed description will be omitted.

In a display device, the pixel circuit and the gate driving circuit may include at least one of an N-channel transistor (NMOS) and a P-channel transistor (PMOS). A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In the transistor, carriers start to flow from the source. The drain is an electrode from which carriers exit the transistor. In the transistor, the flow of carriers flows from the source to the drain. In the case of an N-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In the N-channel transistor, the direction of current flows from the drain to the source. In the case of a P-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the P-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as the first and second electrodes.

A scan signal (or gate signal) applied to the pixels swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than a threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, while it is turned off in response to the gate-off voltage. In the case of an N-channel transistor, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of a P-channel transistor, the gate-on voltage may be a gate low voltage (VGL), and the gate-off voltage may be a gate high voltage (VGH).

Each pixel of an organic light-emitting display device includes an OLED, which is a light-emitting element, and a driving element that supplies current to the OLED according to a gate-source voltage (Vgs) to drive the OLED. The OLED includes an anode, a cathode, and an organic compound layer formed between these electrodes. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), and the like. When current flows through the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML), thereby forming excitons, and as a result, the emission layer (EML) can emit visible light.

The driving element can be implemented with a transistor such as a MOSFET (metal oxide semiconductor field effect transistor). The driving transistor must have uniform electrical characteristics between pixels, but may differ between pixels due to process deviation and element characteristic deviation, and may change over the display driving time. In order to compensate for such electrical characteristic deviation of the driving transistor, an internal compensation method and/or an external compensation method may be applied to the organic light emitting display device. In the following embodiments, the internal compensation method is applied.

Recently, there have been increasing attempts to use oxide transistors, which use oxide semiconductor materials, in transistors that constitute pixel circuits of display devices, especially organic light-emitting display devices. Instead of silicon as a semiconductor material, oxide transistors use an oxide called IGZO, which combines In (indium), Ga (gallium), Zn (zinc), and O (oxygen).

Oxide transistors have lower electron mobility than low-temperature poly-silicon transistors, but are more than 10 times higher than amorphous silicon transistors, and their manufacturing cost is higher than that of amorphous silicon transistors, but much lower than that of low-temperature poly-silicon transistors.

In addition, since the manufacturing process of oxide transistors is similar to that of amorphous silicon transistors, existing equipment can be utilized, which provides an efficiency advantage. Therefore, oxide transistors are used in large liquid crystal displays that require high resolution and low power operation, or in OLED TVs that cannot accommodate the screen size with low-temperature polysilicon processes.

Fig. 1 is a block diagram of an organic light-emitting display device. The display device of Fig. 1 may include a display panel (10), a timing controller (11), a data driving circuit (12), a gate driving circuit (13), and a power supply (16).

The timing controller (11), data driving circuit (12), gate driving circuit (13), and power supply (16) of Fig. 1 may be integrated in whole or in part into the drive IC.

On the screen where the input image is expressed on the display panel (10), a plurality of data lines (14) running in the column direction (or vertical direction) and a plurality of gate lines (15) running in the row direction (or horizontal direction) intersect, and pixels (PXL) are arranged in a matrix form at each intersection area to form a pixel array.

The gate line (15) may include two or more lines for supplying two or more scan signals for applying the data voltage supplied to the data line (14) and the initialization voltage supplied to the initialization voltage line to the pixel, and a line for supplying a light-emitting signal for causing the pixel to light up.

The display panel (10) may further include a first power line for supplying a pixel voltage (or a high-potential driving voltage) (Vdd) to the pixels (PXL), a second power line for supplying a low-potential driving voltage (Vss) to the pixels (PXL), an initialization voltage line for supplying an initialization voltage (Vini) for initializing a pixel circuit, etc. The first/second power lines and the initialization voltage line are connected to a power supply unit (16). The second power line may be formed in the form of a transparent electrode covering a plurality of pixels (PXL).

Touch sensors may be arranged on the pixel array of the display panel (10). Touch input may be sensed using separate touch sensors or through pixels. The touch sensors may be implemented as in-cell type touch sensors arranged on the screen (AA) of the display panel (PXL) as an on-cell type or an add on type, or built into the pixel array.

In a pixel array, pixels (PXL) arranged in the same horizontal line are connected to one of the data lines (14), one or more of the gate lines (15), and form a pixel line. The pixel (PXL) is electrically connected to the data line (14) in response to a scan signal and an emission signal applied through the gate line (15), receives a data voltage, and causes the OLED to emit light with a current corresponding to the data voltage. Pixels (PXL) arranged in the same pixel line operate simultaneously according to the scan signal and the emission signal applied from the same gate line (15).

A pixel unit may be composed of, but is not limited to, three subpixels including a red subpixel, a green subpixel, and a blue subpixel, or four subpixels including a red subpixel, a green subpixel, a blue subpixel, and a white subpixel. Each subpixel may be implemented with a pixel circuit including an internal compensation circuit. Hereinafter, a pixel means a subpixel.

A pixel (PXL) may be supplied with a high-potential driving voltage (Vdd), a first/second initialization voltage (Vini1, Vini2), and a low-potential power supply voltage (Vss) from a power supply unit (16), and may be equipped with a driving transistor, an OLED, and an internal compensation circuit. The internal compensation circuit may be composed of a plurality of switching transistors and one or more capacitors, as illustrated in FIG. 2 described below.

The timing controller (11) supplies image data (RGB) transmitted from an external host system (not shown) to the data driving circuit (12). The timing controller (11) receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a dot clock (DCLK) from the host system and generates control signals for controlling the operation timing of the data driving circuit (12) and the gate driving circuit (13). The control signals include a gate timing control signal (GCS) for controlling the operation timing of the gate driving circuit (13) and a data timing control signal (DCS) for controlling the operation timing of the data driving circuit (12).

The data driving circuit (12) samples and latches image data (RGB) (digital video data) input from the timing controller (11) based on a data control signal (DCS), changes it into parallel data, converts it into an analog data voltage according to a gamma reference voltage through channels, and supplies the data voltage to pixels (PXL) through output channels and data lines (14). The data voltage may be a value corresponding to a gradation to be expressed by the pixel. The data driving circuit (12) may be composed of a plurality of driver ICs.

The data driving circuit (12) may include a shift register, a latch, a level shifter, a DAC, and a buffer. The shift register shifts a clock input from a timing controller (11) and sequentially outputs a clock for sampling, the latch samples digital video data or pixel data at the sampling clock timing sequentially input from the shift register and latches and simultaneously outputs the sampled pixel data, the level shifter shifts the voltage of pixel data input from the latch within the input voltage range of the DAC, the DAC converts pixel data from the level shifter into a data voltage based on a gamma compensation voltage and outputs the converted data voltage, and the data voltage output from the DAC is supplied to a data line (14) through a buffer.

The data driving circuit (12) can sense the threshold voltage of the switching transistor constituting the pixel and transmit the sensing data (Sensing Data, SD) to the timing controller. The timing controller (11) can compensate the image data (RGB) based on the sensing data (SD) to compensate the threshold voltage of the switching transistor included in the pixel and supply the compensated image data (RGB') to the data driving circuit (12).

The gate driving circuit (13) generates a scan signal and a light emitting signal based on a gate control signal (GCS), and generates the scan signal and the light emitting signal in a row-sequential manner during an active period and sequentially provides them to the gate line (15) connected to each pixel line. The scan signal and the light emitting signal of the gate line (15) are synchronized with the supply of the data voltage of the data line (14). The scan signal and the light emitting signal swing between a gate-on voltage (VGL) and a gate-off voltage (VGH). The gate-on voltage for turning on the switching transistor can be changed when the scan signal senses a threshold voltage of the switching transistor.

The gate driving circuit (13) may be composed of a plurality of gate drive integrated circuits, each of which includes a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving the TFT of the pixel, and an output buffer. Alternatively, the gate driving circuit (13) may be formed directly on the lower substrate of the display panel (10) in a GIP (Gate Drive IC in Panel) manner. In the case of the GIP method, the level shifter may be mounted on a PCB (Printed Circuit Board), and the shift register may be formed on the lower substrate of the display panel (10).

The power supply unit (16) adjusts the DC input voltage provided from the host using a DC-DC converter to generate two or more gate-on voltages, gate-off voltages, etc. (VGH, VGH1, VGH2, VGL) required for the operation of the data driving circuit (12) and the gate driving circuit (13), and also generates a high-potential driving voltage (Vdd), an initialization voltage (Vini), and a low-potential driving voltage (Vss) required for driving the pixel array.

The host system can be an AP (Application Processor) in a mobile device, a wearable device, a virtual/augmented reality device, etc. Or, the host system can be a main board of a television system, a set-top box, a navigation system, a personal computer, a home theater system, etc., but is not limited thereto.

Figure 2 illustrates a pixel circuit using an oxide semiconductor for a switching transistor. The pixel circuit is composed of six transistors and two capacitors, and compensates for the threshold voltage of the driving transistor with an internal compensation circuit.

The pixel circuit can be configured to include a driving transistor (DT), a light-emitting element (OLED), and an internal compensation circuit. The internal compensation circuit is configured with five switching transistors and two capacitors, and all or part of the switching transistors can be configured with oxide transistors.

The driving transistor (DT) is configured to generate a current to cause the OLED to emit light in response to the data voltage (Vdata), and has a first electrode connected to a third node (N3), a second electrode connected to the anode electrode of the OLED, and a gate electrode connected to a first node (n1).

The second switching transistor (T2) is for storing the threshold voltage of the driving transistor (DT) in the second node (n2). One of the first electrode and the second electrode is connected to the second node (n2) and the other is connected to the third node (n3), and the gate electrode is supplied with the first scan signal (Scan_N(n-2)).

The third switching transistor (T3) is for supplying the data voltage (Vdata) of the data line (13) to the second node (n2). One of the first electrode and the second electrode is connected to the data line (13) and the other is connected to the second node (n2), and the gate electrode is supplied with the second scan signal (Scan_N(n)).

The fourth switching transistor (T4) is for supplying the first initialization voltage (Vini1) to the gate electrode of the driving transistor (DT), i.e., the first node (n1). One of the first electrode and the second electrode is supplied with the first initialization voltage (Vini1) and the other is connected to the first node (n2), and the gate electrode is supplied with the first scan signal (Scan_N(n-2)).

The fifth switching transistor (T5) is used to control the emission of the OLED. One of the first electrode and the second electrode is supplied with a high-potential power supply voltage (Vdd), the other is connected to the third node (n3), and the gate electrode is supplied with an emission signal (EM).

The sixth switching transistor (T6) is for supplying a second initialization voltage (Vini2) to the anode electrode of the OLED. One of the first electrode and the second electrode is connected to the anode electrode of the OLED, the other is supplied with the second initialization voltage (Vini2), and the gate electrode is supplied with the third scan signal (Scan_P(n-2)).

A first storage capacitor (Cst1) is connected between the first node (n1) and the second node (n2) and stores the threshold voltage of the driving transistor (DT).

The second storage capacitor (Cst2) has one of the first electrode and the second electrode connected to the second node (n2) and the other electrode supplied with the high-potential power supply voltage (Vdd), and maintains the voltage of the second node (n2) with respect to the high-potential power supply voltage (Vdd). The second storage capacitor (Cst2) may be omitted.

The second to fourth switching transistors (T2, T3, T4) are N-channel transistors that use oxide semiconductors, and the fifth and sixth switching transistors (T5, T6) and the driving transistor (DT) are P-channel transistors that can use amorphous silicon.

In a P-channel transistor, the gate-on voltage that turns the transistor on is the gate low voltage (VGL) and the gate-off voltage that turns the transistor off is the gate high voltage (VGH). In an N-channel transistor, the gate-on voltage that turns the transistor on is the gate high voltage (VGH) and the gate-off voltage that turns the transistor off is the gate low voltage (VGL).

FIGS. 3 to 6 illustrate each step of driving the pixel circuit of FIG. 2 while compensating for the threshold voltage of the driving transistor. FIG. 3 is a non-emission period in which emission is stopped, FIG. 4 is an initialization and sensing period, FIG. 5 is a data recording period, and FIG. 6 is a emission period.

The second scan signal (Scan_N(n)) is a control signal for supplying a data voltage to pixels of the current pixel line (the nth horizontal line), and the first scan signal (Scan_N(n-2)) is a control signal for supplying a data voltage to pixels of the pixel line two pixel lines preceding the current pixel line, i.e., the (n-2)th horizontal line. Therefore, the second scan signal (Scan_N(n)) is two horizontal periods (H) behind the first scan signal (Scan_N(n-2)).

The third scan signal (Scan_P(n-2)) is a control signal for initializing the anode electrode of the OLED prior to applying the data voltage to the current pixel line, and is supplied with the opposite phase at the same timing as the first scan signal (Scan_N(n-2)).

In the first period (t1) corresponding to the non-luminous period, referring to FIG. 3, the first to third scan signals (Scan_N(n-2), Scan_N(n), Scan_P(n-2)) and the emission signal (EM) are all gate-off voltages. The second to sixth switching transistors (T2 to T6) and the driving transistors are all turned off, so that the first to third nodes (n1 to n3) maintain the voltage of the previous state or the voltage state cannot be known.

In the second period (t2) corresponding to the initialization and sensing period, referring to FIG. 4, the first and third scan signals (Scan_N(n-2), Scan_P(n-2)) are gate-on voltages, and the second scan signal (Scan_N(n)) and the emission signal (EM) are gate-off voltages. The second, fourth, and sixth switching transistors (T2, T4, T6) are turned on by the first and third scan signals (Scan_N(n-2), Scan_P(n-2)) of the gate-on voltages, so that the first initialization voltage (Vini1) is supplied to the first node (n1) through the fourth switching transistor (T4), and current flows to the second node (n2) through the second and sixth switching transistors (T2, T6).

The second initialization voltage (Vini2) is higher in potential than the first initialization voltage (Vini1), so that at the beginning of the second period (t2), the voltage of the gate electrode (or the first node (n1)) of the driving transistor (DT), which is a P-channel transistor, is lower than the anode electrode of the OLED, and thus the driving transistor (DT) is turned on. That is, a current flows from the sixth switching transistor (T6) -> driving transistor (DT) -> second switching transistor (T2) or in the opposite direction, and the potential of the second node (n2) or the third node (n3) rises (or falls) until the potential of the driving transistor (DT) becomes lower by the threshold voltage (Vth) of the driving transistor (DT) than that of the first node (n1), and the driving transistor (DT) is turned off.

Therefore, at the end of the second period (t2), the first node (n1) becomes the first initialization voltage (Vini1), and the second node (Vini2) becomes a voltage (Vini1-Vth) that is lower than the first initialization voltage (Vini1) by the threshold voltage (Vth) of the driving transistor (DT). Therefore, the threshold voltage (Vth) of the driving transistor (DT) is stored in the first storage capacitor (Cst1).

At the beginning of the second period (t2), the potential of the first node (n1) becomes the first initialization voltage (Vini1), and the potential difference between the high-potential driving voltage (Vdd) and the first initialization voltage (Vini1) of the first node (n1) is distributed by the first and second storage capacitors (Cst1, Cst2), so that the distributed potential is formed directly at the second node (n2). Thereafter, the potential of the second node (n2) becomes a voltage (Vini-Vth) reflecting the first initialization voltage (Vini1) and the threshold voltage (Vth) by the current due to the second initialization voltage (Vini2). Therefore, the settling time of the potential of the second node (n2) is not long.

After the second period (t2), in the third period (t3), the same scan signal and emission signal as in the first period (t1) are input again, the switching transistors are turned off, and the voltages of the first node (n1) and the second node (n2) are maintained by the first and second storage capacitors (Cst1, Cst2). The third period (t3) corresponds to the period in which the scan signal (Scan_N(n-2)) for applying the data voltage to the pixels arranged in the (n-1)th pixel line is supplied.

In the fourth period (t4) corresponding to the data recording period, referring to Fig. 5, the second scan signal (Scan_N(n)) is the gate-on voltage, and the remaining scan signals and the emission signal (EM) are the gate-off voltages. The third switching transistor (T3) is turned on by the second scan signal (Scan_N(n)) of the gate-on voltage, so that the data voltage (Vdata) of the data line (13) is supplied to the second node (n2).

Since the second node (n2) becomes the data voltage (Vdata) while maintaining the potential difference on both sides of the first storage capacitor (Cst1), the first node (n1) becomes the value (Vdata+Vth) that adds the threshold voltage (Vth) of the driving transistor (DT) to the data voltage (Vdata).

By storing the threshold voltage (Vth) of the driving transistor (DT) in the first storage capacitor (Cst1) in the second period (t2) prior to supplying the data voltage (Vdata), the amount of charge accumulated in the first storage capacitor (Cst1) does not change in the fourth period (t4), but only the potentials of both electrodes of the first storage capacitor (Cst1) change at the same speed. Accordingly, the time during which the potential of the first node (n1) is set to the data voltage (Vdata) (more precisely, the data voltage reflecting the threshold voltage) in the fourth period (t4) is reduced.

After the fourth period, in the fifth period (t5), the same scan signal and emission signal as in the first period (t1) or the third period (t3) are input again, so that the switching transistors are turned off, and the first node (n1) and the second node (n2) maintain their voltages by the first and second storage capacitors (Cst1, Cst2).

In the sixth period (t6) corresponding to the emission period, the first to third scan signals (Scan_N(n-2), Scan_N(n), Scan_P(n-2)) are gate-off voltages, and the emission signal (EM) is gate-on voltage. The second to sixth switching transistors (T2 to T6) are all turned off, but a high-potential power supply voltage (Vdd) is input to the third node (n3), and since the first node (n1) maintains a voltage value (Vdata+Vth) lower than the high-potential power supply voltage (Vdd), the driving transistor (DT) is turned on to flow a pixel current capable of emitting light from the OLED.

The current (I_OLED) flowing in the driving transistor (DT) is proportional to the square of the gate-source voltage (Vgs) of the driving transistor (DT) minus the threshold voltage (Vth), and can be expressed as in the following mathematical expression 1.

As shown in mathematical expression 1, the threshold voltage (Vth) component of the driving transistor (DT) is eliminated in the relationship of the driving current (I_OLED), so even if the threshold voltage of the driving transistor (DT) changes, the OLED can be made to emit light with a current corresponding to the data voltage (Vdata) input through the data line while compensating for the threshold voltage.

The third period (t3) and the fifth period (t5) are periods in which the voltage of each node is maintained the same as the previous period by turning off all the switching transistors, and can be called a maintenance period or hold period. The third period (t3) is fixed to one horizontal period, and the fifth period (t5) is omitted and proceeds directly to the sixth period (t6) so that the pixels of the corresponding pixel line immediately emit light, or is extended until after the data voltage is applied to all pixel lines and then proceeds to the sixth period (t6) so that the pixels of all pixel lines emit light simultaneously.

FIG. 7 illustrates a sensing circuit that detects a threshold voltage of a switching transistor included in the pixel circuit of FIG. 2, and FIG. 8 illustrates the operation of a switch that connects the pixel circuit of FIG. 2 and the sensing circuit of FIG. 7.

While driving the pixel circuit of Fig. 2, a gate-off voltage (VGL) is applied to the gate terminals of the second to fourth switching transistors (T2 to T4), which are oxide TFTs, for a long time, so that the second to fourth switching transistors (T2 to T4) deteriorate and their threshold voltages change. In particular, since the third switching transistor (T3) supplies the data voltage of the data line (13) to the second node (n2), deterioration of the third switching transistor (T3) means a change in the gradation that the corresponding pixel intends to express.

Therefore, the threshold voltage of the switching transistor constituting the pixel circuit of Fig. 2 must be sensed and compensated for.

In this specification, in order to detect the threshold voltages of the third and fourth switching transistors (T3, T4) through the data line (13) in FIG. 7, the source drive IC (SD-IC) included in the data driving circuit (12) may further include a voltage source (or voltage input terminal) for supplying a predetermined voltage (V1) to the data line (13), a sample/hold unit (S/H) for detecting the voltage charged in the data line (13) and converting it into digital data, and an analog-to-digital converter (ADC).

The V1 voltage source and ADC may be included in the source driver IC (SD-IC) or configured separately from the source driver IC (SD-IC).

In the configuration of Fig. 7, the data line (13) serves as a passage for supplying the data voltage from the DAC of the source drive IC (SD-IC) to the pixel, and serves to sense the threshold voltage of the switching transistors (T2, T3) constituting the pixel circuit by charging the voltage V1 and the threshold voltage of the switching transistor and transferring the threshold voltage to the ADC of the source drive IC (SD-IC).

Accordingly, the timing controller (11) can drive the display device by dividing one frame into a display stage (Display), a sensing stage (Sensing) for sensing a threshold voltage, and a compensation stage (Compensation) for compensating a data voltage, as shown in FIG. 8. The compensation stage (Compensation) can be included in the display stage.

In addition, switches (SW1, SW2, SW3) for controlling the connection between the data line (13) and the voltage source of the voltage V1, the sample/hold section (S/H), and the DAC can be provided so that the data line (13) can perform the roles assigned to each of the display stage and the sensing stage.

That is, a first switch (SW1) is provided between a voltage source of voltage V1 and a data line (13), a second switch (SW2) is provided between a sample/hold unit (S/H) and the data line (13), and a third switch (SW3) is provided between the DAC and the data line (13).

In Fig. 7, the sample/hold section (S/H) and the ADC can be referred to as a sensing circuit that senses the threshold voltage of the switching transistor and outputs sensing data. Alternatively, the sensing circuit can further include a voltage source of voltage V1 and the first to third switches (SW1 to SW3).

FIG. 9 illustrates the operation of a display step for displaying an image on a pixel circuit in the circuit of FIG. 7, and FIG. 10 illustrates the operation of a sensing step for sensing a switching transistor included in a pixel circuit in the circuit of FIG. 7.

In the display stage (Display), as shown in Fig. 9, the first and second switches (SW1, SW2) are supplied with a control signal to be turned off, so that the data line (13) is disconnected from the voltage source of voltage V1 of the source drive IC (SD-IC) and the sample/hold section (S/H), and the third switch (SW3) is supplied with a control signal to be turned on, so that the DAC of the source drive IC (SD-IC) can supply image data (RGB) to the pixels as a data voltage (Vdata) via the data line (13).

In the sensing step (Sensing), as shown in FIG. 10, the third switch (SW3) is supplied with a turn-off control signal, so that the data line (13) is disconnected from the DAC of the source drive IC (SD-IC), and the first and second switches (SW1, SW2) are supplied with a turn-on control signal and a turn-off control signal in a predetermined order, so that the data line (13) can be charged with voltage V1 and a voltage related to the threshold voltage of the third switching transistor (T3) or the second switching transistor (T2), and the voltage related to the threshold voltage can be sensed.

That is, while the first switch (SW1) is turned on, the data line (13) is charged with voltage V1, and while the second switch (SW2) is turned on, the voltage charged in the data line (13) and related to the threshold voltage of the third switching transistor (T3) or the second switching transistor (T2) is sampled by the sample/hold section (S/H) of the source drive IC (SD-IC), and then output as sensing data (SD) by the ADC.

The timing controller (11) calculates the threshold voltage of the switching transistor based on the sensing data (SD) detected from the pixel and transmitted from the source drive IC (SD-IC) in the compensation step, and when transmitting the image data (RGB) to the source drive IC (SD-IC), compensates for the image data (RGB) by reflecting the threshold voltage calculated for the corresponding pixel and outputs it.

Figure 11 illustrates a timing chart for the control signal controlling the switching transistor in the sensing step of Figure 10 and the voltage of each node.

The sensing phase can be largely composed of a first charging period (V1) for charging the data line (13) to a voltage V1, a second charging period (VGH2-Vth3) for charging the data line (13) to a voltage related to the threshold voltage of the third switching transistor (T3), and a sampling period (Sampling) for sampling the voltage charged to the data line (13).

Figure 12 illustrates the operation of the first charging section in the timing chart of Figure 11, which charges the data line to voltage V1.

In the first charging section (V1), the first switch (SW1) is turned on and then turned off, the second switch (SW2) is maintained in the turned-off state, and the first to third scan signals (Scan_N(n-2), Scan_N(n), Scan_P(n-2)) and the emission signal (EM) are input as a gate-off voltage. The first switch (SW1) is turned on, and the data line (13) is connected to a voltage source of voltage V1 and charged to the voltage V1.

FIG. 13 illustrates the operation of the second charging section in which the data line is charged to the threshold voltage of the third switching transistor in the timing chart of FIG. 11.

In the second charging section (VGH2-Vth3), the first and second switches (SW1, SW2) are kept in a turned-off state so that the data line (13) is disconnected from the voltage source of voltage V1 and the sample/hold section (S/H), and the first to third scan signals (Scan_N(n-2), Scan_N(n), Scan_P(n-2)) and the emission signal (EM) are input in a predetermined order.

First, the first and third scan signals (Scan_N(n-2), Scan_P(n-2)) and the emission signal (EM) are changed to gate-on voltages, and the first initialization voltage (Vini1) is increased in value and input higher than the second initialization voltage (Vini2). Accordingly, the second, fourth, fifth, and sixth switching transistors (T2, T4, T5, T6) are turned on, so that the first node (n1) becomes the first initialization voltage (Vini1), the second node (n2) and the third node (n3) become a high-potential power supply voltage (Vdd), and the anode electrode of the OLED becomes the second initialization voltage (Vini2).

The first initialization voltage (Vini1), which is the voltage of the gate electrode (the first electrode (n1)) of the driving transistor (DT), becomes higher than the second initialization voltage (Vini2), which is the anode electrode of the OLED, so that the driving transistor (DT) is turned off. Since the driving transistor (DT) is turned off, the OLED does not emit light.

Thereafter, when the second scan signal (Scan_N(n)) changes to the gate-on voltage, a path is formed in which the data line (13) is connected to the first power line supplying the high-potential power voltage (Vdd) through the third switching transistor (T3), the second switching transistor (T2), and the fifth switching transistor (T5), so that the voltage of the data line (13) increases from the voltage V1 by the high-potential power voltage (Vdd).

At this time, the gate-on voltage of the first scan signal (Scan_N(n-2)) and the gate-on voltage of the second scan signal (Scan_N(n)) are set to be different from each other, and the first gate-on voltage (VGH1) of the first scan signal (Scan_N(n-2)) is set higher than the second gate-on voltage (VGH2) of the second scan signal (Scan_N(n)).

When the voltage of the data line (13) (or the voltage of the second node (n2)) rises to a level (VGH2-Vth3) that is lower than the second gate-on voltage (VGH2) supplied to the gate electrode of the third switching transistor (T3) by the threshold voltage (Vth3) of the third switching transistor (T3), the third switching transistor (T3) is turned off (On->Off), and the voltage of the data line (13) stops rising to a voltage (VGH2-Vth3) or higher that reflects the threshold voltage (Vth3) of the third switching transistor (T3).

Since the gate electrode of the second switching transistor (T2) is supplied with a first gate-on voltage (VGH1) of a higher level than the second gate-on voltage (VGH2), even if the voltage of the data line (13) or the second node (n2) becomes (VGH2-Vth3), the difference between the voltage (VGH1) of the gate electrode of the second switching transistor (T2) and the voltage (VGH2-Vth3) of the second node (n2) remains greater than the threshold voltage (Vth2) of the second switching transistor (T2), and therefore the second switching transistor (T2) is not turned off.

Figure 14 illustrates the operation of a sampling interval for sampling the threshold voltage of a third switching transistor charged to a data line.

In the sampling section (Sampling), the first switch (SW1) is maintained in a turned-off state, the second switch (SW2) is turned on and then turned off, and the first to third scan signals (Scan_N(n-2), Scan_N(n), Scan_P(n-2)) and the emission signal (EM) are input as a gate-off voltage. The second switch (SW2) is turned on, and the sample/hold unit (S/H) is connected to the data line (13) to sample and hold a voltage (VGH2-Vth3) reflecting the threshold voltage of the third switching transistor (T3) charged in the data line (13), and then the ADC converts this into sensing data (SD).

Accordingly, the threshold voltage (Vth3) of the third switching transistor (T3) can be detected through the data line (13).

Figure 15 illustrates an operation of sensing the threshold voltage of the second switching transistor.

FIG. 15 is the same as FIG. 13 except that the second gate-on voltage (VGH2) of the second scan signal (Scan_N(n)) is set higher than the first gate-on voltage (VGH1) of the first scan signal (Scan_N(n-2)).

That is, when the voltage of the data line (13) (or the voltage of the second node (n2) or the third node (n3)) rises to a level (VGH1-Vth2) that is lower than the first gate-on voltage (VGH1) supplied to the gate electrode of the second switching transistor (T2) by the threshold voltage (Vth2) of the second switching transistor (T2), the second switching transistor (T2) is turned off (On->Off), and the data line (13) stops rising to a voltage (VGH1-Vth2) or higher that reflects the threshold voltage (Vth2) of the second switching transistor (T2).

Since the second gate-on voltage (VGH2) of a higher level than the first gate-on voltage (VGH1) is supplied to the gate electrode of the third switching transistor (T3), even if the voltage of the data line (13) or the second node (n2) becomes (VGH1-Vth2), the difference between the voltage (VGH2) of the gate electrode of the third switching transistor (T3) and the voltage (VGH1-Vth2) of the second node (n2) remains greater than the threshold voltage (Vth3) of the third switching transistor (T3), and therefore the third switching transistor (T3) is not turned off.

In the sampling period, the second switch (SW2) is turned on, and the sample/hold unit (S/H) samples and holds the voltage (VGH1-Vth2) that reflects the threshold voltage (Vth2) of the second switching transistor (T2) charged to the data line (13), and then the ADC converts this into sensing data (SD) and transmits it to the timing controller (11).

Figure 16 illustrates the level of a control signal for controlling the second and third switching transistors in the display stage and the sensing stage and the configuration for generating the control signal.

In the display stage (Display), the first scan signal (Scan_N(n-2)) and the second scan signal (Scan_N(n)) are sequentially output with the gate-on voltage (VGH) with two horizontal periods (H) in between, and the periods during which the two scan signals are output with the gate-on voltage do not overlap each other.

In the sensing stage, the first scan signal (Scan_N(n-2)) is first output with the gate-on voltage, and then the second scan signal (Scan_N(n)) is output with the gate-on voltage. The periods during which the two scan signals are output with the gate-on voltage overlap, and at the same time, the two scan signals change to the gate-off voltage.

In the sensing step, in order to charge the threshold voltage (Vth3) of the third switching transistor (T3) to the data line (13), the gate-on voltage (VGH1) of the first scan signal (Scan_N(n-2)) is output higher than the gate-on voltage (VGH2) of the second scan signal (Scan_N(n)), and in order to charge the threshold voltage (Vth2) of the second switching transistor (T2) to the data line (13), the gate-on voltage (VGH1) of the first scan signal (Scan_N(n-2)) is output lower than the gate-on voltage (VGH2) of the second scan signal (Scan_N(n)).

Meanwhile, one or both of the gate-on voltage (VGH1) of the first scan signal (Scan_N(n-2)) output in the sensing stage (Sensing) and the gate-on voltage (VGH2) of the second scan signal (Scan_N(n)) may be different from the gate-on voltages (VGH) of the first scan signal (Scan_N(n-2)) and the second scan signal (Scan_N(n)) output in the display stage (Display).

That is, when the threshold voltage (Vth3) of the third switching transistor (T3) is charged to the data line (13), the gate-on voltage (VGH2) of the second scan signal (Scan_N(n)) can be made equal to the gate-on voltage (VGH) of the second scan signal (Scan_N(n)) (or the first scan signal (Scan_N(n-2))) during the display phase (Display), and the gate-on voltage (VGH1) of the first scan signal (Scan_N(n-2)) can be output higher than the gate-on voltage (VGH) during the display phase (Display).

Alternatively, when charging the threshold voltage (Vth3) of the third switching transistor (T3) to the data line (13), the gate-on voltage (VGH1) of the first scan signal (Scan_N(n-2)) may be equal to the gate-on voltage (VGH) of the first scan signal (Scan_N(n-2)) (or the second scan signal (Scan_N(n))) during the display phase (Display), and the gate-on voltage (VGH2) of the second scan signal (Scan_N(n)) may be output lower than the gate-on voltage (VGH) during the display phase (Display).

Similarly, when charging the threshold voltage (Vth2) of the second switching transistor (T2) to the data line (13), the gate-on voltage (VGH2) of the first scan signal (Scan_N(n-2)) can be made equal to the gate-on voltage (VGH) of the first scan signal (Scan_N(n-2)) (or the second scan signal (Scan_N(n))) during the display phase (Display), and the gate-on voltage (VGH2) of the second scan signal (Scan_N(n)) can be output higher than the gate-on voltage (VGH) during the display phase (Display).

Alternatively, when charging the threshold voltage (Vth2) of the second switching transistor (T2) to the data line (13), the gate-on voltage (VGH2) of the second scan signal (Scan_N(n)) may be equal to the gate-on voltage (VGH) of the second scan signal (Scan_N(n)) (or the first scan signal (Scan_N(n-2))) during the display phase (Display), and the gate-on voltage (VGH1) of the first scan signal (Scan_N(n-2)) may be output lower than the gate-on voltage (VGH) during the display phase (Display).

In this case, only two gate-on voltages of the scan signal may be used: VGH in the display stage and VGH1 (or VGH2) in the sensing stage.

By providing two or more level shifters and shift registers in the gate driving circuit (14), clock signals (GCLK, GCLK') of different levels and scan signals of different gate-on levels (VGH, VGH1 (or VGH2)) can be generated, and scan signals of different gate-on voltage levels can be output to the display stage (Display) and the sensing stage (Sensing) by using switches, and in the sensing stage (Sensing), the first scan signal (Scan_N(n-2)) and the second scan signal (Scan_N(n)) can be output with different gate-on voltage levels (VGH and VGH1, VGH and VGH2, or VGH1 and VGH2).

In Fig. 16, the voltages input to the level shifter are illustrated as VGH, VGH1, VGH2, and VGL, but in reality, the levels of the scan signals output from the shift register are VGH, VGH1, VGH2, and VGL, and the voltages actually input to the level shifter may be voltages corresponding to VGH, VGH1, VGH2, and VGL.

Figure 17 illustrates an example of sensing the threshold voltage of a switching transistor included in a pixel connected to a data line arranged at the outermost edge.

Since the capacitance of the data line is large and it takes a long time to charge the data line to a voltage reflecting the threshold voltage, there is a limit to the number of switching transistors constituting a pixel or pixel circuit that can sense the threshold voltage through the same data line (13) in one sensing step.

Meanwhile, the deterioration of the switching transistor is affected by the scan signal supplied to the gate electrode, and pixels arranged in the same pixel line have similar degrees of deterioration because they are supplied with the same scan signal.

Therefore, rather than sensing the threshold voltage of the switching transistor for all pixels, it is possible to sense the threshold voltage of the switching transistor included in the pixel circuit only for one pixel arranged at the outermost side of the display panel (10) among the pixels arranged in each pixel line.

To this end, as shown in Fig. 17, the sensing circuit of Fig. 7 may be connected only to the first data line (DL#1) (or the last data line) that supplies data voltage to pixels arranged at the outermost side of the display panel (10), and the sensing circuit may not be provided for the remaining data lines. In Fig. 17, the first to third switches (SW1 to SW3) of Fig. 7 are expressed as a multiplexer (MUX).

Figures 18a and 18b illustrate examples of sensing the threshold voltage of a switching transistor included in a pixel circuit while displaying part of the screen in a constant display mode.

Mobile devices such as smartphones have adopted an Always On Display (AOD) function that always displays user-specified information, such as a clock and calendar, on the screen. In the AOD mode, user-specified information is continuously displayed in a part of the display panel (10) (the first area), but the panel can be driven at 30 Hz or 10 Hz, which is slower than 60 Hz, and the remaining area (the second area) does not turn on the OLED and only displays a black image, thereby reducing power consumption. The threshold voltage of the switching transistor constituting the pixel circuit can be sensed for the area that displays a black image in the AOD mode.

In the display step (Display) that displays information in the first area, the first initialization voltage (Vini1) must be supplied at a low voltage so as to turn on the driving transistor (DT) as shown in Fig. 4, but in the sensing step (Sensing), the first initialization voltage (Vini1) must be supplied at an increased level. In addition, different first initialization voltages (Vini1) cannot be supplied simultaneously to different areas of the display panel (10). Therefore, it is impossible to display information in the first area and sense the threshold voltage of the switching transistor in the second area at the same time.

Depending on the AOD mode, when only one of the two frames is driven for display, information such as a clock can be displayed in the first area, and a black image can be continuously displayed in the second area without driving the display. As shown in FIG. 18b, information such as a clock can be displayed by driving the first area at the beginning of the first frame (Frame1), and the threshold voltage of the switching transistor can be sensed in the second area from the latter half of the first frame until the end of the second frame (Fraem2).

In this way, in AOD mode, the sensing period can be extended so that the threshold voltage of the switching transistor can be sensed in more pixels.

Accordingly, the threshold voltage of the switching transistor constituting the pixel circuit can be accurately detected, thereby reducing distortion of the data voltage supplied to the driving transistor due to deterioration of the switching transistor and improving display quality.

The display devices described in the specification can be described as follows.

A display device according to one embodiment comprises: a display panel having a plurality of pixels, the display panel including a driving transistor for generating a current corresponding to a data voltage, a light-emitting element that emits light by the current, and a switching transistor for supplying the data voltage to the driving transistor, and a compensation circuit including a capacitor for compensating a first threshold voltage of the driving transistor; a data driving circuit for converting image data into data voltages and supplying the data voltages to the plurality of pixels through a plurality of data lines and generating sensing data according to electric signals transmitted from the pixels through the data lines; a gate driving circuit for supplying scan signals to the plurality of gate lines; and a timing controller for generating a control signal for controlling operations of the data driving circuit and the gate driving circuit so as to drive a data frame by dividing it into a display step for supplying the data voltages to the plurality of pixels and a sensing step for generating electric signals, wherein the gate driving circuit is characterized in that a second gate-on voltage of a first scan signal supplied to a gate electrode of the switching transistor during the sensing step is adjusted differently from a first gate-on voltage of a first scan signal during the display step so that the electric signal reflects a second threshold voltage of the switching transistor.

In one embodiment, the electrical signal can be a voltage that is a second gate-on voltage minus a second threshold voltage.

In one embodiment, the data driving circuit can be configured to include a first voltage input terminal for charging a data line with a first voltage in a sensing stage, a sensing circuit for sampling an electrical signal and converting it into sensing data, a digital-to-analog converter (DAC) for converting image data into a data voltage, and first to third switches for respectively connecting the first voltage input terminal, the sensing circuit, and the DAC to the data line.

In one embodiment, the timing controller can control the gate drive circuit to form a first path from a first power input terminal that supplies a high-potential power voltage to the driving transistor through the switching transistor to the data line during the sensing phase.

In one embodiment, the timing controller can control the gate drive circuit to form a second path connected to the data line through the driving transistor and the switching transistor, wherein the first or second electrode is connected to the anode electrode from the sixth switching transistor for initializing the anode electrode of the driving element during the sensing phase. A voltage higher than an initialization voltage input to the input electrode of the sixth switching transistor for initializing the anode electrode during the display phase can be input to the input electrode of the sixth switching transistor during the sensing phase.

In one embodiment, the timing controller can control the data driving circuit to, in the sensing step, turn on the first switch to connect the first voltage input terminal to the data line to charge the data line with the first voltage, then turn off the first switch to form the first path or the second path to charge the data line with the second voltage obtained by subtracting the second threshold voltage from the second gate-on voltage, and then turn on the second switch to cause the sensing circuit to convert the second voltage of the data line into sensing data.

In one embodiment, the timing controller can control the data drive circuit to turn off the first and second switches and turn on the third switch, in the display phase, to connect the DAC to the data line, and for the DAC to convert image data into a data voltage and supply it to the pixel via the data line.

In one embodiment, the compensation circuit may be configured to include a second switching transistor for storing a first threshold voltage of the driving transistor in the second node; a third switching transistor for supplying a data voltage of the data line to the second node; a fourth switching transistor for supplying a first initialization voltage to a gate electrode of the driving transistor; a fifth switching transistor for controlling connection of the driving transistor and a first power input terminal supplying a high-potential power voltage; a sixth switching transistor for supplying a second initialization voltage to an anode electrode of the driving element; and a storage capacitor connected between the gate electrode of the driving transistor and the second node for storing the first threshold voltage of the driving transistor.

In one embodiment, in the display stage, the second, fourth and sixth switching transistors are turned on during the initialization and sensing periods so that the first threshold voltage of the driving transistor is stored in the storage capacitor, the third switching transistor is turned on during the data recording period so that a voltage that adds the first threshold voltage to the data voltage is stored in the gate electrode of the driving transistor, and the fifth switching transistor and the driving transistor are turned on during the light-emitting period so that the light-emitting element can light up.

In one embodiment, when sensing a threshold voltage of a third switching transistor in a sensing step, a first path is formed that connects to a data line through a fifth switching transistor, a second switching transistor, and a third switching transistor from a first power input terminal, and a gate-on voltage of a scan signal supplied to a gate electrode of the second switching transistor can be set higher than a gate-on voltage of a scan signal supplied to a gate electrode of the third switching transistor.

In one embodiment, when sensing a threshold voltage of the second switching transistor in the sensing step, a second path is formed that connects from an input electrode of the sixth switching transistor to a data line through the sixth switching transistor, the driving transistor, the second switching transistor, and the third switching transistor, and a gate-on voltage of a scan signal supplied to a gate electrode of the third switching transistor can be set higher than a gate-on voltage of a scan signal supplied to a gate electrode of the second switching transistor.

In one embodiment, the sensing circuit further includes a current integrator for integrating a current of the electric signal, and when sensing a third threshold voltage of the fourth switching transistor in the sensing step, a third voltage is supplied to an input electrode and a gate electrode of the fourth switching transistor to turn on the fourth switching transistor, and a fourth voltage obtained by subtracting the third threshold voltage of the fourth switching transistor from the third voltage is applied to the gate electrode of the driving transistor, and a current generated by the driving transistor corresponding to the fourth voltage flows as an electric signal to the data line through the second and third switching transistors, and the sensing circuit can integrate the current of the electric signal and convert it into sensing data.

In one embodiment, the second, third and fourth switching transistors can be oxide transistors using oxide semiconductor materials.

In one embodiment, the data driving circuit may include the first voltage input terminal, the sensing circuit, and the first to third switches only on the first data line or the last data line.

Through the above explanation, those skilled in the art will be able to see that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the scope of the patent claims.

10: Display panel 11: Timing controller
12: Data driving circuit 13: Gate driving circuit
14: Data line 15: Gate line
16: Power supply

Claims (11)

A display panel having a plurality of pixels, including a driving transistor for generating a current corresponding to a data voltage, a light-emitting element that emits light by the current, and a compensation circuit including a switching transistor and a capacitor for supplying the data voltage to the driving transistor, the compensation circuit compensating for a first threshold voltage of the driving transistor;
A data driving circuit that converts image data into the data voltage and supplies it to the plurality of pixels through the plurality of data lines and generates sensing data according to an electric signal transmitted from the pixels through the data lines;
A gate driving circuit for supplying scan signals to multiple gate lines; and
It is configured to include a timing controller that generates a control signal for controlling the operation of the data driving circuit and the gate driving circuit to drive the data frame by dividing it into a display step for supplying the data voltage to the plurality of pixels and a sensing step for generating the electric signal,
A display device characterized in that the gate driving circuit adjusts the second gate-on voltage of the first scan signal supplied to the gate electrode of the switching transistor during the sensing step differently from the first gate-on voltage of the first scan signal during the display step so that the electric signal reflects the second threshold voltage of the switching transistor. In the first paragraph,
A display device, characterized in that the electric signal is a voltage obtained by subtracting the second threshold voltage from the second gate-on voltage. In the first paragraph,
A display device, characterized in that the data driving circuit comprises a first voltage input terminal for charging the data line with a first voltage in the sensing step, a sensing circuit for sampling the electric signal and converting it into the sensing data, a digital-to-analog converter (DAC) for converting the image data into the data voltage, and first to third switches for respectively connecting the first voltage input terminal, the sensing circuit, and the DAC to the data line. In the third paragraph,
A display device characterized in that the timing controller controls the gate driving circuit to form a first path connected from a first power input terminal that supplies a high-potential power voltage to the driving transistor through the switching transistor to the data line during the sensing step. In the fourth paragraph,
A display device characterized in that the timing controller controls the data driving circuit to, in the sensing step, turn on the first switch to connect the first voltage input terminal to the data line to charge the data line with the first voltage, then turn off the first switch to form the first path to charge the data line with a second voltage obtained by subtracting the second threshold voltage from the second gate-on voltage, and turn on the second switch so that the sensing circuit converts the second voltage of the data line into the sensing data. In the third paragraph,
A display device characterized in that the timing controller controls the data driving circuit to turn off the first and second switches and turn on the third switch in the display stage to connect the DAC to the data line, and to have the DAC convert the image data into the data voltage and supply it to the pixel via the data line. In the third paragraph,
The above compensation circuit,
A second switching transistor for storing the first threshold voltage of the driving transistor in the second node;
A third switching transistor for supplying the data voltage of the data line to the second node;
A fourth switching transistor for supplying a first initialization voltage to the gate electrode of the driving transistor;
A fifth switching transistor for controlling the connection of the driving transistor and the first power input terminal supplying the high-potential power voltage;
A sixth switching transistor for supplying a second initialization voltage to the anode electrode of the light emitting element; and
A display device characterized by comprising a storage capacitor connected between the gate electrode of the driving transistor and the second node to store the first threshold voltage of the driving transistor.
In Article 7,
A display device characterized in that, in the display stage, the second, fourth and sixth switching transistors are turned on during the initialization and sensing periods so that the first threshold voltage of the driving transistor is stored in the storage capacitor, the third switching transistor is turned on during the data recording period so that a voltage that adds the first threshold voltage to the data voltage is stored in the gate electrode of the driving transistor, and the fifth switching transistor and the driving transistor are turned on during the light-emitting period so that the light-emitting element lights up. In Article 7,
A display device characterized in that when sensing the threshold voltage of the third switching transistor in the sensing step, a first path is formed that connects from the first power input terminal to the data line via the fifth switching transistor, the second switching transistor, and the third switching transistor, and the gate-on voltage of the scan signal supplied to the gate electrode of the second switching transistor is set higher than the gate-on voltage of the scan signal supplied to the gate electrode of the third switching transistor. In Article 7,
A display device characterized in that the second, third and fourth switching transistors are oxide transistors using an oxide semiconductor material. In the third paragraph,
A display device, characterized in that the data driving circuit comprises the first voltage input terminal, the sensing circuit, and the first to third switches only on the first data line or the last data line.

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