CN109427308B - Display panel driving device and method for compensating pixel voltage - Google Patents
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Abstract
一种显示面板驱动装置与方法。显示面板驱动装置包括时序控制电路、存储器、补偿电路以及数据驱动电路。存储器提供在显示面板中的目前像素与至少一个邻接像素之间的至少一个耦合电容信息。通过使用所述耦合电容信息，补偿电路补偿目前像素数据而获得经补偿像素数据，以补偿目前像素因所述邻接像素的耦合电压所造成的电压偏移。数据驱动电路依据经补偿像素数据去驱动目前像素。
A display panel driving device and method. The display panel driving device includes a timing control circuit, a memory, a compensation circuit, and a data driving circuit. The memory provides at least one coupling capacitance information between a current pixel and at least one adjacent pixel in the display panel. By using the coupling capacitance information, the compensation circuit compensates the current pixel data to obtain compensated pixel data to compensate for the voltage offset of the current pixel caused by the coupling voltage of the adjacent pixel. The data driving circuit drives the current pixel according to the compensated pixel data.
Description
Technical Field
The present invention relates to a display device, and more particularly, to a display panel driving device and method for compensating pixel voltages.
Background
When liquid crystal on silicon (LCoS) is used for general display purposes, uniformity of the same gray scale is emphasized in the displayed image, and the voltage error of the pixel can be tolerated. When LCoS is used for phase modulation (phase modulation), the voltage error of the pixel is more important, because the voltage error of the pixel greatly affects the image quality. In any case, since the coupling capacitance between the adjacent pixels is necessarily present. The coupling capacitance causes voltage errors of the pixels. The coupling capacitance between adjacent pixels is larger as the distance/gap between adjacent pixels is smaller. The pixel voltage is affected by the coupling capacitance of the neighboring pixels, so that the voltage error of the pixel becomes more serious. The prior art has not provided a suitable solution to the voltage error of a pixel due to the coupling capacitance between adjacent pixels.
Disclosure of Invention
The invention provides a display panel driving device and method, which can compensate the voltage offset of the current pixel caused by the coupling voltage of the adjacent pixel.
Embodiments of the present invention provide a display panel driving apparatus. The display panel driving device comprises a time sequence control circuit, a memorizer, a compensation circuit and a data driving circuit. The timing control circuit is used for providing current pixel data of a current pixel in the display panel. The memory is used for providing at least one coupling capacitance information between a current pixel and at least one adjacent pixel in the display panel. The compensation circuit is coupled to the timing control circuit to receive the current pixel data. The compensation circuit is coupled to the memory to receive the coupling capacitance information. By using the coupling capacitance information, the compensation circuit is used for compensating the current pixel data to obtain compensated pixel data so as to compensate the voltage offset of the current pixel caused by the coupling voltage of the adjacent pixel. The data driving circuit is coupled to a current pixel of the display panel. The data driving circuit is coupled to the compensation circuit to receive the compensated pixel data. The data driving circuit is used for driving the current pixel according to the compensated pixel data.
The embodiment of the invention provides a display panel driving method. The display panel driving method includes: providing, by the timing control circuit, current pixel data of a current pixel in the display panel; providing, by a memory, at least one coupling capacitance information between a current pixel and at least one neighboring pixel in a display panel; compensating the current pixel data by a compensation circuit to obtain compensated pixel data by using the coupling capacitance information to compensate the voltage offset of the current pixel caused by the coupling voltage of the adjacent pixel; and driving the current pixel by the data driving circuit according to the compensated pixel data.
In view of the above, embodiments of the present invention provide a display panel driving apparatus and method, which can provide at least one coupling capacitance information between a current pixel and at least one neighboring pixel in a display panel by a memory. By using the coupling capacitance information, the compensation circuit may compensate the current pixel data to obtain compensated pixel data. Therefore, the display panel driving device can compensate the voltage offset of the current pixel caused by the coupling voltage of the adjacent pixels.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic block diagram of a circuit of a display panel driving apparatus according to an embodiment of the invention.
Fig. 2 is a flowchart illustrating a display panel driving method according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a portion of the pixels of the display panel shown in FIG. 1 according to an embodiment of the invention.
FIG. 4 is a schematic diagram illustrating a polarity inversion of signals of the display panel shown in FIG. 1 according to an embodiment of the invention.
FIG. 5 is a flowchart illustrating the step of obtaining the compensated pixel data shown in FIG. 2 according to one embodiment of the present invention.
Description of reference numerals:
10: display panel
100: display panel driving device
110: sequential control circuit
120: memory device
130: compensation circuit
140: data driving circuit
CP2P5、CP4P5、CP6P5、CP8P5: coupling capacitor
FN-1、FN、FN+1: frame
P1, P2, P3, P4, P5, P6, P7, P8, P9: pixel
S210 to S240, S510 to S530: step (ii) of
VCOM: common voltage
VGMA (0), VGMA (128), VGMA (255): gray scale voltage
VGR: maximum range of pixel voltage
Detailed Description
The term "coupled (or connected)" as used throughout this disclosure, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples (or connects) to a second device, it should be construed that the first device may be directly connected to the second device or the first device may be indirectly connected to the second device through some other device or some connection means. Further, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. Elements/components/steps in different embodiments using the same reference numerals or using the same terms may be referred to one another in relation to the description.
Fig. 1 is a schematic block diagram of a display panel driving apparatus 100 according to an embodiment of the invention. The display panel driving apparatus 100 may drive the display panel 10. The display panel 10 may be a conventional LCoS display panel, a liquid crystal display panel or other display panels according to design requirements. The display panel driving apparatus 100 includes a timing control circuit 110, a memory 120, a compensation circuit 130, and a data driving circuit 140.
Fig. 2 is a flowchart illustrating a display panel driving method according to an embodiment of the invention. Please refer to fig. 1 and fig. 2. In step S210, the timing control circuit 110 may provide data of a plurality of pixels of the display panel 10 to the compensation circuit 130. For example, the timing control circuit 110 may provide the current pixel data of a current pixel in the display panel 10 to the compensation circuit 130 in step S210. The timing control circuit 110 may be an existing timing controller or other pixel data processing circuits/elements according to design requirements. In step S220, the memory 120 may provide at least one coupling capacitance information between the current pixel and at least one neighboring pixel in the display panel 10 to the compensation circuit 130.
Fig. 3 is a schematic diagram of a portion of the pixels of the display panel 10 shown in fig. 1 according to an embodiment of the invention. The display panel 10 includes a plurality of pixels, such as the pixel P1, the pixel P2, the pixel P3, the pixel P4, the pixel P5, the pixel P6, the pixel P7, the pixel P8, and the pixel P9 shown in fig. 3. The distance/gap between two adjacent pixels shown in fig. 3 has been exaggerated. The distance/gap between two adjacent pixels is usually very small according to the actual design requirements. There is a coupling capacitance (parasitic capacitance) between two adjacent pixels. For example, there is a coupling capacitance C between pixel P2 and pixel P5P2P5Coupling capacitance C exists between the pixel P4 and the pixel P5P4P5Coupling capacitance C exists between the pixel P6 and the pixel P5P6P5And a coupling capacitor C exists between the pixel P8 and the pixel P5P8P5As shown in fig. 3. When the pixel P5 is the current pixel, the memory 120 can provide the coupling capacitor C in step S220P2P5、CP4P5、CP6P5And CP8P5To the compensation circuit 130.
The compensation circuit 130 is coupled to the timing control circuit 110 for receiving the current pixel data of the current pixel P5. The compensation circuit 130 is coupled to the memory 120 to receive the coupling capacitance information. By using the coupling capacitance information, the compensation circuit 130 can compensate the current pixel data of the current pixel P5 in step S230 to obtain compensated pixel data, so as to compensate the voltage offset of the current pixel P5 caused by the coupling voltages of the neighboring pixels P2, P4, P6 and P8.
The data driving circuit 140 is coupled to a plurality of pixels (e.g., the current pixel P5 and other pixels shown in fig. 3) of the display panel 10. The data driving circuit 140 is coupled to the compensation circuit 130 to receive the compensated pixel data. In step S240, the data driving circuit 140 drives the current pixel P5 of the display panel 10 according to the compensated pixel data. The data driving circuit 140 may be an existing data driver, an existing source driver, or other driving circuits/elements according to design requirements. The compensation circuit 130 may change the pixel data (e.g., the gray-scale value) of the current pixel P5 in advance by considering the voltage variation of the adjacent pixels. By means of pre-compensation, the display panel driving apparatus 100 can effectively reduce the voltage error of the pixel.
For example, in some embodiments, the compensation circuit 130 may compensate the current pixel data to obtain compensated pixel data by using the coupling capacitance information and by using a gray scale difference between the current pixel (e.g., the pixel P5 of fig. 3) and an adjacent pixel (e.g., the pixel P2, P4, P6, or P8 of fig. 3). For convenience of illustration, a Normally white (Normally white) LCoS display panel is used as an illustrative example of the display panel 10, but the embodiment of the display panel 10 is not limited thereto.
Fig. 4 is a schematic diagram illustrating a polarity inversion of signals of the display panel 10 shown in fig. 1 according to an embodiment of the invention. The horizontal axis in fig. 4 represents time, and the vertical axis represents voltage. In the embodiment shown in FIG. 4, the common voltage VCOM of the display panel 10 can be an AC voltage. For example, the common voltage VCOM is in the previous frame FN-1Medium may be a low voltage (e.g., 0V), so the previous frame FN-1Is positive in polarity. To the current frame FNIn the middle, the common voltage VCOM can be changed to a high voltage (e.g. 6V), so that the current frame FNIs negative. The remaining frames may refer to the previous frame FN-1With the current frame FNThe description is similar to that of the previous embodiment, and thus is not repeated.
In the embodiment shown in FIG. 4, the pixel data is assumed to be 8-bit data, so that the gray scale range of the pixel data is 0-255. If the gray level of the pixel data is 0, the corresponding gray level voltage is VGMA (0). If the gray level of the pixel data is 128, the corresponding gray level voltage is VGMA (128). If the gray scale of the pixel data is 255, the corresponding gray scale voltage is VGMA (255). The voltage difference between the gray scale voltage VGMA (0) and the gray scale voltage VGMA (255) (i.e., the maximum range of the pixel voltage) is VGR, as shown in fig. 4.
Please refer to fig. 3 and fig. 4. Assuming that the gray level of the current pixel P5 is M, the current pixel P5 is from frame FN-1To frame FNThe voltage variation of (A) is about VGR (M-128)/128, and from frame FNTo frame FN+1The voltage variation of (a) is about VGR (128-M)/128. Assuming that the gray level of the adjacent pixel P2 is Q, the adjacent pixel P2 is from the frame FN-1To frame FNThe voltage variation of (A) is about VGR (Q-128)/128, and from frame FNTo frame FN+1The voltage variation of (a) is about VGR (128-Q)/128. The other adjacent pixels P4, P6 and P8 can be analogized by referring to the description of the adjacent pixel P2, and thus the description thereof is omitted.
An application example for a still picture is explained here. Please refer to fig. 1, fig. 3 and fig. 4. The compensation circuit 130 may calculate the following equation 1 to obtain the compensation value ERRP5. By using the compensation value ERRP5The compensation circuit 130 can compensate the current pixel data M of the current pixel P5P5To obtain compensated pixel data COMPP5As shown in equation 2. In equation 1, PAR2Representing the coupling capacitance information, PAR, between the current pixel P5 and the first neighboring pixel P24Representing coupling capacitance information between the current pixel P5 and the second neighboring pixel P4,PAR6representing the coupling capacitance information, PAR, between the current pixel P5 and the third neighboring pixel P68Representing coupling capacitance information, Q, between the current pixel P5 and the fourth neighboring pixel P8P2Pixel data, Q, representing a first neighboring pixel P2P4A pixel data, Q, representing a second neighboring pixel P4P6Pixel data, Q, representing the third adjacent pixel P6P8Pixel data representing a fourth neighboring pixel P8, and PAR52、PAR54、PAR56、PAR58And PAR5Are real numbers. PAR52、PAR54、PAR56、PAR58And PAR5The value of (c) can be determined according to design requirements.
ERRP5＝PAR2*(MP5–QP2)+PAR52+PAR4*(MP5–QP4)+PAR54+PAR6*(MP5–QP6)+PAR56+PAR8*(MP5–QP8)+PAR58+PAR5Equation 1
COMPP5＝MP5+ERRP5Equation 2
In equation 1, coupling capacitance information PAR2、PAR4、PAR6And PAR8May be determined according to the characteristics of the display panel 10 and/or according to the maximum range VGR of the pixel voltage. For example, in some embodiments, the coupling capacitance information PAR in equation 12Is (C)P2P5*VGR*P)/(RG*CP5) Coupling capacitance information PAR4Is (C)P4P5*VGR*P)/(RG*CP5) Coupling capacitance information PAR6Is (C)P6P5*VGR*P)/(RG*CP5) Coupling capacitance information PAR8Is (C)P8P5*VGR*P)/(RG*CP5) In which C isP5Represents the storage capacitance, C, of the current pixel P5P2P5Represents the coupling capacitance, C, between the current pixel P5 and the first adjacent pixel P2P4P5Represents the coupling capacitance, C, between the current pixel P5 and the second adjacent pixel P4P6P5Represents the coupling capacitance, C, between the current pixel P5 and the third adjacent pixel P6P8P5Represents the coupling capacitance between the current pixel P5 and the fourth neighboring pixel P8, P represents the polarity transformation coefficient, and RG represents the reference gray level value. The polarity conversion coefficient P is 1 or-1. When the frame has positive polarity (frame F)N-1) Change to negative picture (frame F)N) When the polarity conversion coefficient P is 1. When drawing with negative polarity (frame F)N) Change to positive polarity picture (frame F)N+1) Then, the polarity conversion coefficient P is-1. Taking the application conditions shown in fig. 4 as an example, the reference gray-scale value RG is 128.
Suppose that the storage capacitance C of the current pixel P5P520fF, coupling capacitance CP2P5、CP4P5、CP6P5And CP8P5Are all 0.5fF, and the maximum range of pixel voltage VGR is 4V. Assume the gray level of the current pixel P5 (current pixel data M)P5) Is 128, and the gray levels of the adjacent pixels P2, P4, P6 and P8 are all 0. When the frame has positive polarity (frame F)N-1) Change to negative picture (frame F)N) Then, the voltage variation of the neighboring pixel P2 with respect to the current pixel P5 is (VGR/128) (Q-M) × P ═ (VGR/128) (0-128) × 1 ═ VGR. By analogy, the voltage variation of the other neighboring pixels (P4, P6 or P8) with respect to the current pixel P5 is also-VGR. Assume that the coupling capacitances of pixel P1, pixel P3, pixel P7, and pixel P9 with respect to pixel P5 are negligible. Calculated by the capacitance formula, CP5*ΔVP5＝CP2 P5*ΔVP2P5+CP4P5*ΔVP4P5+CP6P5*ΔVP6P5+CP8P5*ΔVP8P5Wherein Δ VP2P5Δ V which is a voltage variation amount of the pixel P2 with respect to the pixel P5P4P5Δ V which is a voltage variation amount of the pixel P4 with respect to the pixel P5P6P5Is the voltage variation of the pixel P6 relative to the pixel P5, and Δ VP8P5Is the amount of voltage fluctuation of pixel P8 with respect to pixel P5. Δ VP2P5＝ΔVP4P5＝ΔVP6P5＝ΔVP8P5(VGR/128) (Q-M) P (4/128) (0-128) 1-4. Therefore, the voltage variation Δ V of the pixel P5 due to the coupling capacitanceP5(0.5/20) × (-4) + (0.5/20) × (-4) ═ 0.4V. Unit gray scale voltageVGRAY is VGR/255-4/255-15.7 mV. Voltage Error (ERR) due to coupling effectsP5) Is DeltaVP5and/VGRAY is-0.4V/15.7 mV and is approximately equal to-25. That is, the coupling capacitance of the neighboring pixels P2, P4, P6 and P8 to the current pixel P5 will cause the current pixel P5 to have a voltage error of-25 gray scale. Thus, compensated pixel data COMPP5Is MP5The +25 is 128+25 to compensate for errors caused by coupling effects.
In another embodiment, the compensation circuit 130 can calculate the current pixel P5 in the current frame FNAnd the previous frame FN-1Current pixel change in between. The compensation circuit 130 also calculates the neighboring pixels (e.g., the pixels P2, P4, P6, and P8 shown in FIG. 3) in the current frame FNAnd the previous frame FN-1Adjacent pixels in between. By using the coupling capacitance information and by using the current pixel variation and the adjacent pixel variation, the compensation circuit 130 can compensate the current pixel data M of the current pixel P5P5To obtain compensated pixel data COMPP5。
An application example for a moving picture is explained here. Please refer to fig. 1, fig. 3 and fig. 4. The compensation circuit 130 may calculate equation 3 below to obtain the compensation value ERRP5. By using the compensation value ERRP5The compensation circuit 130 can compensate the current pixel data M of the current pixel P5P5To obtain compensated pixel data COMPP5As shown in equation 2. In equation 3, C2Representing the coupling capacitance information, C, between the current pixel P5 and the first neighboring pixel P24Represents the coupling capacitance information, C, between the current pixel P5 and the second adjacent pixel P46Represents the coupling capacitance information between the current pixel P5 and the third adjacent pixel P6, C8Represents the coupling capacitance information between the current pixel P5 and the fourth neighboring pixel P8, PV5Indicating the current pixel P5 in the current frame FNAnd the previous frame FN-1Current pixel change in between, PV2Indicating the first adjacent pixel P2 in the current frame FNAnd the previous frame FN-1Adjacent pixel variation between, PV4Indicating the second adjacent pixel P4 in the current frame FNAnd the previous frame FN-1In betweenAdjacent pixel variation, PV6Indicating the third adjacent pixel P6 in the current frame FNAnd the previous frame FN-1Adjacent pixel variation between, PV8Indicating the fourth neighboring pixel P8 in the current frame FNAnd the previous frame FN-1Adjacent pixel change therebetween, and PAR5Are real numbers. PAR5The value of (c) can be determined according to design requirements.
ERRP5＝C2*(PV2–PV5)+C4*(PV4–PV5)+C6*(PV6–PV5)+C8*(PV8–PV5)+PAR5Equation 3
In equation 3, coupling capacitance information C2、C4、C6And C8May be determined according to the characteristics of the display panel 10 and/or according to the maximum range VGR of the pixel voltage. For example, in some embodiments, the coupling capacitance information C in equation 32Is (GT/VGR) × (C)P2P5/CP5) Coupling capacitance information C4Is (GT/VGR) × (C)P4P5/CP5) Coupling capacitance information C6Is (GT/VGR) × (C)P6P5/CP5) Coupling capacitance information C8Is (GT/VGR) × (C)P8P5/CP5). Wherein GT represents the maximum gray scale range, VGR represents the maximum pixel voltage range, CP5Indicating the storage capacitance of the current pixel P5. Taking the application conditions shown in fig. 4 as an example, the maximum gray scale range GT is 256, and the maximum pixel voltage range VGR is 4V.
In a positive polarity frame (e.g., frame F shown in FIG. 4)N-1) In the current pixel P5, the voltage is VGMA (128) + (VGR/2) [ (GT/2-M)P5(N-1))/(GT/2)]P, wherein the polarity transformation coefficient P is 1. MP5(N-1)Indicating the current pixel P5 in frame FN-1The current pixel data. In a negative polarity picture (e.g., frame F shown in FIG. 4)N) In the current pixel P5, the voltage is VGMA (128) + (VGR/2) [ (GT/2-M)P5(N))/(GT/2)]P, wherein the polarity transformation coefficient P is-1. MP5(N)Indicating the current pixel P5 in frame FNThe current pixel data. Thus, of the current pixel P5Current pixel variation PV5＝{VGMA(128)+(VGR/2)*[(GT/2-MP5(N))/(GT/2)]*(-1)}–{VGMA(128)+(VGR/2)*[(GT/2-MP5(N-1))/(GT/2)]}＝(VGR/GT)*(MP5(N)+MP5(N-1))–VGR。
In a positive polarity frame (e.g., frame F shown in FIG. 4)N-1) The voltage of the first adjacent pixel P2 is VGMA (128) + (VGR/2) [ (GT/2-Q)P2(N-1))/(GT/2)]P, wherein the polarity transformation coefficient P is 1. QP2(N-1)Indicating a first adjacent pixel P2 in frame FN-1The pixel data of (1). In a negative polarity picture (e.g., frame F shown in FIG. 4)N) In the current pixel P5, the voltage is VGMA (128) + (VGR/2) [ (GT/2-Q)P2(N))/(GT/2)]P, wherein the polarity transformation coefficient P is-1. QP2(N)Indicating a first adjacent pixel P2 in frame FNThe pixel data of (1). Therefore, the adjacent pixel variation PV of the first adjacent pixel P22＝{VGMA(128)+(VGR/2)*[(GT/2-QP2(N))/(GT/2)]*(-1)}–{VGMA(128)+(VGR/2)*[(GT/2-QP2(N-1))/(GT/2)]}＝(VGR/GT)*(QP2(N)+QP2(N-1)) -VGR. The remaining adjacent pixels may be analogized. Adjacent pixel variation PV of second adjacent pixel P44Is (VGR/GT) × (Q)P4(N)+QP4(N-1)) VGR, adjacent pixel variation PV of the third adjacent pixel P66Is (VGR/GT) × (Q)P6(N)+QP6(N-1)) VGR, adjacent pixel variation PV of fourth adjacent pixel P88Is (VGR/GT) × (Q)P8(N)+QP8(N-1)) -VGR. Wherein Q isP4(N)Indicating a second adjacent pixel P4 in frame FNPixel data of, QP4(N-1)Indicating a second adjacent pixel P4 in frame FN-1Pixel data of, QP6(N)Indicating the third adjacent pixel P6 in frame FNPixel data of, QP6(N-1)Indicating the third adjacent pixel P6 in frame FN-1Pixel data of, QP8(N)Indicating the fourth neighboring pixel P8 in frame FNPixel data of, QP8(N-1)Indicating the fourth neighboring pixel P8 in frame FN-1The pixel data of (1).
Fig. 5 is a flowchart illustrating the step S230 of obtaining the compensated pixel data shown in fig. 2 according to an embodiment of the invention. In the figureIn the embodiment shown in fig. 5, step S230 includes step S510, step S520, and step S530. In step S510, the compensation circuit 130 converts the current pixel data of the current pixel P5 into corresponding gray scale voltage values. According to some design requirements, the compensation circuit 130 may use a lookup table (lookup table), a conversion method or an algorithm to convert the current pixel data into the corresponding gray scale voltage value. In step S520, the compensation circuit 130 may compensate the corresponding gray scale voltage value by using the coupling capacitance information, thereby obtaining a compensated gray scale voltage value. The compensation method performed in step S520 can be analogized by referring to the related descriptions of fig. 3, fig. 4, equation 1, equation 2, and/or equation 3, and thus will not be described again. In step S530, the compensation circuit 130 can convert the compensated gray scale voltage values into compensated pixel data COMPP5To compensate the pixel data COMPP5To the data driving circuit 140. According to some design requirements, the compensation circuit 130 may use a lookup table, a conversion method or an algorithm to convert the compensated gray scale voltage values into compensated pixel data COMPP5。
It is noted that in some embodiments, the compensation circuit 130 may be a stand-alone integrated circuit and the memory 120 may be an additional integrated circuit. In other embodiments, the memory 120 may be embedded in the compensation circuit 130. Depending on design requirements, the timing control circuit 110 and the data driving circuit 140 may be two separate integrated circuits, and the compensation circuit 130 may be embedded in the timing control circuit 110, or the compensation circuit 130 may be embedded in the data driving circuit 140. In other embodiments, the timing control circuit 110, the compensation circuit 130, and the data driving circuit 140 may be implemented as the same integrated circuit.
In different application scenarios, the related functions of the timing control circuit 110, the memory 120, the compensation circuit 130 and/or the data driving circuit 140 may be implemented as software, firmware or hardware by using a general programming language (e.g., C or C + +), a hardware description language (e.g., Verilog HDL or VHDL) or other suitable programming languages. The programming language that can perform the related functions may be arranged as any known computer-accessible media such as magnetic tapes (magnetic tapes), semiconductor memories (semiconductors), magnetic disks (magnetic disks) or optical disks (compact disks such as CD-ROM or DVD-ROM), or may be transmitted through the Internet (Internet), wired communication, wireless communication or other communication media. The programming language may be stored in a computer accessible medium for facilitating access/execution of programming codes of the software (or firmware) by a processor of the computer. For a hardware implementation, various logic regions, modules, and circuits in one or more controllers, microcontrollers, microprocessors, Application-specific integrated circuits (ASICs), Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs), and/or other processing units may be used to implement or perform the functions described in the embodiments herein. In addition, the apparatus and method of the present invention may be implemented by a combination of hardware and software.
In summary, the display panel driving apparatus 100 and the driving method according to the embodiments of the invention can provide the coupling capacitance information between the current pixel P5 and the adjacent pixel (P2, P4, P6 and/or P8) in the display panel 10 from the memory 120. By using the coupling capacitance information, the compensation circuit 130 can compensate the current pixel data of the current pixel P5 to obtain compensated pixel data of the current pixel P5. Therefore, the display panel driving apparatus 100 can compensate the voltage offset of the current pixel P5 caused by the coupling voltage of the neighboring pixels.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (16)
1. A display panel driving apparatus comprising:
a timing control circuit for providing a current pixel data of a current pixel in a display panel;
a memory for providing at least one coupling capacitance information between the current pixel and at least one neighboring pixel in the display panel;
a compensation circuit, coupled to the timing control circuit for receiving the current pixel data, coupled to the memory for receiving the coupling capacitance information, for compensating the current pixel data by using the at least one coupling capacitance information to obtain a compensated pixel data for compensating a voltage offset of the current pixel caused by the coupling voltage of the at least one neighboring pixel; and
a data driving circuit coupled to the current pixel of the display panel, coupled to the compensation circuit to receive the compensated pixel data, for driving the current pixel according to the compensated pixel data.
2. The display panel driving apparatus according to claim 1, wherein the compensation circuit obtains the compensated pixel data by compensating the current pixel data using the at least one coupling capacitance information and by using at least one gray-scale difference between the at least one neighboring pixel and the current pixel.
3. The display panel driving apparatus according to claim 1, wherein the at least one neighboring pixel comprises a first neighboring pixel, a second neighboring pixel, a third neighboring pixel and a fourth neighboring pixel, and the compensation circuit calculates the equation ERRP5＝PAR2*(MP5–QP2)+PAR52+PAR4*(MP5–QP4)+PAR54+PAR6*(MP5–QP6)+PAR56+PAR8*(MP5–QP8)+PAR58+PAR5To obtain a compensation value ERRP5And using the compensation value ERRP5To compensate the current pixel data MP5To obtain the compensatedPixel data of PAR2Representing the coupling capacitance information, PAR, between the current pixel and the first adjacent pixel4Representing the coupling capacitance information, PAR, between the current pixel and the second adjacent pixel6Representing the coupling capacitance information, PAR, between the current pixel and the third adjacent pixel8Representing the coupling capacitance information, Q, between the current pixel and the fourth neighboring pixelP2A pixel data, Q, representing the first adjacent pixelP4A pixel data, Q, representing the second adjacent pixelP6A pixel data, Q, representing the third adjacent pixelP8A pixel data representing the fourth adjacent pixel, and PAR52、PAR54、PAR56、PAR58And PAR5Are real numbers.
4. The display panel driving apparatus according to claim 3,
PAR2＝(CP2P5*VGR*P)/(RG*CP5)；
PAR4＝(CP4P5*VGR*P)/(RG*CP5)；
PAR6＝(CP6P5*VGR*P)/(RG*CP5)；
PAR8＝(CP8P5*VGR*P)/(RG*CP5)；
wherein C isP5A storage capacitance, C, representing the current pixelP2P5Representing a coupling capacitance, C, between the current pixel and the first adjacent pixelP4P5Representing a coupling capacitance, C, between the current pixel and the second adjacent pixelP6P5Representing a coupling capacitance, C, between the current pixel and the third adjacent pixelP8P5Represents a coupling capacitance between the current pixel and the fourth neighboring pixel, VGR represents a maximum range of pixel voltage, P represents a polarity transformation coefficient, and RG represents a reference gray level.
5. The display panel driving apparatus according to claim 1, wherein the compensation circuit calculates a current pixel variation of the current pixel between a current frame and a previous frame, the compensation circuit calculates at least one neighboring pixel variation of the at least one neighboring pixel between the current frame and the previous frame, and the compensation circuit obtains the compensated pixel data by compensating the current pixel data using the at least one coupling capacitance information and by using the current pixel variation and the at least one neighboring pixel variation.
6. The display panel driving apparatus according to claim 1, wherein the at least one neighboring pixel comprises a first neighboring pixel, a second neighboring pixel, a third neighboring pixel and a fourth neighboring pixel, and the compensation circuit calculates the equation ERRP5＝C2*(PV2–PV5)+C4*(PV4–PV5)+C6*(PV6–PV5)+C8*(PV8–PV5)+PAR5To obtain a compensation value ERRP5And using the compensation value ERRP5Compensating the current pixel data M of the current pixel in a current frameP5(N)To obtain the compensated pixel data, wherein C2Representing the coupling capacitance information between the current pixel and the first adjacent pixel, C4Representing the coupling capacitance information between the current pixel and the second adjacent pixel, C6Representing the coupling capacitance information between the current pixel and the third adjacent pixel, C8Represents the coupling capacitance information between the current pixel and the fourth neighboring pixel, PV5Represents a current pixel change, PV, of the current pixel between the current frame and a previous frame2Represents a change of a neighboring pixel of the first neighboring pixel between the current frame and the previous frame, PV4Represents a change of an adjacent pixel of the second adjacent pixel between the current frame and the previous frame, PV6Indicating a change in an adjacent pixel of the third adjacent pixel between the current frame and the previous frame, PV8Indicating a neighboring pixel change of the fourth neighboring pixel between the current frame and the previous frame, and PAR5Are real numbers.
7. The display panel driving apparatus according to claim 6, wherein
C2＝(GT/VGR)*(CP2P5/CP5)，C4＝(GT/VGR)*(CP4P5/CP5)；
C6＝(GT/VGR)*(CP6P5/CP5)，C8＝(GT/VGR)*(CP8P5/CP5)；
PV5＝(VGR/GT)*(MP5(N)+MP5(N-1))-VGR；
PV2＝(VGR/GT)*(QP2(N)+QP2(N-1))-VGR；
PV4＝(VGR/GT)*(QP4(N)+QP4(N-1))-VGR；
PV6＝(VGR/GT)*(QP6(N)+QP6(N-1))-VGR；
PV8＝(VGR/GT)*(QP8(N)+QP8(N-1))-VGR；
Wherein GT represents a maximum gray scale range, VGR represents a maximum pixel voltage range, CP5A storage capacitance, C, representing the current pixelP2P5Representing a coupling capacitance, C, between the current pixel and the first adjacent pixelP4P5Representing a coupling capacitance, C, between the current pixel and the second adjacent pixelP6P5Representing a coupling capacitance, C, between the current pixel and the third adjacent pixelP8P5Represents a coupling capacitance, M, between the current pixel and the fourth neighboring pixelP5(N-1)The current pixel data, Q, representing the current pixel in a previous frameP2(N)A pixel data, Q, representing the first adjacent pixel in the current frameP2(N-1)A pixel data, Q, representing the first adjacent pixel in the previous frameP4(N)A pixel data, Q, representing the second adjacent pixel in the current frameP4(N-1)A pixel data, Q, representing the second adjacent pixel in the previous frameP6(N)A pixel data, Q, representing the third adjacent pixel in the current frameP6(N-1)Indicating the third adjacent pixel in one of the previous framesPixel data, QP8(N)A pixel data, Q, representing the fourth neighboring pixel in the current frameP8(N-1)Indicating a pixel data of the fourth neighboring pixel in the previous frame.
8. The display panel driving apparatus according to claim 1, wherein the compensation circuit converts the current pixel data into a corresponding gray scale voltage value, the compensation circuit obtains a compensated gray scale voltage value by compensating the corresponding gray scale voltage value using the at least one coupling capacitance information, and the compensation circuit converts the compensated gray scale voltage value into the compensated pixel data.
9. A display panel driving method, comprising:
providing a current pixel data of a current pixel in a display panel by a time sequence control circuit;
providing, by a memory, at least one coupling capacitance information between the current pixel and at least one neighboring pixel in the display panel;
obtaining a compensated pixel data by compensating the current pixel data by a compensation circuit using the at least one coupling capacitance information to compensate a voltage offset of the current pixel due to the coupling voltage of the at least one neighboring pixel; and
a data driving circuit drives the current pixel according to the compensated pixel data.
10. The display panel driving method of claim 9, wherein the step of compensating the current pixel data comprises:
the compensated pixel data is obtained by compensating the current pixel data by the compensation circuit using the at least one coupling capacitance information and using at least one gray scale difference between the at least one neighboring pixel and the current pixel.
11. The method according to claim 9, wherein the at least one neighboring pixel comprises a first neighboring pixel, a second neighboring pixel, a third neighboring pixel and a fourth neighboring pixel, and the step of compensating the current pixel data comprises:
calculating the equation ERR from the compensation circuitP5＝PAR2*(MP5–QP2)+PAR52+PAR4*(MP5–QP4)+PAR54+PAR6*(MP5–QP6)+PAR56+PAR8*(MP5–QP8)+PAR58+PAR5To obtain a compensation value ERRP5Wherein PAR2Representing the coupling capacitance information, PAR, between the current pixel and the first adjacent pixel4Representing the coupling capacitance information, PAR, between the current pixel and the second adjacent pixel6Representing the coupling capacitance information, PAR, between the current pixel and the third adjacent pixel8Representing the coupling capacitance information between the current pixel and the fourth neighboring pixel, MP5Representing the current pixel data, QP2A pixel data, Q, representing the first adjacent pixelP4A pixel data, Q, representing the second adjacent pixelP6A pixel data, Q, representing the third adjacent pixelP8A pixel data representing the fourth adjacent pixel, and PAR52、PAR54、PAR56、PAR58And PAR5Is a real number; and
using the compensation value ERRP5To compensate the current pixel data MP5The compensated pixel data is obtained.
12. The display panel driving method according to claim 11,
PAR2＝(CP2P5*VGR*P)/(RG*CP5)，PAR4＝(CP4P5*VGR*P)/(RG*CP5)；
PAR6＝(CP6P5*VGR*P)/(RG*CP5)，PAR8＝(CP8P5*VGR*P)/(RG*CP5)；
wherein C isP5Represents the current imageA storage capacitance value of element, CP2P5Representing a coupling capacitance, C, between the current pixel and the first adjacent pixelP4P5Representing a coupling capacitance, C, between the current pixel and the second adjacent pixelP6P5Representing a coupling capacitance, C, between the current pixel and the third adjacent pixelP8P5Represents a coupling capacitance between the current pixel and the fourth neighboring pixel, VGR represents a maximum range of pixel voltage, P represents a polarity transformation coefficient, and RG represents a reference gray level.
13. The display panel driving method of claim 9, wherein the step of compensating the current pixel data comprises:
calculating a current pixel variation of the current pixel between a current frame and a previous frame by the compensation circuit;
calculating, by the compensation circuit, at least one neighboring pixel variation of the at least one neighboring pixel between the current frame and the previous frame; and
the compensated pixel data is obtained by compensating the current pixel data by the compensation circuit using the at least one coupling capacitance information and using the current pixel variation and the at least one neighboring pixel variation.
14. The method according to claim 9, wherein the at least one neighboring pixel comprises a first neighboring pixel, a second neighboring pixel, a third neighboring pixel and a fourth neighboring pixel, and the step of compensating the current pixel data comprises:
calculating the equation ERR from the compensation circuitP5＝C2*(PV2–PV5)+C4*(PV4–PV5)+C6*(PV6–PV5)+C8*(PV8–PV5)+PAR5To obtain a compensation value ERRP5In which C is2Representing the coupling capacitance information between the current pixel and the first adjacent pixel, C4Indicating the current pixel and the second adjacent pixelThe coupling capacitance information of C6Representing the coupling capacitance information between the current pixel and the third adjacent pixel, C8Represents the coupling capacitance information between the current pixel and the fourth neighboring pixel, PV5Represents a current pixel change, PV, of the current pixel between a current frame and a previous frame2Represents a change of a neighboring pixel of the first neighboring pixel between the current frame and the previous frame, PV4Represents a change of an adjacent pixel of the second adjacent pixel between the current frame and the previous frame, PV6Indicating a change in an adjacent pixel of the third adjacent pixel between the current frame and the previous frame, PV8Indicating a neighboring pixel change of the fourth neighboring pixel between the current frame and the previous frame, and PAR5Is a real number; and
using the compensation value ERR by the compensation circuitP5To compensate the current pixel data M of the current pixel in the current frameP5(N)The compensated pixel data is obtained.
15. The display panel driving method according to claim 14,
C2＝(GT/VGR)*(CP2P5/CP5)，C4＝(GT/VGR)*(CP4P5/CP5)；
C6＝(GT/VGR)*(CP6P5/CP5)，C8＝(GT/VGR)*(CP8P5/CP5)；
PV5＝(VGR/GT)*(MP5(N)+MP5(N-1))-VGR，PV2＝(VGR/GT)*(QP2(N)+QP2(N-1))-VGR，PV4＝(VGR/GT)*(QP4(N)+QP4(N-1))-VGR；
PV6＝(VGR/GT)*(QP6(N)+QP6(N-1))-VGR，PV8＝(VGR/GT)*(QP8(N)+QP8(N-1))-VGR；
wherein GT represents a maximum gray scale range, VGR represents a maximum pixel voltage range, CP5A storage capacitance, C, representing the current pixelP2P5Representing a coupling capacitance, C, between the current pixel and the first adjacent pixelP4P5Representing a coupling capacitance, C, between the current pixel and the second adjacent pixelP6P5Representing a coupling capacitance, C, between the current pixel and the third adjacent pixelP8P5Represents a coupling capacitance, M, between the current pixel and the fourth neighboring pixelP5(N-1)The current pixel data, Q, representing the current pixel in a previous frameP2(N)A pixel data, Q, representing the first adjacent pixel in the current frameP2(N-1)A pixel data, Q, representing the first adjacent pixel in the previous frameP4(N)A pixel data, Q, representing the second adjacent pixel in the current frameP4(N-1)A pixel data, Q, representing the second adjacent pixel in the previous frameP6(N)A pixel data, Q, representing the third adjacent pixel in the current frameP6(N-1)A pixel data, Q, representing the third adjacent pixel in the previous frameP8(N)A pixel data, Q, representing the fourth neighboring pixel in the current frameP8(N-1)Indicating a pixel data of the fourth neighboring pixel in the previous frame.
16. The display panel driving method of claim 9, wherein the obtaining the compensated pixel data comprises:
converting the current pixel data into a corresponding gray scale voltage value by the compensation circuit;
obtaining a compensated gray scale voltage value by the compensation circuit by compensating the corresponding gray scale voltage value using the at least one coupling capacitance information; and
the compensated gray scale voltage value is converted into the compensated pixel data by the compensation circuit.
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