CN105845548A - Silicon substrate and a manufacturing method thereof - Google Patents
Silicon substrate and a manufacturing method thereof Download PDFInfo
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- CN105845548A CN105845548A CN201510024145.XA CN201510024145A CN105845548A CN 105845548 A CN105845548 A CN 105845548A CN 201510024145 A CN201510024145 A CN 201510024145A CN 105845548 A CN105845548 A CN 105845548A
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- silicon chip
- silicon
- polysilicon layer
- silicon substrate
- manufacture method
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 159
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 154
- 239000010703 silicon Substances 0.000 title claims abstract description 154
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 title claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 52
- 230000007547 defect Effects 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims description 60
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 229910002808 Si–O–Si Inorganic materials 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000007792 gaseous phase Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 11
- 230000008859 change Effects 0.000 abstract description 10
- 239000013078 crystal Substances 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 abstract description 10
- 238000005247 gettering Methods 0.000 abstract description 10
- 230000008569 process Effects 0.000 abstract description 8
- 235000012431 wafers Nutrition 0.000 abstract 5
- 238000009776 industrial production Methods 0.000 abstract 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000001556 precipitation Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 230000009885 systemic effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The invention provides a silicon substrate and a manufacturing method thereof. The manufacturing method comprises the following steps: (1) providing a first silicon wafer and a second silicon wafer, and forming a first polycrystalline silicon layer and a second polycrystalline silicon layer on the surface of the first silicon wafer and on the surface of the second silicon wafer respectively; and (2) bonding the first polycrystalline silicon layer and the second polycrystalline silicon layer. According to the invention, the gettering action of polycrystalline silicon replaces that of BMD (Bulk-Micro Defect). A low-BMD silicon substrate can be made using the manufacturing method of the invention. The silicon substrate of the invention is of high stability, and there is neither need for BMD to change as the thermal process of the semiconductor technology changes nor need to increase the concentration of BMD deliberately in the crystal pulling process of the silicon wafers. The silicon substrate and the manufacturing method thereof have the advantage of simple steps and structure, and are suitable for industrial production.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to a kind of silicon substrate and manufacture method thereof.
Background technology
21 century will be the century of global IT application high development, and the information industry based on integrated circuit industry is in global economy
In strategic position constantly promote, surmounted iron and steel, automobile becomes the big industry of the first in the world.Integrated circuit is currently towards " more
Hurry up, more preferable, less expensive " direction develop, technical characteristic shows as " device feature live width is less, the bigger ＂ of silicon chip diameter.
" international semiconductor technical manual " prediction issued in 2005 according to " silicon TIA ", by 2015, integrated circuit
Characteristic line breadth will narrow down to 25nm, and silicon chip diameter will be increased to 450mm simultaneously.Integrated circuit is in now from deep sub-micro
Metrical scale, to the developmental stage of nanoscale transition, proposes new challenge to the silicon single crystal material as integrated circuit basis, makes
Obtain czochralski silicon monocrystal just to develop towards the direction of " high integrality, high uniformity, major diameter ".Oxygen is most important non-in progress in Czochralski silicon
The impurity deliberately mixed, it is introduced by silica crucible in crystal growing process, is often as high as 10 in silicon17～1018/cm3
The order of magnitude, is generally in hypersaturated state.Oxygen atom can assemble formation grown-in oxygen precipitates in the cooling procedure of crystal growth, and
Grow up further during the thermal process of follow-up IC manufacturing.Oxygen precipitation is most important microdefect in progress in Czochralski silicon, to list
Brilliant character and the yield rate of integrated circuit have important impact.On the one hand, the suitable oxygen precipitation of size is conducive to improving silicon chip
Mechanical performance, thus suppress silicon chip warpage in higher device temperature manufacturing process, on the other hand, oxygen precipitation in wafer bulk and
Its induced defects can effectively absorb, as gettering point, the metal contamination being incorporated into silicon chip surface in ic manufacturing process,
Here it is so-called intrinsic gettering, it it is one of the important application of Defect engineering.Ic manufacturing process controls and utilizes
Oxygen precipitation is considered as the key problem of Defect engineering.The near-surface region of silicon chip is formed miscellaneous without crystal defect and metal
The clean area of matter, and form high density bulky micro defect (bulk-micro defect, BMD) in vivo, it is beneficial to improve integrated
The yield rate of circuit.But, along with the ever-larger diameters of progress in Czochralski silicon, Oxygen in silicon content decreases, on the other hand integrated circuit system
The heat budget made significantly reduces than before, and these two aspects is all unfavorable for the generation of oxygen precipitation thus weakens the intrinsic gettering energy of silicon chip
Power, therefore tradition systemic impurity process is challenged.
Quasiconductor cutting edge technology is more and more higher to the requirement of the gettering performance of metal to silicon chip, and the gettering performance of silicon chip is primarily now
Rely on the bulky micro defect (bulk-micro defect, BMD) in wafer bulk, such as, for 28nm live width technique, silicon chip
Interior BMD concentration requirement needs more than 1E8ea/cm3。
But, the BMD in silicon chip can not infinitely increase, if BMD is too many, can draw during semiconductor fabrication process
Play the Light deformation of silicon chip, covering problem can be played when photoetching.
It addition, BMD except having with silicon chip itself outside the Pass, also and the hot processing procedure of semiconductor technology is closely bound up, current methods and
Shortcoming: the first, the BMD of silicon chip raw material during crystal pulling to be controlled own, second, the hot processing procedure of semiconductor technology to be controlled will not
Cause BMD to increase change big, and cause the Light deformation of silicon chip, the 3rd, BMD be dynamically change, by semiconductor technology heat system
The impact of journey, silicon chip body BMD to match by processing procedure hot with semiconductor technology, if silicon chip body BMD and semiconductor technology
Hot processing procedure one of both changes, and will reappraise both.
For these reasons, it is provided that a kind of silicon substrate making low BMD is necessary.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of silicon substrate and manufacture method thereof, is used for
Solve the problem that in prior art, in silicon chip, BMD content demand is higher.
For achieving the above object and other relevant purposes, the present invention provides the manufacture method of a kind of silicon substrate, described manufacture method bag
Include step:
1) the first silicon chip and the second silicon chip are provided, form more than first respectively at the surface of the surface of described first silicon chip and the second silicon chip
Crystal silicon layer and the second polysilicon layer；
2) it is bonded described first polysilicon layer and the second polysilicon layer.
As a kind of preferred version of manufacture method of the silicon substrate of the present invention, step 1) in, described first silicon chip and the second silicon
Bulky micro defect concentration in sheet is no more than 1E6ea/cm3。
As a kind of preferred version of manufacture method of the silicon substrate of the present invention, step 1) in, use chemical vapour deposition technique to divide
Do not form the first polysilicon layer and the second polysilicon layer in the surface of described first silicon chip and the surface of the second silicon chip.
Further, the predecessor that described chemical vapour deposition technique uses is SiH4, and range of reaction temperature is 500～700 DEG C, instead
Answering air pressure range is 0.5～0.2Torr.
As a kind of preferred version of manufacture method of the silicon substrate of the present invention, described first polysilicon layer and the second polysilicon layer
Total thickness is respectively 700～900nm.
As a kind of preferred version of manufacture method of the silicon substrate of the present invention, step 2) including:
2-1) form the first oxide layer and the second oxide layer respectively at described first polysilicon layer and the second polysilicon layer surface；
2-2) it is bonded described first oxide layer and the second oxide layer, is formed between described first polysilicon and the second polysilicon
Si-O-Si is bonded, and the temperature range of bonding is 800～1200 DEG C.
As a kind of preferred version of manufacture method of the silicon substrate of the present invention, also include step 3), thinning described first silicon chip
And second silicon chip, thinning after the first silicon chip and the thickness range of the second silicon chip be 700～800um.
The present invention also provides for a kind of silicon substrate, the polysilicon layer including the first silicon chip, being incorporated into described first silicon chip surface and
It is incorporated into second silicon chip on described polysilicon layer surface.
As a kind of preferred version of the silicon substrate of the present invention, the bulky micro defect concentration in described first silicon chip and the second silicon chip is not
More than 1E8ea/cm3。
As a kind of preferred version of the silicon substrate of the present invention, the thickness range of described first silicon chip and the second silicon chip is
700～800um, the thickness range of described polysilicon layer is 1400～1800nm.
As it has been described above, the present invention provides a kind of silicon substrate and manufacture method thereof, described manufacture method includes step: 1) provide first
Silicon chip and the second silicon chip, form the first polysilicon layer and more than second respectively at the surface of described first silicon chip and the surface of the second silicon chip
Crystal silicon layer；2) it is bonded described first polysilicon layer and the second polysilicon layer.The present invention uses the gettering effect of polysilicon to replace BMD
Gettering effect, use the manufacture method of the present invention can produce the silicon substrate of low BMD.The silicon substrate of the present invention has relatively
High stability, BMD need not the change with the hot processing procedure of semiconductor technology and changes, it is not required that during the crystal pulling of silicon chip
By the concentration deliberately increasing BMD.Step of the present invention and simple in construction, it is adaptable to commercial production.
Accompanying drawing explanation
Fig. 1 is shown as the steps flow chart schematic diagram of the manufacture method of the silicon substrate of the present invention.
Fig. 2～Fig. 3 is shown as the manufacture method step 1 of the silicon substrate of the present invention) structural representation that presented.
Fig. 4～Fig. 6 is shown as the manufacture method step 2 of the silicon substrate of the present invention) structural representation that presented.
Fig. 7 is shown as the manufacture method step 3 of the silicon substrate of the present invention) structural representation that presented.
Fig. 8 is shown as the structural representation of the silicon substrate of the present invention.
Element numbers explanation
101 first silicon chips
201 second silicon chips
102 first polysilicon layers
202 second polysilicon layers
103 first oxide layers
203 second oxide layers
S11～S13 step 1)～step 3)
301 first silicon chips
302 polysilicon layers
303 oxide layers
304 second silicon chips
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art can be by disclosed by this specification
Content understand other advantages and effect of the present invention easily.The present invention can also be added by the most different detailed description of the invention
To implement or application, the every details in this specification can also be based on different viewpoints and application, in the essence without departing from the present invention
Various modification or change is carried out under god.
Refer to Fig. 1～Fig. 8.It should be noted that the diagram provided in the present embodiment illustrates the present invention's the most in a schematic way
Basic conception, the most graphic in component count time only display with relevant assembly in the present invention rather than is implemented according to reality, shape and
Size is drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout type
State is likely to increasingly complex.
Embodiment 1
As shown in Fig. 1～Fig. 7, the present embodiment provides the manufacture method of a kind of silicon substrate, and described manufacture method includes step:
As shown in FIG. 1 to 3, step 1 is first carried out) S11, it is provided that the first silicon chip 101 and the second silicon chip 201, respectively at institute
The surface on the surface and the second silicon chip 201 of stating the first silicon chip 101 forms the first polysilicon layer 102 and the second polysilicon layer 202.
As example, the bulky micro defect concentration in described first silicon chip 101 and the second silicon chip 201 is no more than 1E6ea/cm3.When
So, the bulky micro defect concentration in described first silicon chip 101 and the second silicon chip 201 can also be more than 1E6ea/cm3, can be according to needing
Ask and select, such as 1E7ea/cm3、1E8ea/cm3Deng, but, during selecting, the present invention can select than reality
The silicon chip that the BMD concentration of demand is lower.
As example, use chemical vapour deposition technique respectively at the surface of described first silicon chip 101 and the surface of the second silicon chip 201
Form the first polysilicon layer 102 and the second polysilicon layer 202.In the present embodiment, before described chemical vapour deposition technique uses
Driving thing is SiH4, and range of reaction temperature is 500～700 DEG C, and reaction pressure scope is 0.5～0.2Torr.Specifically, employing is anti-
Answering temperature is 620 DEG C, and the air pressure of reaction is 0.11Torr.
As example, the thickness range of described first polysilicon layer 102 and the second polysilicon layer 202 is respectively 700～900nm.
In the present embodiment, described first polysilicon layer 102 and the thickness 800nm of the second polysilicon layer 202.
As shown in Fig. 1 and Fig. 4～Fig. 6, then carry out step 2) S12, it is bonded described first polysilicon layer 102 and the second polycrystalline
Silicon layer 202.
Specifically, including step:
Carry out step 2-1 as shown in Figure 4), formed respectively at described first polysilicon layer 102 and the second polysilicon layer 202 surface
First oxide layer 103 and the second oxide layer 203, in the present embodiment, uses thermal oxidation process to form described first oxide layer 103
And second oxide layer 203, the thickness of described first oxide layer 103 and the second oxide layer 203 is 50nm.
Carry out step 2-2 as shown in figures 5 and 6), it is bonded described first oxide layer 103 and the second oxide layer 203, in described
Forming Si-O-Si bonding between one polysilicon and the second polysilicon, the temperature range of bonding is 800～1200 DEG C.At the present embodiment
In, the temperature of bonding is 1000 DEG C.
As shown in Fig. 1 and Fig. 7, finally carry out step 3) S13, thinning described first silicon chip 101 and the second silicon chip 201, subtract
The first silicon chip 101 and the thickness range of the second silicon chip 201 after thin are 700～800um.
In the present embodiment, use thinning described first silicon chip 101 and the second silicon chip 201 of Ginding process, thinning after, use machine
The surface of described first silicon chip 101 and the second silicon chip 201 is polished by tool chemical polishing CMP, it is thus achieved that silicon of good performance
Sheet surface, to complete the preparation of described silicon substrate.
Embodiment 2
As shown in Figure 8, the present embodiment provides a kind of silicon substrate, including the first silicon chip 301, is incorporated into described first silicon chip 301
The polysilicon layer 302 on surface and be incorporated into second silicon chip 304 on described polysilicon layer 302 surface.
As example, the bulky micro defect concentration in described first silicon chip 301 and the second silicon chip 304 is no more than 1E6ea/cm3.When
So, the bulky micro defect concentration in described first silicon chip 101 and the second silicon chip 201 can also be more than 1E6ea/cm3, can be according to needing
Ask and select, such as 1E7ea/cm3、1E8ea/cm3Deng, but, during selecting, the present invention can select than reality
The silicon chip that the BMD concentration of demand is lower.
As example, the thickness range of described first silicon chip 301 and the second silicon chip 304 is 700～800um, described polysilicon layer
The thickness range of 302 is 1400～1800nm.In the present embodiment, described first silicon chip 301 and the thickness of the second silicon chip 304
For 775um, the thickness of described polysilicon layer 302 is 1600nm.
As example, described polysilicon layer includes oxide layer 303, to form Si-O-Si bonding in upper and lower two-layer polysilicon
Bonding.
As it has been described above, the present invention provides a kind of silicon substrate and manufacture method thereof, described manufacture method includes step: 1) provide first
Silicon chip 101 and the second silicon chip 201, form first respectively at the surface of the surface of described first silicon chip 101 and the second silicon chip 201
Polysilicon layer 102 and the second polysilicon layer 202；2) it is bonded described first polysilicon layer 102 and the second polysilicon layer 202.This
Invention uses the gettering effect that the gettering effect of polysilicon replaces BMD, uses the manufacture method of the present invention can produce low
The silicon substrate of BMD.The silicon substrate of the present invention has higher stability, and BMD need not the change with the hot processing procedure of semiconductor technology
Change and change, it is not required that by the concentration deliberately increasing BMD during the crystal pulling of silicon chip.Step of the present invention and simple in construction,
It is applicable to commercial production.So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any it is familiar with this skill
Above-described embodiment all can be modified under the spirit and the scope of the present invention or change by the personage of art.Therefore, such as
All that in art, tool usually intellectual is completed under without departing from disclosed spirit and technological thought etc.
Effect is modified or changes, and must be contained by the claim of the present invention.
Claims (10)
1. the manufacture method of a silicon substrate, it is characterised in that described manufacture method includes step:
1) the first silicon chip and the second silicon chip are provided, form the respectively at the surface of the surface of described first silicon chip and the second silicon chip
One polysilicon layer and the second polysilicon layer；
2) it is bonded described first polysilicon layer and the second polysilicon layer.
The manufacture method of silicon substrate the most according to claim 1, it is characterised in that: step 1) in, described first silicon chip and
Bulky micro defect concentration in two silicon chips is no more than 1E6ea/cm3。
The manufacture method of silicon substrate the most according to claim 1, it is characterised in that: step 1) in, use chemical gaseous phase deposition
Method forms the first polysilicon layer and the second polysilicon layer respectively at the surface of described first silicon chip and the surface of the second silicon chip.
The manufacture method of silicon substrate the most according to claim 3, it is characterised in that: the forerunner that described chemical vapour deposition technique uses
Thing is SiH4, range of reaction temperature is 500～700 DEG C, and reaction pressure scope is 0.5～0.2Torr.
The manufacture method of silicon substrate the most according to claim 1, it is characterised in that: described first polysilicon layer and the second polysilicon
The thickness range of layer is respectively 700～900nm.
The manufacture method of silicon substrate the most according to claim 1, it is characterised in that: step 2) including:
2-1) form the first oxide layer and the second oxide layer respectively at described first polysilicon layer and the second polysilicon layer surface；
2-2) it is bonded described first oxide layer and the second oxide layer, is formed between described first polysilicon and the second polysilicon
Si-O-Si is bonded, and the temperature range of bonding is 800～1200 DEG C.
The manufacture method of silicon substrate the most according to claim 1, it is characterised in that: also include step 3), thinning described first
Silicon chip and the second silicon chip, thinning after the first silicon chip and the thickness range of the second silicon chip be 700～800um.
8. a silicon substrate, it is characterised in that: include the first silicon chip, be incorporated into the polysilicon layer of described first silicon chip surface, Yi Jijie
The second silicon chip together in described polysilicon layer surface.
Silicon substrate the most according to claim 8, it is characterised in that: the bulky micro defect concentration in described first silicon chip and the second silicon chip
For no more than 1E6ea/cm3。
Silicon substrate the most according to claim 8, it is characterised in that: the thickness range of described first silicon chip and the second silicon chip is
700～800um, the thickness range of described polysilicon layer is 1400～1800nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510024145.XA CN105845548A (en) | 2015-01-16 | 2015-01-16 | Silicon substrate and a manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510024145.XA CN105845548A (en) | 2015-01-16 | 2015-01-16 | Silicon substrate and a manufacturing method thereof |
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| CN105845548A true CN105845548A (en) | 2016-08-10 |
Family
ID=56580235
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107655467A (en) * | 2017-11-15 | 2018-02-02 | 东南大学 | A kind of overall hemispherical resonant gyro and its processing method for packing of declining |
| CN109346433A (en) * | 2018-09-26 | 2019-02-15 | 上海新傲科技股份有限公司 | Bonding method of semiconductor substrate and bonded semiconductor substrate |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5327007A (en) * | 1991-11-18 | 1994-07-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor substrate having a gettering layer |
| JPH08316443A (en) * | 1995-05-24 | 1996-11-29 | Mitsubishi Materials Corp | Soi substrate and its manufacture |
| CN102226999A (en) * | 2011-05-11 | 2011-10-26 | 迈尔森电子（天津）有限公司 | Substrate structure and fabrication method thereof |
| CN103160809A (en) * | 2011-12-16 | 2013-06-19 | 有研半导体材料股份有限公司 | Gas dispersion device used in a growth process of wafer polycrystalline silicon film and growth process |
| CN103390593A (en) * | 2013-08-05 | 2013-11-13 | 苏州远创达科技有限公司 | Semiconductor substrate and manufacturing method thereof |
| CN103413772A (en) * | 2013-06-25 | 2013-11-27 | 上海华力微电子有限公司 | Wafer thinning method |
| CN103946970A (en) * | 2011-11-30 | 2014-07-23 | Soitec公司 | Process for fabricating a heterostructure limiting the formation of defects |
-
2015
- 2015-01-16 CN CN201510024145.XA patent/CN105845548A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5327007A (en) * | 1991-11-18 | 1994-07-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor substrate having a gettering layer |
| JPH08316443A (en) * | 1995-05-24 | 1996-11-29 | Mitsubishi Materials Corp | Soi substrate and its manufacture |
| CN102226999A (en) * | 2011-05-11 | 2011-10-26 | 迈尔森电子（天津）有限公司 | Substrate structure and fabrication method thereof |
| CN103946970A (en) * | 2011-11-30 | 2014-07-23 | Soitec公司 | Process for fabricating a heterostructure limiting the formation of defects |
| CN103160809A (en) * | 2011-12-16 | 2013-06-19 | 有研半导体材料股份有限公司 | Gas dispersion device used in a growth process of wafer polycrystalline silicon film and growth process |
| CN103413772A (en) * | 2013-06-25 | 2013-11-27 | 上海华力微电子有限公司 | Wafer thinning method |
| CN103390593A (en) * | 2013-08-05 | 2013-11-13 | 苏州远创达科技有限公司 | Semiconductor substrate and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107655467A (en) * | 2017-11-15 | 2018-02-02 | 东南大学 | A kind of overall hemispherical resonant gyro and its processing method for packing of declining |
| CN109346433A (en) * | 2018-09-26 | 2019-02-15 | 上海新傲科技股份有限公司 | Bonding method of semiconductor substrate and bonded semiconductor substrate |
| US11393772B2 (en) | 2018-09-26 | 2022-07-19 | Shanghai Simgui Technology Co., Ltd. | Bonding method for semiconductor substrate, and bonded semiconductor substrate |
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Application publication date: 20160810 |