CN103413772A - Wafer thinning method - Google Patents
Wafer thinning method Download PDFInfo
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- CN103413772A CN103413772A CN201310256826XA CN201310256826A CN103413772A CN 103413772 A CN103413772 A CN 103413772A CN 201310256826X A CN201310256826X A CN 201310256826XA CN 201310256826 A CN201310256826 A CN 201310256826A CN 103413772 A CN103413772 A CN 103413772A
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000000945 filler Substances 0.000 claims abstract description 62
- 238000011946 reduction process Methods 0.000 claims description 19
- 239000013078 crystal Substances 0.000 claims description 13
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 4
- 239000000084 colloidal system Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000007711 solidification Methods 0.000 abstract description 2
- 230000008023 solidification Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 abstract 9
- 238000009966 trimming Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 229920000297 Rayon Polymers 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003319 supportive effect Effects 0.000 description 1
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Abstract
The invention discloses a wafer thinning method, which comprising the steps of: carrying out bonding process on multiple layers of wafers; adding filler in edge gaps of the boned wafers; performing solidification process on the filler; carrying out thinning process on the bonded upmost layer wafer and/or downmost layer wafer; and removing the filler. According to the method provided by the invention, the edges of the wafers cannot be fractured due to stress when thinning the wafers, thereby avoiding scratches and residuals formed on the surfaces of the wafers caused by chippings produced in fracture; and since the trimming process is not needed, the technical process is simplified, the cost is reduced, and the wafer area utilization ratio is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, be specifically related to a kind of method of wafer attenuate.
Background technology
In field of semiconductor manufacture, because the wafer of attenuate can be conducive to encapsulation, effective transmission ray etc., so the wafer reduction process becomes for example one important operation in integrated circuit fields of field of semiconductor manufacture.
Refer to Fig. 1-4, Fig. 1 is the schematic flow sheet of the method for common wafer attenuate, and Fig. 2-4 are the corresponding cross section structure schematic diagram of each preparation process of the method for common wafer attenuate, and the method for common wafer attenuate comprises:
Step S11: refer to Fig. 2, wafer 101 and 102 is carried out to bonding technology;
Step S12: refer to Fig. 3, the wafer 101 of para-linkage carries out deburring technique;
Step S13: refer to Fig. 4, the wafer 101 of para-linkage carries out reduction process.
In the method for above-mentioned wafer attenuate, wafer 101 comprises substrate 1 and multilayer film 2, the multilayer film 2 at the back side of wafer 101 is generally a lot of layers of metal or sull, such as including epitaxial loayer, gate oxide, polysilicon film etc., existence due to multilayer film 2, and the certain radian of the marginal existence of wafer 101 and 102, when bonding, as shown in Figure 2, two wafer 101 and 102 can not fit together closely, the wafer 101 of bonding and 102 marginal existence gap, if directly carry out reduction process, the edge of wafer 101 adheres to and supports owing to can not get, very easily stressed fracture, and to wafer 101 and 102 equal injuries.
Wafer fracture for fear of bonding in reduction process, industry adopts deburring technique usually, before reduction process carries out, first the crystal round fringes of bonding is ground off, namely carry out deburring technique, yet, deburring technique need to be carried out to inside wafer the cutting of large-size, can cause so the actual usable floor area of wafer to reduce, thereby reduce the utilance of wafer area, and improve process costs.
Summary of the invention
In order to overcome the problems referred to above, purpose of the present invention is intended to improve the wafer reduction process, reduces costs, and improves the wafer area utilance.
The method of a kind of wafer attenuate of the present invention comprises:
Step S01: the multilayer wafer is carried out to bonding technology;
Step S02: apply filler in the gap, edge of the wafer after described bonding;
Step S03: described filler is cured to processing;
Step S04: the superiors' wafer and/or orlop wafer to described bonding carry out reduction process;
Step S05: described filler is removed.
Preferably, the number of plies of described multilayer wafer is two-layer.
Preferably, the outer surface of described filler exceeds or flushes in the edge of the described the superiors or orlop wafer.
Preferably, the edge close contact of described filler and described wafer.
Preferably, adopt injection device to apply described filler.
Preferably, in step S03, before carrying out described curing processing, first described crystal column surface is cleaned, remove the remaining filler on its surface.
Preferably, described curing processing is that described filler is carried out to heat treated, forms the described filler with some strength.
Preferably, after described reduction process, adopt cleaning, and/or Technology for Heating Processing is removed described filler.
Preferably, described filler is for having fusible colloid.
Preferably, described filler is dissolved in particular liquid.
The method of wafer attenuate of the present invention, in gap, edge by the wafer at bonding, apply filler, utilize good fillibility, stickiness and the certain intensity after solidifying processing of filler, can play to crystal round fringes the effect of protection, support, like this, when wafer was carried out to attenuate, crystal round fringes can not produce stressed fracture, and the chip produced while having avoided fracture forms cut and residual at crystal column surface; Owing to not needing deburring technique, simplified technical process, reduced cost, improved the wafer area utilance.
The accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the method for common wafer attenuate
Fig. 2-4 are the corresponding cross section structure schematic diagram of each preparation process of the method for common wafer attenuate
Fig. 5 is the schematic flow sheet of method of the wafer attenuate of a preferred embodiment of the present invention
Fig. 6-11st, the formed cross section structure schematic diagram of each preparation process of the wafer thining method of above-mentioned preferred embodiment of the present invention
Embodiment
The embodiment that embodies feature & benefits of the present invention will describe in detail in the explanation of back segment.Be understood that the present invention can have various variations on different examples, its neither departing from the scope of the present invention, and explanation wherein and be shown in the use that ought explain in essence, but not in order to limit the present invention.
Below in conjunction with accompanying drawing 5-11, be described in further detail by the method for specific embodiment to wafer attenuate of the present invention.Wherein, Fig. 5 is the schematic flow sheet of method of the wafer attenuate of a preferred embodiment of the present invention, Fig. 6-11st, the formed cross section structure schematic diagram of each preparation process of the wafer thining method of above-mentioned preferred embodiment of the present invention.
It should be noted that, accompanying drawing all adopts form, the non-ratio accurately of use of simplifying very much, and only in order to purpose convenient, that reach lucidly the aid illustration embodiment of the present invention.
In wafer thining method of the present invention, the wafer adopted can be, but not limited to as silicon chip, the back of wafer can include multiple layer metal or the oxide-film films such as epitaxial loayer, gate oxide, polysilicon film, and the edge of wafer has certain radian, can cause like this when two wafer are carried out bonding, edge at wafer can not well fit, as previously mentioned, although adopt conventional method, can avoid the stressed fracture of crystal round fringes, but reduced the usable floor area of wafer, thereby increased cost.
Refer to Fig. 5, the method for the wafer attenuate of the present embodiment of the present invention comprises:
Step S01: the multilayer wafer is carried out to bonding technology;
Here, in the present embodiment, the multilayer wafer is two-layer, comprises wafer 201 and lower wafer 202, and upper wafer 201 comprises substrate 21 and multilayer film 22; Refer to Fig. 6, wafer 201 and 202 is carried out to bonding technology; As previously mentioned, wafer 201 and wafer 202 are carried out to bonding, wafer 201 includes wafer substrate 21 and multilayer film 22, multilayer film 22 can include multiple layer metal or the oxide-film films such as epitaxial loayer, gate oxide, polysilicon film, due in wafer 201 and wafer 202 are carried out to bonding technology, the reasons such as marginal existence certain radian of multilayer film 22, wafer 201 and 202 are contained at wafer 201 back sides, wafer 201 and wafer 202 can not well fit together, in the marginal existence gap of wafer 201 and the wafer 202 of bonding.
In another embodiment in the present invention, wafer is the multilayer wafer, and the multilayer wafer is carried out to upper and lower stacking bonding.
Step S02: apply filler in the crystal round fringes gap of bonding;
In the present embodiment, refer to Fig. 7, apply filler 203 in the wafer 201 after two bondings and 202 gap, edge;
Concrete, can adopt injection device to apply filler 203, such as, having the syringe of pipeline, filler 203 can be expelled in gap by pipeline; Selected filler 203 is for having fusible colloid, such as filler is viscose; Filler 203 can also be dissolved in particular liquid, is conducive to like this filler 203 and is full of whole gap, improves the filling capacity of filler 203; Because filler 203 has certain filling capacity and stickiness; and has certain intensity after follow-up curing processing; can play the edge of wafer 201 and wafer 202 protection and supporting role, when carrying out attenuate, the edge of wafer 201 not can due to stressed and easily the fracture.
In addition, in another embodiment in the present invention, in the wafer of multilayer bonding, all apply filler in the crystal round fringes gap of every layer of bonding.
Step S03: filler is cured to processing;
Here, in the present embodiment, before filler 203 was cured to processing, the wafer 201 of first para-linkage and wafer 202 surfaces were cleaned, and remove the remaining filler on its surface; Refer to Fig. 8, cleaning process can adopt chemical liquids to clean; Why clean, due in the process applying filler 203, unavoidably can filler be arranged the remained on surface in wafer 201 or 202, for fear of the impact on follow-up reduction process of the filler of these residual crystal column surfaces, so first the surface of wafer 201 or 202 is cleaned.
Refer to Fig. 9, the curing processing mode adopted, can adopt filler 203 is carried out to mode of heating, because the insufficient strength of the filler 203 that is in viscous state is large, can not advantageously to the edge of wafer 201 and wafer 202, play a supporting role, therefore, also need it is cured to processing, strengthen the intensity of filler; And in solidification process, filler can better carry out with the edge of wafer 201 and wafer 202 bonding, thus filling capacity, the adhesive power of raising filler 203.
In view of this, filler 203 need to have good filling capacity, adhesive power, and has certain intensity after solidifying processing.Because the purpose that applies filler 203 is that edge to wafer 201 and wafer 202 plays protection and supporting role; so; in the present embodiment; the outer surface of filler 203 exceeds or flushes in the wafer 201 of bonding and the edge of wafer 202; the edge close contact of filler 203 and wafer 201 and wafer 202; like this, can avoid greatly reducing owing to filling insufficient effect of filler 203 that makes.
In another embodiment of the present invention, cleaning is carried out in the surface of the wafer of multilayer bonding at first, and then adopt but the mode that is not limited to heat is cured processing to filler.
Step S04: the superiors' wafer and/or the orlop wafer of para-linkage carry out reduction process.
In the present embodiment, refer to Figure 10, the wafer 201 of para-linkage carries out reduction process.
After above-mentioned steps, the filler applied has played good support and adhesive effect to the edge of wafer 201 and wafer 202, when the wafer 201 of para-linkage carries out reduction process, can avoid the stressed fracture at the edge of wafer 201, reduce residual on wafer 201 and wafer 202 surfaces of fragment.
In another embodiment of the present invention, can carry out reduction process to the superiors or the orlop wafer of the wafer of multilayer bonding, such as, can be at first the superiors' wafer of the wafer of multilayer bonding be carried out to reduction process, then, the wafer of multilayer bonding is inverted, the orlop wafer of the wafer of multilayer bonding is carried out to reduction process; Also can be only the superiors' wafer or the orlop wafer of the wafer of multilayer bonding be carried out to reduction process.
Step S05: remove filler.
In the present embodiment, refer to Figure 11, after reduction process, adopt cleaning or Technology for Heating Processing or cleaning and Technology for Heating Processing to be combined together, the filler in the gap, edge of wafer 201 and 202 is removed.
To sum up, the method of wafer attenuate of the present invention, in gap, edge by the wafer at bonding, apply filler, utilize good fillibility, stickiness and the certain intensity after solidifying processing of filler, can to crystal round fringes, play the effect of protection, support, like this, when wafer is carried out to attenuate, crystal round fringes can not produce stressed fracture, and the chip produced while having avoided fracture forms cut and residual at crystal column surface; Owing to not needing deburring technique, simplified technical process, reduced cost, improved the wafer area utilance.
Above-described is only embodiments of the invention; described embodiment is not in order to limit scope of patent protection of the present invention; therefore the equivalent structure done of every utilization specification of the present invention and accompanying drawing content changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. the method for a wafer attenuate, is characterized in that, comprising:
Step S01: the multilayer wafer is carried out to bonding technology;
Step S02: apply filler in the gap, edge of the wafer after described bonding;
Step S03: described filler is cured to processing;
Step S04: the superiors' wafer and/or orlop wafer to described bonding carry out reduction process;
Step S05: described filler is removed.
2. the method for wafer attenuate according to claim 1, is characterized in that, the number of plies of described multilayer wafer is two-layer.
3. the method for wafer attenuate according to claim 1, is characterized in that, the outer surface of described filler exceeds or flushes in the edge of the described the superiors or orlop wafer.
4. the method for wafer attenuate according to claim 1, is characterized in that, the edge close contact of described filler and described wafer.
5. the method for wafer attenuate according to claim 1, is characterized in that, adopts injection device to apply described filler.
6. the method for wafer attenuate according to claim 1, is characterized in that, in step S03, before carrying out described curing processing, first described crystal column surface cleaned, and removes the remaining filler on its surface.
7. the method for wafer attenuate according to claim 1, is characterized in that, described curing processing is that described filler is carried out to heat treated, forms the described filler with some strength.
8. the method for wafer attenuate according to claim 1, is characterized in that, after described reduction process, adopt cleaning, and/or Technology for Heating Processing removed described filler.
9. the method for wafer attenuate according to claim 1, is characterized in that, described filler is for having fusible colloid.
10. the method for wafer attenuate according to claim 1, is characterized in that, described filler is dissolved in particular liquid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310256826.XA CN103413772B (en) | 2013-06-25 | 2013-06-25 | A kind of method that wafer is thinning |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310256826.XA CN103413772B (en) | 2013-06-25 | 2013-06-25 | A kind of method that wafer is thinning |
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| CN103413772A true CN103413772A (en) | 2013-11-27 |
| CN103413772B CN103413772B (en) | 2016-08-10 |
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Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104118844A (en) * | 2014-07-15 | 2014-10-29 | 电子科技大学 | Method for thinning silicon-base back surface |
| CN104409581A (en) * | 2014-11-19 | 2015-03-11 | 迪源光电股份有限公司 | Improved wafer thinning processing method |
| CN104716056A (en) * | 2013-12-17 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method |
| CN105845548A (en) * | 2015-01-16 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Silicon substrate and a manufacturing method thereof |
| CN105984837A (en) * | 2015-02-17 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Wafer of stack structure and thinning method thereof |
| CN106348245A (en) * | 2015-07-23 | 2017-01-25 | 中芯国际集成电路制造(上海)有限公司 | MEMS device as well as preparation method and electronic device thereof |
| CN106571376A (en) * | 2015-10-13 | 2017-04-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic device |
| CN108022836A (en) * | 2016-10-31 | 2018-05-11 | 中芯国际集成电路制造(上海)有限公司 | A kind of Ginding process of multiple-level stack wafer |
| CN109461647A (en) * | 2018-11-16 | 2019-03-12 | 德淮半导体有限公司 | The manufacturing method of semiconductor device |
| CN110394910A (en) * | 2019-07-23 | 2019-11-01 | 芯盟科技有限公司 | Wafer thining method |
| CN110854039A (en) * | 2019-09-30 | 2020-02-28 | 芯盟科技有限公司 | Stack bonding wafer processing apparatus |
| CN110854011A (en) * | 2019-09-30 | 2020-02-28 | 芯盟科技有限公司 | Processing method of stacked bonded wafers |
| CN111298854A (en) * | 2020-02-27 | 2020-06-19 | 西人马联合测控（泉州）科技有限公司 | Chip forming method and wafer |
| CN111430276A (en) * | 2020-04-24 | 2020-07-17 | 武汉新芯集成电路制造有限公司 | Multi-wafer stacking trimming method |
| CN112959211A (en) * | 2021-02-22 | 2021-06-15 | 长江存储科技有限责任公司 | Wafer processing apparatus and processing method |
| CN113948373A (en) * | 2021-09-07 | 2022-01-18 | 浙江同芯祺科技有限公司 | Wafer preparation method |
| CN118983275A (en) * | 2024-10-17 | 2024-11-19 | 长鑫科技集团股份有限公司 | Semiconductor structure and method for manufacturing the same |
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| CN101327572A (en) * | 2007-06-22 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Technique for thinning back side of silicon wafer |
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Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716056A (en) * | 2013-12-17 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method |
| CN104118844A (en) * | 2014-07-15 | 2014-10-29 | 电子科技大学 | Method for thinning silicon-base back surface |
| CN104409581A (en) * | 2014-11-19 | 2015-03-11 | 迪源光电股份有限公司 | Improved wafer thinning processing method |
| CN105845548A (en) * | 2015-01-16 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Silicon substrate and a manufacturing method thereof |
| CN105984837A (en) * | 2015-02-17 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Wafer of stack structure and thinning method thereof |
| CN106348245A (en) * | 2015-07-23 | 2017-01-25 | 中芯国际集成电路制造(上海)有限公司 | MEMS device as well as preparation method and electronic device thereof |
| CN106348245B (en) * | 2015-07-23 | 2018-02-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof, electronic installation |
| CN106571376A (en) * | 2015-10-13 | 2017-04-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic device |
| CN108022836B (en) * | 2016-10-31 | 2021-04-06 | 中芯国际集成电路制造(上海)有限公司 | Grinding method of multilayer stacked wafer |
| CN108022836A (en) * | 2016-10-31 | 2018-05-11 | 中芯国际集成电路制造(上海)有限公司 | A kind of Ginding process of multiple-level stack wafer |
| CN109461647A (en) * | 2018-11-16 | 2019-03-12 | 德淮半导体有限公司 | The manufacturing method of semiconductor device |
| CN110394910A (en) * | 2019-07-23 | 2019-11-01 | 芯盟科技有限公司 | Wafer thining method |
| CN110854011A (en) * | 2019-09-30 | 2020-02-28 | 芯盟科技有限公司 | Processing method of stacked bonded wafers |
| CN110854039A (en) * | 2019-09-30 | 2020-02-28 | 芯盟科技有限公司 | Stack bonding wafer processing apparatus |
| CN111298854A (en) * | 2020-02-27 | 2020-06-19 | 西人马联合测控（泉州）科技有限公司 | Chip forming method and wafer |
| CN111298854B (en) * | 2020-02-27 | 2021-08-06 | 西人马联合测控（泉州）科技有限公司 | Chip forming method and wafer |
| CN111430276A (en) * | 2020-04-24 | 2020-07-17 | 武汉新芯集成电路制造有限公司 | Multi-wafer stacking trimming method |
| CN111430276B (en) * | 2020-04-24 | 2021-04-23 | 武汉新芯集成电路制造有限公司 | Multi-wafer stacking trimming method |
| CN112959211A (en) * | 2021-02-22 | 2021-06-15 | 长江存储科技有限责任公司 | Wafer processing apparatus and processing method |
| CN112959211B (en) * | 2021-02-22 | 2021-12-31 | 长江存储科技有限责任公司 | Wafer processing apparatus and processing method |
| CN113948373A (en) * | 2021-09-07 | 2022-01-18 | 浙江同芯祺科技有限公司 | Wafer preparation method |
| CN118983275A (en) * | 2024-10-17 | 2024-11-19 | 长鑫科技集团股份有限公司 | Semiconductor structure and method for manufacturing the same |
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