CN105634461B - A kind of level shift circuit - Google Patents

Abstract

The invention provides a level shift circuit for controlling the on-off of the power tube, comprising: a narrow pulse generator, which outputs the first narrow pulse signal according to the rising edge of the low-voltage duty ratio signal, and outputs the first narrow pulse signal according to the input low-voltage duty ratio The second narrow pulse signal is output from the falling edge of the ratio signal; the level shift module reverses the first narrow pulse signal and raises the potential to the positive-ground of the floating power supply to obtain the first high-level reverse signal, and converts the second narrow pulse signal The pulse signal is reversed and the potential is raised to the positive-ground of the floating power supply to obtain the second high-level reverse signal; the signal latch outputs a high-voltage duty cycle according to the first high-level reverse signal and the second high-level reverse signal signal; the driver stage circuit controls the opening and closing of the power tube according to the high voltage duty cycle signal, the input end of the drive stage circuit is connected to the high voltage duty cycle signal, and the output end is connected to the grid of the power tube. The short pulse drive capability is large, and the level shift can be realized quickly, which shortens the level shift time and saves power consumption.

Description

A level shift circuit

technical field

The invention relates to the technical field of control of high-voltage devices, in particular to a level shift circuit suitable for floating power supply rails.

Background technique

The level shift circuit converts the low-voltage control signal into a high-voltage control signal, and realizes the control of the low-voltage logic on the high-voltage power output stage. ) and FLASH memory circuits have been widely used. In the field of control technology for high-voltage devices, the control circuit and high-voltage output drive circuit can be integrated to achieve high withstand voltage, high current, and high precision.

A conventional level shift circuit converts a low-voltage control signal into a high-voltage control signal for driving an output-stage NMOS (should be an NMOS) tube operating under high voltage. As a key circuit connecting the control circuit and the output driver stage, the level shift circuit requires fast response capability, low quiescent current, and high stability and reliability. In the prior art, a Zener tube is usually used as a clamping component in a level shift circuit. This structure has the problems of high cost and high process requirements.

Contents of the invention

Aiming at the defects in the prior art, the object of the present invention is to provide a level shift circuit.

A level shift circuit provided according to the present invention is used to control the on-off of a power tube, comprising: a narrow pulse generator, a level shift module, a signal latch, and a driver stage circuit;

The narrow pulse generator is used to output the first narrow pulse signal according to the rising edge of the low-voltage duty ratio signal, and output the second narrow pulse signal according to the falling edge of the input low-voltage duty ratio signal, and the first narrow pulse signal signal and the second narrow pulse signal are faster than the low-voltage duty ratio signal, the power supply terminal of the narrow pulse generator is connected to the low-voltage power supply, and the input terminal of the narrow pulse generator is connected to the low-voltage duty ratio signal. empty ratio signal;

The level shifting module is used to invert the first narrow pulse signal and raise the potential to the positive-ground of the floating power supply to obtain a first high level inversion signal, and invert the second narrow pulse signal and Raise the potential to obtain a second high-level reverse signal between the positive and the ground of the floating power supply, the first input terminal of the level shift module is connected to the first narrow pulse signal, and the first narrow pulse signal of the level shift module The second input terminal is connected to the second narrow pulse signal;

The signal latch is used to output a high-voltage duty ratio signal according to the first high-level inversion signal and the second high-level inversion signal, and the set input terminal of the signal latch is connected to the first high-level inversion signal. A level inversion signal, the zeroing input terminal is connected to the second high level inversion signal;

The driving stage circuit is used to control the opening and closing of the power tube according to the high voltage duty cycle signal, the input end of the driving stage circuit is connected to the high voltage duty cycle signal, and the output end is connected to the power tube grid.

As an optimization solution, the level shift module includes a first high voltage MOS field effect transistor, a second high voltage MOS field effect transistor, a first clamp MOS field effect transistor, a second clamp MOS field effect transistor, a first resistor , the second resistance;

The gate of the first high-voltage MOS field effect transistor is the first input terminal, connected to the first narrow pulse signal, the source is connected to the ground of the low-voltage power supply, and the drain is connected to the first clamping MOS source of the FET,

The gate of the first clamp MOS field effect transistor is connected to the ground of the floating power supply, the drain is connected to the positive pole of the floating power supply, the first resistor is connected between the drain and the source, and the signal latch The set input terminal of the device is connected between the drain of the first high voltage MOS field effect transistor and the source of the first clamping MOS field effect transistor;

The gate of the second high-voltage MOS field effect transistor is the second input terminal, connected to the second narrow pulse signal, the source is connected to the ground of the low-voltage power supply, and the drain is connected to the second clamping MOS source of the FET,

The gate of the second clamping MOS field effect transistor is connected to the ground of the floating power supply, the drain is connected to the positive pole of the floating power supply, the second resistor is connected between the drain and the source, and the signal latch The zero-setting input terminal of the device is connected between the drain of the second high voltage MOS field effect transistor and the source of the second clamping MOS field effect transistor.

As an optimized solution, the resistance values of the first resistor and the second resistor are both in the range of 1kΩ˜10kΩ.

As an optimization scheme, the threshold voltages of the first high voltage MOS field effect transistor and the second high voltage MOS field effect transistor are both greater than the threshold voltages of the first clamping MOS field effect transistor and the second clamping MOS field effect transistor .

As an optimization solution, the level shift module includes a first high voltage MOS field effect transistor, a second high voltage MOS field effect transistor, a first clamping transistor, a second clamping transistor, a first diode, a second two Pole tube;

The gate of the first high-voltage MOS field effect transistor is the first input terminal, connected to the first narrow pulse signal, the source is connected to the ground of the low-voltage power supply, and the drain is connected to the first clamping transistor the emitter,

The base of the first clamping transistor is connected to the ground of the floating power supply, the collector is connected to the positive pole of the floating power supply, and the set input terminal of the signal latch is connected to the first high voltage MOS field effect transistor between the drain and the emitter of the first clamping transistor,

The cathode of the first diode is connected to the collector of the first clamping transistor, and the anode is connected to the emitter of the first clamping transistor;

The gate of the second high-voltage MOS field effect transistor is the second input terminal, connected to the second narrow pulse signal, the source is connected to the ground of the low-voltage power supply, and the drain is connected to the second clamping transistor the emitter,

The base of the second clamping transistor is connected to the ground of the floating power supply, the collector is connected to the positive pole of the floating power supply, and the zero-setting input terminal of the signal latch is connected to the second high-voltage MOS field effect transistor between the drain and the emitter of the second clamping transistor,

The cathode of the second diode is connected to the collector of the second clamping transistor, and the anode is connected to the emitter of the second clamping transistor.

As an optimized solution, the resistance values of the first diode and the second diode are both in the range of 1kΩ˜10kΩ.

As an optimization solution, the threshold voltages of the first high voltage MOS field effect transistor and the second high voltage MOS field effect transistor are both greater than the threshold voltages of the first clamping transistor and the second clamping transistor.

As an optimized solution, the potential difference between the positive ground of the floating power supply is 10-20V.

As an optimized solution, noise filtering circuit is also included;

The first high-level inverted signal output by the level shift module is connected to the set input terminal of the signal latch through the noise filter circuit,

The second high-level inverted signal output by the level shift module is connected to the zero-setting input terminal of the signal latch through the noise filter circuit.

As an optimization scheme, the noise filtering circuit is composed of two sets of RC filters; one set of RC filters is used to filter the first high-level reverse signal and output it to the setting of the signal latch At the input end, another set of RC filters is used to filter the second high-level inverted signal and output it to the zero-setting input end of the signal latch.

Compared with the prior art, the present invention has the following beneficial effects:

The invention has a simple structure, and the level shifting module performs level shifting on the narrow pulse signal obtained by the narrow pulse generator. Because of the large driving capacity of this short pulse mode, the level shifting can be quickly realized, thereby increasing the working frequency. In addition, the narrow pulse mode enables the level shift circuit to work for a short time, saving power consumption. The level shift module is composed of the first diode d1, the second diode d2, the first clamping transistor Q1, and the second clamping transistor Q2, or the first clamping MOS field effect transistor NM3 and the second clamping transistor NM3 The clamping effect of the MOS field effect transistor NM4 prevents the damage of the signal latch caused by the low potential. Compared with the solutions in the prior art, the present invention reduces the requirements on the production process, reduces the manufacturing cost, improves the stability and reliability of the circuit, and is beneficial to popularization and application.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without any creative work. In the attached picture:

Fig. 1 is a structural block diagram of a level shift circuit in an optional embodiment;

Fig. 2 is a kind of level shift circuit structure in optional embodiment;

Fig. 3 is another kind of level shift circuit structure in the optional embodiment;

Figure 4 is a schematic diagram of the comparison of waveforms at various stages in the circuit.

Detailed ways

The present invention will be described in detail below in terms of specific embodiments in conjunction with the accompanying drawings. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It is to be noted that other embodiments may be utilized or structural and functional modifications may be made to the embodiments set forth herein without departing from the scope and spirit of the invention.

A level shift circuit provided in the present invention is used to control the on-off of the power tube, as shown in the structural block diagram of Figure 1, including: a narrow pulse generator, a level shift module, a signal latch, and a driver stage circuit ;

The narrow pulse generator is used to output the first narrow pulse signal according to the rising edge of the low-voltage duty ratio signal, and output the second narrow pulse signal according to the falling edge of the input low-voltage duty ratio signal, and the first narrow pulse signal signal and the second narrow pulse signal are faster than the low-voltage duty ratio signal, the power supply terminal of the narrow pulse generator is connected to the low-voltage power supply, and the input terminal of the narrow pulse generator is connected to the low-voltage duty ratio signal. empty ratio signal;

The level shifting module is used to invert the first narrow pulse signal and raise the potential to the positive-ground of the floating power supply to obtain a first high level inversion signal, and invert the second narrow pulse signal and Raise the potential to obtain a second high-level reverse signal between the positive and the ground of the floating power supply, the first input terminal of the level shift module is connected to the first narrow pulse signal, and the first narrow pulse signal of the level shift module The second input terminal is connected to the second narrow pulse signal;

The signal latch is used to output a high-voltage duty ratio signal according to the first high-level inversion signal and the second high-level inversion signal, and the set input terminal of the signal latch is connected to the first high-level inversion signal. A level inversion signal, the zeroing input terminal is connected to the second high level inversion signal;

The driving stage circuit is used to control the opening and closing of the power tube according to the high voltage duty cycle signal, the input end of the driving stage circuit is connected to the high voltage duty cycle signal, and the output end is connected to the power tube grid.

The power supply terminals of the level shifting module, the signal latch and the driving stage circuit are all connected to the floating power supply.

In the embodiment shown in FIG. 1 , the input low-voltage duty cycle signal is a PWM signal, and VDD and GND are the power and ground of the low-voltage power supply part. BST and SW are power and ground for the high voltage floating power rail section. PVIN is the supply voltage of the controlled power tube. In the low-voltage power supply part in the figure, only the narrow pulse and the circuit part before it, the level shift module and the noise filter circuit connected after it, the signal latch, and the driver stage are all part of the high-voltage floating power supply rail. The high-voltage floating power rail mentioned in this patent refers to a bootstrap circuit, also known as a boost circuit. The relative voltage difference between BST and SW remains unchanged, but the potential can be increased, such as floating from 20V-0V in SW ground state to 220V -200V. VDD-GND is a low-voltage power supply, and is a fixed ground power supply, such as 15V-0V or 20V-0V in this embodiment. The floating power supply is a common circuit in the prior art, and its structure will not be described in detail in the present invention.

In Figure 1, when the PWM signal is input, the narrow pulse generator generates a narrow pulse signal according to the rising edge and falling edge of the PWM signal, namely the first narrow pulse signal PWM_R and the second narrow pulse signal PWM_F, as shown in Figure 4.

The narrow pulse signal passes through the level shift circuit to increase the amplitude of the input signal from 20V-0V corresponding to VDD-GND to 220V-200V corresponding to BST-SW. Due to the large driving capability of this short pulse method, the level shift can be quickly realized, thereby increasing the operating frequency. In addition, the narrow pulse mode enables the level shift circuit to work for a short time, saving power consumption.

As an embodiment, the level shifting circuit further includes a noise filtering circuit;

The first high-level inverted signal output by the level shift module is connected to the set input terminal of the signal latch through the noise filter circuit,

The second high-level inverted signal output by the level shift module is connected to the zero-setting input terminal of the signal latch through the noise filter circuit.

The first high-level reverse signal and the second high-level reverse signal output from the level shift module are still narrow pulse signals, but the signal level has been converted to 220V-200V corresponding to BST-SW. In order to prevent noise interference in the circuit, a first-stage noise filter circuit is followed, which is beneficial to prevent false triggering of subsequent connected signal latches, resulting in misoperation of the power tube. The signal latch is sensitive to the pulse signal, so if there is noise interference, it will have a great impact on the subsequent output. The noise-filtered output signal is the zero input terminal R and the set input terminal S in Figure 4 . After the noise filter circuit and the R-S signal latch, the signal changes from a narrow pulse signal to a duty ratio signal (high voltage duty ratio signal), but the high voltage duty ratio signal level has been raised to the corresponding 220V- 200V, the level shift from the low-voltage duty ratio signal to the high-voltage duty ratio signal is finally realized. The high-voltage duty ratio signal is shown in the Q signal in Figure 4. The high-voltage duty ratio signal Q output by the signal latch controls the opening and closing of the power transistor PM1 after passing through the driver stage, thereby realizing the control of the high-voltage driver stage and the power transistor by the PWM low-voltage signal.

The noise filtering circuit is composed of two sets of RC filters; one set of RC filters is used to filter the first high-level reverse signal and output it to the set input terminal S of the signal latch, and the other set The set of RC filters is used to filter the second high-level inverted signal and output it to the zero-setting input terminal R of the signal latch. The RC filter is a commonly used filter circuit structure in the field. The structure of the RC filter adopted in the present invention is shown in Fig. 2 and Fig. 3: it is composed of a resistor and a capacitor, one end of the resistor is the output end of the level shift module, and the other end is connected to the input end of the signal latch; one end of the capacitor is connected to the Between the resistor and the signal latch, the other end is connected to the ground of the floating power supply (that is, the SW pole).

Figure 2 is an embodiment of the level shift module in Figure 1, the level shift module includes a first high-voltage MOS field effect transistor NM1, a second high-voltage MOS field effect transistor NM2, a first clamp MOS field Effect transistor NM3, second clamp MOS field effect transistor NM4, first resistor R1, second resistor R2;

The gate of the first high-voltage MOS field effect transistor NM1 is the first input terminal, connected to the first narrow pulse signal, the source is connected to the ground (low-voltage GND) of the low-voltage power supply, and the drain is connected to the The source of the first clamp MOS field effect transistor NM3,

The gate of the first clamp MOS field effect transistor NM3 is connected to the ground of the floating power supply, the drain is connected to the positive pole of the floating power supply, the first resistor R1 is connected between the drain and the source, and the signal The set input end of the latch is connected between the drain of the first high voltage MOS field effect transistor NM1 and the source of the first clamping MOS field effect transistor NM3;

The gate of the second high-voltage MOS field effect transistor NM2 is the second input terminal, connected to the second narrow pulse signal, the source is connected to the ground (low-voltage GND) of the low-voltage power supply, and the drain is connected to the The source of the second clamp MOS field effect transistor NM4,

The gate of the second clamp MOS field effect transistor NM4 is connected to the ground of the floating power supply, the drain is connected to the positive pole of the floating power supply, the second resistor R2 is connected between the drain and the source, and the signal The zero-setting input terminal of the latch is connected between the drain of the second high voltage MOS field effect transistor NM2 and the source of the second clamping MOS field effect transistor NM4.

The resistance values of the first resistor R1 and the second resistor R2 are both in the range of 1kΩ˜10kΩ, and the resistance values of the first resistor R1 and the second resistor R2 are the same, which may be 1kΩ, or 5kΩ, or 10kΩ.

Both the threshold voltages of the first high voltage MOS field effect transistor NM1 and the second high voltage MOS field effect transistor NM2 are greater than the threshold voltages of the first clamping MOS field effect transistor NM3 and the second clamping MOS field effect transistor NM4 . In this embodiment, the floating power supply can be boosted from 20V-0V to 220V-200V, and the first high voltage MOS field effect transistor NM1 and the second high voltage MOS field effect transistor NM2 need to be able to withstand the floating power supply boosting from 20V-0V to 220V The high voltage difference caused by -200V requires performance that can withstand high voltage. However, the first clamp MOS field effect transistor NM3 and the second clamp MOS field effect transistor NM4 only need to withstand the voltage difference between the positive electrode of the floating power supply and the floating ground, so they only need to withstand the voltage of 20V, and no high voltage requirement is required. In this embodiment, different devices are selected according to different performance requirements to achieve the best cost performance.

When PWM becomes high, the first narrow pulse signal PWM_R becomes high, the first high-voltage MOS field effect transistor NM1 is turned on, and the voltage at point n1 connected to the set input terminal S of the signal latch by the level shift module is pulled down , the current flows through the first resistor R1. When the voltage at point n1 is lower than the SW of the floating power supply, and the voltage difference is greater than the threshold voltage of the first clamp MOS field effect transistor NM3, the first clamp MOS field effect transistor NM3 is turned on, and part of the current passes through the first clamp The voltage at the bit MOS field effect transistor NM3, n1 will not decrease any more, but will be clamped by the first clamping MOS field effect transistor NM3. In this way, the voltage difference from the positive pole BST of the floating power supply to point n1 will not be too large, and the signal input to the setting input terminal S of the signal latch will not be too low to cause damage to the signal latch. After the voltage at point n1 becomes low, it passes through the RC filter and reaches the set input terminal S of the signal latch. The set input terminal S of the signal latch is active at low level, the signal latch is set, and a high-voltage duty cycle signal is output. Q is high. When the narrow pulse of the first narrow pulse signal PWM_R disappears and becomes low again, the first high voltage MOS field effect transistor NM1 is turned off. Point n1 is charged through the first resistor R1, and the final voltage is equal to the voltage of BST. The voltage output from the RC filter to the set input terminal S of the signal latch also becomes the BST voltage, but the output of the signal latch remains at a high level, as shown in signal Q in FIG. 4 .

When PWM becomes low, the second narrow pulse signal PWM_F becomes high, the second high-voltage MOS field effect transistor NM2 is turned on, and the voltage at point n2 of the level shift module connected to the zero-setting input terminal R of the signal latch is pulled down , the current flows through the second resistor R2. When the voltage at point n2 is lower than the SW of the floating power supply and the voltage difference is greater than the threshold voltage of the second clamping MOS field effect transistor NM4, the second clamping MOS field effect transistor NM4 is turned on. At this time, part of the current passes through the second clamping MOS field effect transistor NM4, and the voltage at point n2 will not decrease any more, and is clamped by the second clamping MOS field effect transistor NM4. In this way, the voltage difference from the positive pole BST of the floating power supply to point n2 will not be too large, and the signal input to the zero-setting input terminal R of the signal latch will not cause damage to the signal latch because it is too low. After the voltage at point n2 becomes low, it passes through the RC filter and reaches the zero-setting input terminal R of the signal latch. The zero-setting input terminal R of the signal latch is active at low level, the signal latch is reset, and the high-voltage duty ratio of the output Signal Q goes low, see signal Q in FIG. 4 . When the narrow pulse of the second narrow pulse signal PWM_F disappears and becomes low again, the second high-voltage MOS field effect transistor NM2 is turned off, the voltage at point n2 is charged through the resistor R2, and the final voltage is equal to the BST voltage, and the RC filter is output to the signal latch The voltage at the zero-setting input terminal R also becomes the BST voltage, but the output of the signal latch remains low.

When the BST and SW voltages of the floating power supply become low at the same time, n1 and n2 can discharge the voltage of points n1 and n2 through the parasitic diodes of the first clamping MOS field effect transistor NM3 and the second clamping MOS field effect transistor NM4, so that n1 The voltage of and n2 will not be too much higher than the positive pole BST of the floating power supply and the ground SW to destroy the subsequent stage circuit. The MOS field effect transistor produces the parasitic diode due to its manufacturing process, and no additional settings are required.

In terms of circuit realization, the above-mentioned parasitic diodes can also be replaced by non-parasitic diodes. The clamping functions of NM3 and NM4 in the figure can also be replaced by NPN transistors. Among them, the collector of the triode is connected to BST, the base is connected to SW, and the emitter is connected to n1 and n2. In addition, the functions of NM3 and NM4 can also be directly clamped by the Zener tube, the P level of the Zener tube is connected to n1 and n2, and the N level is connected to BST.

Therefore, another embodiment of the level shift module can be designed. In the embodiment shown in FIG. 3 , the level shift module includes a first high voltage MOS field effect transistor NM1, a second high voltage MOS field effect transistor NM2, The first clamping transistor Q1, the second clamping transistor Q2, the first diode d1, and the second diode d2;

The gate of the first high-voltage MOS field effect transistor NM1 is the first input terminal, connected to the first narrow pulse signal, the source is connected to the ground (low-voltage GND) of the low-voltage power supply, and the drain is connected to the The emitter of the first clamp transistor Q1,

The base of the first clamping transistor Q1 is connected to the ground of the floating power supply, the collector is connected to the positive pole of the floating power supply, and the set input terminal of the signal latch is connected to the first high-voltage MOS field effect between the drain of the transistor NM1 and the emitter of the first clamp transistor Q1,

The cathode of the first diode d1 is connected to the collector of the first clamping transistor Q1, and the anode is connected to the emitter of the first clamping transistor Q1;

The gate of the second high-voltage MOS field effect transistor NM2 is the second input terminal, connected to the second narrow pulse signal, the source is connected to the ground (low-voltage GND) of the low-voltage power supply, and the drain is connected to the The emitter of the second clamp transistor Q2,

The base of the second clamping transistor Q2 is connected to the ground of the floating power supply, the collector is connected to the positive pole of the floating power supply, and the zero-setting input terminal of the signal latch is connected to the second high-voltage MOS field effect between the drain of the transistor NM2 and the emitter of the second clamp transistor Q2,

The cathode of the second diode d2 is connected to the collector of the second clamping transistor Q2, and the anode is connected to the emitter of the second clamping transistor Q2.

As an embodiment, the resistance values of the first diode d1 and the second diode d2 are both in the range of 1kΩ～10kΩ, and the resistance values of the first diode d1 and the second diode d2 are The value is the same, it can be 1kΩ, or 5kΩ, or 10kΩ. Both the threshold voltages of the first high voltage MOS field effect transistor NM1 and the second high voltage MOS field effect transistor NM2 are greater than the threshold voltages of the first clamping transistor Q1 and the second clamping transistor Q2 . The potential difference between the positive electrode of the floating power supply and the ground is 10-20V.

In the embodiment shown in Figure 3, when PWM becomes high, the first narrow pulse signal PWM_R becomes high, the first high-voltage MOS field effect transistor NM1 is turned on, and the level shift module and the signal latch set input The voltage of point n1 connected to terminal S is pulled down, and the current flows through the first diode d1. When the voltage at point n1 is lower than the SW of the floating power supply, and the voltage difference is greater than the threshold voltage of the first clamping transistor Q1, the first clamping transistor Q1 is turned on, and at this time part of the current passes through the first clamping transistor Q1, point n1 The voltage of will not decrease any more, but will be clamped by the first clamping transistor Q1. In this way, the voltage difference from the positive pole BST of the floating power supply to point n1 will not be too large, and the signal input to the setting input terminal S of the signal latch will not be too low to cause damage to the signal latch. After the voltage at point n1 becomes low, it passes through the RC filter and reaches the set input terminal S of the signal latch. The set input terminal S of the signal latch is active at low level, the signal latch is set, and a high-voltage duty cycle signal is output. Q is high. When the narrow pulse of the first narrow pulse signal PWM_R disappears and becomes low again, the first high voltage MOS field effect transistor NM1 is turned off. Point n1 is charged through the first diode d1, and the final voltage is equal to the BST voltage. The voltage output from the RC filter to the set input terminal S of the signal latch also becomes the BST voltage, but the output of the signal latch remains at a high level, as shown in signal Q in FIG. 4 .

When PWM becomes low, the second narrow pulse signal PWM_F becomes high, the second high-voltage MOS field effect transistor NM2 is turned on, and the voltage at point n2 of the level shift module connected to the zero-setting input terminal R of the signal latch is pulled down , the current passes through the second diode d2. When the voltage at point n2 is lower than the SW of the floating power supply and the voltage difference is greater than the threshold voltage of the second clamping transistor Q2, the second clamping transistor Q2 is turned on. At this time, part of the current passes through the second clamping transistor Q2, and the voltage at point n2 will not decrease any more, and is clamped by the second clamping transistor Q2. In this way, the voltage difference from the positive pole BST of the floating power supply to point n2 will not be too large, and the signal input to the zero-setting input terminal R of the signal latch will not cause damage to the signal latch because it is too low. After the voltage at point n2 becomes low, it passes through the RC filter and reaches the zero-setting input terminal R of the signal latch. The zero-setting input terminal R of the signal latch is active at low level, the signal latch is reset, and the high-voltage duty ratio of the output Signal Q goes low, see signal Q in FIG. 4 . When the narrow pulse of the second narrow pulse signal PWM_F disappears and becomes low again, the second high-voltage MOS field effect transistor NM2 is turned off, the voltage at point n2 is charged through the resistor R2, and the final voltage is equal to the BST voltage, and the RC filter is output to the signal latch The voltage at the zero-setting input terminal R also becomes the BST voltage, but the output of the signal latch remains low.

When the BST and SW voltages of the floating power supply become low at the same time, n1 and n2 can discharge the voltage of n1 and n2 points through the first diode d1 and the second diode d2, so that the voltage of n1 and n2 will not be higher than the floating Too much positive BST and ground SW of the power supply will destroy the subsequent circuit.

The present invention has a simple structure, and can ensure the entire level shift through the clamping effect of the first diode d1 and the second diode d2, or the first clamping MOS field effect transistor NM3 and the second clamping MOS field effect transistor NM4 The stability of the bit circuit improves the reliability of the circuit. Compared with the solutions in the prior art, the invention reduces the manufacturing cost and is beneficial to popularization and application.

The above descriptions are only preferred embodiments of the present invention, and those skilled in the art know that various changes or equivalent replacements can be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, the features and examples may be modified to adapt a particular situation and material to the teachings of the invention without departing from the spirit and scope of the invention. Therefore, the present invention is not limited by the specific embodiments disclosed here, and all embodiments falling within the scope of the claims of the present application belong to the protection scope of the present invention.

Claims (10)

1. A level shift circuit, used to control the on-off of a power tube, is characterized in that, comprising: a narrow pulse generator, a level shift module, a signal latch, a driver stage circuit; The narrow pulse generator is used to output the first narrow pulse signal according to the rising edge of the low-voltage duty ratio signal, and output the second narrow pulse signal according to the falling edge of the input low-voltage duty ratio signal, and the first narrow pulse signal signal and the second narrow pulse signal are faster than the low-voltage duty ratio signal, the power supply terminal of the narrow pulse generator is connected to the low-voltage power supply, and the input terminal of the narrow pulse generator is connected to the low-voltage duty ratio signal. empty ratio signal; The level shift module is used to reverse the first narrow pulse signal and raise the potential to obtain a first high-level reverse signal between the positive pole of the floating power supply and the ground, and reverse the second narrow pulse signal and Raise the potential to obtain a second high-level reverse signal between the positive pole of the floating power supply and the ground, the first input terminal of the level shift module is connected to the first narrow pulse signal, and the first narrow pulse signal of the level shift module The second input terminal is connected to the second narrow pulse signal; The signal latch is used to output a high-voltage duty ratio signal according to the first high-level inversion signal and the second high-level inversion signal, and the set input terminal of the signal latch is connected to the first high-level inversion signal. A level inversion signal, the zeroing input terminal is connected to the second high level inversion signal; The driving stage circuit is used to control the opening and closing of the power tube according to the high voltage duty cycle signal, the input end of the driving stage circuit is connected to the high voltage duty cycle signal, and the output end is connected to the power tube grid. 2. A level shifting circuit according to claim 1, wherein the level shifting module comprises a first high voltage MOS field effect transistor, a second high voltage MOS field effect transistor, a first clamping MOS field effect transistor tube, the second clamp MOS field effect tube, the first resistor, and the second resistor; The gate of the first high-voltage MOS field effect transistor is the first input terminal, connected to the first narrow pulse signal, the source is connected to the ground of the low-voltage power supply, and the drain is connected to the first clamping MOS source of the FET, The gate of the first clamp MOS field effect transistor is connected to the ground of the floating power supply, the drain is connected to the positive pole of the floating power supply, the first resistor is connected between the drain and the source, and the signal latch The set input terminal of the device is connected between the drain of the first high voltage MOS field effect transistor and the source of the first clamping MOS field effect transistor; The gate of the second high-voltage MOS field effect transistor is the second input terminal, connected to the second narrow pulse signal, the source is connected to the ground of the low-voltage power supply, and the drain is connected to the second clamping MOS source of the FET, The gate of the second clamping MOS field effect transistor is connected to the ground of the floating power supply, the drain is connected to the positive pole of the floating power supply, the second resistor is connected between the drain and the source, and the signal latch The zero-setting input terminal of the device is connected between the drain of the second high voltage MOS field effect transistor and the source of the second clamping MOS field effect transistor. 3 . The level shift circuit according to claim 2 , wherein the resistance values of the first resistor and the second resistor are both in the range of 1 kΩ˜10 kΩ. 4 . 4. A level shift circuit according to claim 2, wherein the threshold voltages of the first high voltage MOS field effect transistor and the second high voltage MOS field effect transistor are both greater than the first clamping MOS field effect transistor The threshold voltage of the effect transistor and the second clamp MOS field effect transistor. 5. A level shift circuit according to claim 1, wherein the level shift module comprises a first high voltage MOS field effect transistor, a second high voltage MOS field effect transistor, a first clamping transistor, a second Two clamping transistors, a first diode, and a second diode; The gate of the first high-voltage MOS field effect transistor is the first input terminal, connected to the first narrow pulse signal, the source is connected to the ground of the low-voltage power supply, and the drain is connected to the first clamping transistor the emitter, The base of the first clamping transistor is connected to the ground of the floating power supply, the collector is connected to the positive pole of the floating power supply, and the set input terminal of the signal latch is connected to the first high voltage MOS field effect transistor between the drain and the emitter of the first clamping transistor, The cathode of the first diode is connected to the collector of the first clamping transistor, and the anode is connected to the emitter of the first clamping transistor; The gate of the second high-voltage MOS field effect transistor is the second input terminal, connected to the second narrow pulse signal, the source is connected to the ground of the low-voltage power supply, and the drain is connected to the second clamping transistor the emitter, The base of the second clamping transistor is connected to the ground of the floating power supply, the collector is connected to the positive pole of the floating power supply, and the zero-setting input terminal of the signal latch is connected to the second high-voltage MOS field effect transistor between the drain and the emitter of the second clamping transistor, The cathode of the second diode is connected to the collector of the second clamping transistor, and the anode is connected to the emitter of the second clamping transistor. 6 . The level shift circuit according to claim 5 , wherein the resistance values of the first diode and the second diode are both in the range of 1 kΩ˜10 kΩ. 7. A level shift circuit according to claim 5, characterized in that the threshold voltages of the first high voltage MOS field effect transistor and the second high voltage MOS field effect transistor are both greater than the first clamping transistor and the Threshold voltage of the second clamp transistor. 8 . The level shift circuit according to claim 1 , wherein the potential difference between the positive electrode of the floating power supply and the ground is 10-20V. 9. A kind of level shifting circuit according to claim 1, is characterized in that, also comprises noise filtering circuit; The first high-level inverted signal output by the level shift module is connected to the set input terminal of the signal latch through the noise filter circuit, The second high-level inverted signal output by the level shift module is connected to the zero-setting input terminal of the signal latch through the noise filter circuit. 10. A kind of level shifting circuit according to claim 9, it is characterized in that, described noise filtering circuit is made up of two groups of RC filters; One group of described RC filters is used for inverting the first high level After the signal is filtered, it is output to the set input terminal of the signal latch, and the other set of RC filters is used to filter the second high level reverse signal and then output to the zero input of the signal latch end.