CN204244063U - Anti-phase buck-boost type inverter drive circuit - Google Patents

Abstract

The disclosure relates to a kind of anti-phase buck-boost type inverter drive circuit, and this drive circuit comprises: high side power transistor, has the source drain path be coupling between first node and Section Point; And low side power transistor, there is the source drain path be coupling between Section Point and the 3rd node.High side drive circuit have be configured to receive drive singal input and comprise the output being configured to the control terminal driving described high side power transistor.High side drive circuit is configured as capacitive drive device and operates.Low side drive circuit has the input of the drive singal being configured to reception complementation and comprises the output being configured to the control terminal driving described low side power transistor.Low side drive circuit is configured to operate as level shift driver.

Description

Anti-phase buck-boost type inverter drive circuit

Technical field

The disclosure relates generally to buck-boost type converter circuit, and relates more specifically to drive circuit.

Background technology

DC/DC converter circuit is widely used in battery powered portable set.The example of such equipment comprises: smart phone, intelligent watch, camera, media player and other portable digital devices many.In order to extending battery life, those skilled in the art recognize that the efficient operation needed under wide loading range.In a lot of example, the whole efficiency of equipment is limited to the efficiency of comprised anti-phase buck-boost type converter.The reason of this problem is because there is larger switching loss in anti-phase buck-boost type converter, and anti-phase buck-boost type converter needs more complicated drive circuit design.Correspondingly, this area needs to carry out maximized battery life by the efficiency promoting anti-phase buck-boost type converter.

Utility model content

In order to promote the efficiency of anti-phase buck-boost type converter, disclose driver architecture, this framework provides the light load efficiency of lifting.This framework employs different Driving technique for high side and low side power transistor.Such as, high-side driver uses capacitive drive technology and low side driver to use level shift Driving technique.

In an embodiment, a kind of circuit comprises: high side power transistor, has the source drain path be coupling between first node and Section Point; Low side power transistor, has the source drain path be coupling between Section Point and the 3rd node; High side drive circuit, have and be configured to receive the input of drive singal and be configured to the output of the control terminal driving described high side power transistor, described high side drive circuit comprises capacitive drive device; And low side drive circuit, have and be configured to receive the input of complementary drive singal and be configured to the output of the control terminal driving described low side power transistor, described low side drive circuit comprises level shift driver.

Preferably, described first node is coupled to receive positive voltage, and described 3rd node is configured to export negative supply voltage, and described circuit is included in the ground connection load circuit be coupled between described 3rd node and described Section Point further.

Preferably, described capacitive drive device comprises: the first half-bridge driver, has the input in response to described drive singal; And first bootstrap capacitor, between the output being coupling in described first half-bridge driver and the described control terminal of described high side power transistor; And described level shift driver comprises: level shift circuit, has the input of the drive singal in response to described complementation; And second half-bridge driver, have in response to the output of described level shift circuit input and be coupled to the output of described control terminal of described low side power transistor.

Preferably, described level shift driver comprises adjuster circuit further, and described adjuster circuit is configured to generate clamp voltage, thus to described level shift circuit and described second half-bridge driver supply power.

Preferably, described capacitive drive device comprises further: negative circuit, is configured to the output of anti-phase described first half-bridge driver; Second bootstrap capacitor, is coupling between the output of described negative circuit and the 4th node; And transistor, have the source drain path be coupling between the described control terminal of described high side power transistor and described Section Point, described transistor has the control terminal being coupled to described 4th node.

Preferably, described capacitive drive device comprises further: switching transistor, have the source-drain path be coupling between described first bootstrap capacitor and the control terminal of described high side power transistor, the control terminal of wherein said switching transistor is coupled to described first node.

Preferably, described capacitive drive device comprises diode further, and described diode-coupled is between described first node and the 5th node, and described 5th node locating is between described first bootstrap capacitor and described switching transistor.

Preferably, described capacitive drive device comprises clamp circuit further, and described clamp circuit is coupling between the described control terminal of described transistor and described Section Point.

Preferably, this circuit comprises control circuit for pulse-width modulation further, and described control circuit for pulse-width modulation is configured to generate the drive singal of described drive singal and described complementation as pwm signal.

Preferably, this circuit comprises feedback circuit further, and described feedback circuit is coupling between described 3rd node and the input of described control circuit for pulse-width modulation.

Preferably, this circuit comprises current sensing circuit further, and described current sensing circuit is configured to the electric current of senses flow through described high side power transistor, and current sensing signal is exported to the input of described control circuit for pulse-width modulation.

Preferably, this circuit comprises non-continuous mode testing circuit further, described non-continuous mode testing circuit is coupled to described low side power transistor, and is configured to the non-continuous mode detection signal of the input generated for being applied to described control circuit for pulse-width modulation.

Preferably, described circuit is implemented as integrated circuit.

Technical scheme of the present disclosure can promote the efficiency of anti-phase buck-boost type converter, discloses driver architecture, and this framework provides the light load efficiency of lifting.

Accompanying drawing explanation

For a more complete understanding of the present disclosure and advantage, be described with reference to the accompanying drawings, wherein:

Fig. 1 is the circuit diagram of anti-phase buck-boost type converter circuit;

Fig. 2 shows the circuit diagram of the driving operation of anti-phase buck-boost type converter;

Fig. 3 shows the underloaded work wave of the driver of Fig. 2;

Fig. 4 shows the circuit diagram of the driving operation of anti-phase buck-boost type converter;

Fig. 5 shows the underloaded work wave of the driver of Fig. 4;

Fig. 6 is the comparison inductor of the driver shown in Fig. 2 and Fig. 4 and the Rdson power loss curve relative to load.

Fig. 7 is the curve of the efficiency of comparison diagram 2 and the driver shown in Fig. 4;

Fig. 8 shows the circuit diagram of the driving operation of anti-phase buck-boost type converter;

Fig. 9 shows the underloaded work wave of the driver of Fig. 8; And

Figure 10 is the curve of the efficiency of comparison diagram 4 and the driver shown in Fig. 8.

Embodiment

The circuit diagram of the anti-phase buck-boost type converter circuit 10 of synchronized model is shown referring now to Fig. 1, Fig. 1.This circuit comprises pulse-width modulation (PWM) control circuit (control module) 12, drive circuit 14, MOS circuit 16 and load circuit (LC) 18.

Control circuit 12 comprises pierce circuit (OSC) 19, swings device circuit (OSC) 19 and is configured to generate sawtooth oscillation signal and impulse oscillation signal.Two signals have same frequency.Impulse oscillation signal is applied to control logic circuit 23, is used as such as sequential (clock) reference signal.Electric current converts the current signal 20 of sensing to voltage signal 22 to voltage conversion circuit (I to V) 21.(by summing circuit 24) is added to sawtooth oscillation signal, to generate ramp signal 26 after voltage signal 22.Ramp signal 26 is applied to the first input of comparator (Comp) 33.Bleeder circuit 28 receives reference voltage VREF and generates the reference signal 30 of dividing potential drop.Bleeder circuit 28 is coupling between reference voltage and output node Vo2.The reference signal 30 of dividing potential drop is transferred through trsanscondutance amplifier (Gm) 31, and with generating reference signal 32, this reference signal 32 is applied to the second input of comparator (Comp) 33.Comparator (Comp) 33 compares ramp signal 26 and reference signal 32, to generate the duty cycle control signal 34 being applied to control logic 23.Control logic 23 according to impulse oscillation signal process duty cycle control signal 34, to export the first pwm control signal 36 (driving for high side) and the second pwm control signal 38 (for low side drive).These signals 36 and 38 can be called DRV and DRV (inverse).

Drive circuit 14 receives the first control signal 36 and the second control signal 38 and generates high side control signal 44 and low side control signal 46.In the example of the embodiment of drive circuit 14, the first control signal 36 and the second control signal 38 are undertaken processing to generate high side control signal 44 and low side control signal 46 respectively by level shift circuit 40 and driving amplifier 42.As described herein, this execution mode more at large can illustrate with reference to Fig. 2.It shall yet further be noted that in other embodiments, as described herein, drive circuit 14 can also be implemented as Fig. 4 or Fig. 8.To each execution mode of reference correspondingly shown in coverage diagram 2, Fig. 4 and Fig. 8 of the drive circuit 14 of Fig. 1.

MOS circuit 16 comprises high side drive transistors (MHS) and low side drive transistors (MLS), and its source drain path is connected in series between node LX2 input voltage node VIN and output node Vo2 at node LX2 place.Transistor MHS and MLS is N-shaped power MOSFET device.More specifically, in an embodiment, transistor MHS and LHS is power NDMOS device.High-side transistor MHS is configured to be controlled by high side control signal 44, and low side transistors MLS is configured to be controlled by low side control signal 46.Electric current in the circuit paths formed by the source drain path be connected in series of transistor is sensed by current sensing circuit 48.The output of current sensing circuit comprises the signal 20 of the input being applied to I to V circuit 21.

Load circuit 18 comprises the load inductance (being expressed as resistive component Rind and inductive component L2) between the reference power source node being coupling in node LX2 and such as ground connection (GND).Load circuit 18 comprises the load capacitance (being expressed as resistive component Rc and capacitive component CL) be coupling between output node Vo2 and ground connection reference power source node further.Load circuit 18 comprises the load resistance (being expressed as resistive component RL) be coupling between output node Vo2 and ground connection reference power source node further.

Corresponding to control circuit 12, drive circuit 14, MOS circuit 16 and load circuit 18, the power loss of anti-phase buck-boost type converter 10 can be divided into four parts.So, there is basic control module loss, driver losses, MOS loss and load (inductor) loss.In these losses, MOS loss is made up of conduction loss and switching loss.Power loss can be represented according to following equation:

P _loss＝V _IN×I _q+P _{loss，driver}+P _{loss，switch}+P _loss，rdson+P _loss，ind(1)

In equation (1), because actuating speed is identical with MOS, therefore V can be supposed _iN× I _qand P _{loss, switch}all constant.So, be applicable to only being analyzed as follows loss:

Inductor loss:

P _loss，ind＝I _ind，rms ²×R _ind(2)

Drain-to-source ohmic conduction losses (Rdson):

P _loss，rdson＝I _{highside，rms} ²×R _dson，MHS+I _{lowside，rms} ²×R _dson，MLS...(3)

Driver losses:

P _{loss，driver}＝P _{loss，driver，quie}+P _{loss，driver，switch}(4)

In equation (2)-equation (4), P _{loss, driver, quie}driver quiescent dissipation, P _{loss, driver, switch}driver switch loss, P _{dson, MHS}high side power MOS conduct electricity resistance, R _{dson, MLS}lowside power MOS conduct electricity resistance, and R _indit is inductor internal resistance.When considering portable set application, use the inductor of inner wrapping, and its internal resistance can be larger.In this case, inductor losses can become the signal portion forming total losses.

Show the driving operation of the anti-phase buck-boost type converter 10 of Fig. 1 referring now to Fig. 2, Fig. 2, illustrated therein is additional circuit details.Non-continuous mode detects (DMD) module 80 for detecting the electric current across transistor MLS when when lowside power MOS MLS conducting high side power MOS MLH turns off.When the electric current sensed is reduced to zero, DMD CMOS macro cell is applied to the signal (SDMD) of control logic (see Fig. 1), turns off to make lowside power MOS MLS.After turning off low side transistors MLS because DMD detects, vibration cancellation module 82 eliminates up time vibration (ringing) (relative to the load inductor L2 and output capacitor Co2) on node LX2 within the time period be all turned off at high-side transistor MHS and low side transistors MLS.

The circuit of Fig. 2 comprises high side level shifter (level shift 1) 84, its for by signal logic power supply between the voltage being displaced to voltage PCLAMP and node LX2 between builtin voltage VDD and reference voltage ground connection (GND).This process can use at least two-stage level shift circuit and being assisted by bootstrap capacitor CBOOT.The output of level shifter 84 is applied to the input of the half-bridge drive circuit formed by transistor M1 and M2 (also being powered by the voltage PCLAMP regulated) by inverter 86 (being powered by the voltage PCLAMP regulated).The output of half-bridge drive circuit is applied to the gate terminal of high side power transistor MHS.There is provided downside level shifter (level shift 2) with by signal logic power supply between the voltage being displaced to voltage NCLAMP and node Vo2 between builtin voltage VDD and power source reference voltage (GND).This circuit can only need one-level level shift circuit.The output of level shift 162 is applied to the input of the half-bridge drive circuit formed by transistor M3 and M4 (also being powered by the voltage NCLAMP regulated) by inverter 164 (being powered by the voltage NCLAMP regulated).The output of half-bridge driver circuit is applied to the gate terminal of low side power transistor MLS.So, in this configuration, at least provide level shift circuit 40 (Fig. 1) by shift unit 84/162, and at least provide amplifier 42 (Fig. 1) by transistor M1/M2 and M3/M4.

For the regulating circuit receiver voltage VIN of formation voltage PCLAMP and the mode as shown that comprises connect current source 88, Zener diode D1 and junction diode D2, transistor M5 and resistor 90.For the regulating circuit receiver voltage VIN of formation voltage NCLAMP and the mode as shown that the comprises current source 170, Zener diode D3, transistor M6 and the resistor R3 that connect.Drive singal DRV is applied to inverter 160, is then applied to level shift 2 circuit 162.It is anti-phase that output from level shift 2 circuit 162 is inverted device 164, to guarantee that high lateral circuit and low-side circuitry activated simultaneously.

Suppose that converter circuit operates in equilibrium mode.The work wave of the light load operation of the circuit of Fig. 2 has been shown in Fig. 3.Logical one is become from logical zero at stage 1, t=0, DRV signal.Lowside power MOS MLS turns off in response to transistor M4, and then high side power MOS MHS connects.Electric current in inductor L2 starts to increase.The voltage at posterior nodal point LX2 place be pulled to VIN.Because diode D2 is reverse biased, therefore the initial voltage on capacitor CBOOT equals VCLAMPD1-VGS5-0.7.So high side voltage is:

V _gs，high＝(VCLAMPD1-VGS5-0.7)×CBOOT/(CBOOT+C _gs，high).

Logical zero is become from logical one at stage 2, t=DT, DRV signal.High side power MOSMHS turns off in response to transistor M2, and then lowside power MOS connects.Electric current in inductor L2 starts to reduce.The voltage at node LX2 place is pulled down to the voltage at node Vo2 place by low side power transistor MLS.Now, capacitor CBOOT charges to VCLAMPD1-VGS5-0.7 again, and the electric energy saved in inductor L2 can transfer to output node Vo2.If load is enough light, control loop can enter DCM pattern.

Forward the stage 3 afterwards to, when the electric current in inductor reduces to zero, high side and low side power transistor MHS and MLS turn off, until receive following clock along (oscillation pulse signal) (at time t=T).During this one-phase in stage 3, node LX2 is connected to the reference power source node through vibration arrester 82 ground connection.

The account form of the loss at the underload place of the circuit of Fig. 2 is as follows:

Inductor losses:

$\begin{array}{c}{P}_{\mathrm{loss},\mathrm{ind}}=\frac{1}{T}[{\∫}_0^{\mathrm{DT}}{\left(\frac{V_{\mathrm{IN}}}{L}t\right)}^2\mathrm{dt}+{\∫}_{\mathrm{DT}}^{\mathrm{DT}+D_{2}T}{(\frac{V_{\mathrm{IN}}+V_{O2}}{L}\mathrm{DT}-\frac{V_{O2}}{L}t)}^2\mathrm{dt}+{\∫}_{\mathrm{DT}+D_{2}T}^{T}0\mathrm{dt}]\×R_{\mathrm{ind}}\\ =\frac{1}{3}{T}^2{\left(\frac{V_{\mathrm{IN}}}{L}\right)}^2{D}^3\×R_{\mathrm{ind}}+\frac{1}{3}{T}^2{\left(\frac{V_{O2}}{L}\right)}^2{\left(\frac{V_{\mathrm{IN}}}{V_{O2}}\right)}^3{D}^3\×R_{\mathrm{ind}}\end{array}---\left(5\right)$

Wherein: $D=\frac{\sqrt{{2\mathrm{LI}}_{02}{V}_{02}}}{\mathrm{VIN}}---\left(6\right)$ $D=\frac{\sqrt{{2\mathrm{LI}}_{02}{V}_{02}}}{\mathrm{VIN}}$

So:

$\begin{array}{c}{P}_{\mathrm{loss},\mathrm{ind}}=\frac{1}{3\mathrm{VIN}}\sqrt{\frac{T}{L}}{\left({2I}_{02}{V}_{O2}\right)}^{3/2}\×R_{\mathrm{ind}}+\frac{1}{{3V}_{O2}}\sqrt{\frac{T}{L}}{\left({2I}_{02}{V}_{O2}\right)}^{3/2}\×R_{\mathrm{ind}}\\ =(A_{\mathrm{hs}}+A_{\mathrm{ls}})\×{\left(I_{02}\right)}^{3/2}\×R_{\mathrm{ind}}\end{array}---\left(7\right)$

Drain electrode is to source resistance conduction loss (Rdson):

$\begin{array}{c}{P}_{\mathrm{loss},\mathrm{rdson}}=\frac{1}{3\mathrm{VIN}}\sqrt{\frac{T}{L}}{\left({2I}_{02}{V}_{O2}\right)}^{3/2}\×R_{\mathrm{on},\mathrm{MHS}}+\frac{1}{{3V}_{O2}}\sqrt{\frac{T}{L}}{\left({2I}_{02}{V}_{O2}\right)}^{3/2}\×R_{\mathrm{on},\mathrm{LHS}}\\ =A_{\mathrm{hs}}\×{\left(I_{02}\right)}^{3/2}\×R_{\mathrm{on},\mathrm{MHS}}+A_{\mathrm{ls}}\×{\left(I_{02}\right)}^{3/2}\×R_{\mathrm{on},\mathrm{LHS}}\end{array}---\left(8\right)$

Driver losses:

P _{loss，driver}＝P _{loss，driver，regulator}+P _{loss，driver，levelshift}+P _{loss，driver，switch}(9)

$P_{\mathrm{loss},\mathrm{hs},\mathrm{driver},\mathrm{switch}}=\frac{1}{T}\∫(V_{\mathrm{ds},M5}+V_{D2})\mathrm{dt}---\left(10\right)$

$P_{\mathrm{loss},\mathrm{ls},\mathrm{driver},\mathrm{switch}}=\frac{1}{T}\∫(V_{\mathrm{ds},M6}+V_{\mathrm{ds},M3})\mathrm{dt}---\left(11\right)$

$\begin{array}{c}{P}_{\mathrm{loss},\mathrm{driver}}=P_{\mathrm{loss},\mathrm{driver},\mathrm{regulator}}+P_{\mathrm{loss},\mathrm{driver},\mathrm{levelshift}}+\frac{1}{T}\∫(V_{\mathrm{ds},M5}+V_{D2})\mathrm{dt}+\frac{1}{T}\∫(V_{\mathrm{ds},M6}+\\ V_{\mathrm{ds},M3})\mathrm{dt}\end{array}---\left(12\right)$

To notice, the drive circuit of Fig. 2 needs two adjusters and multiple level shifter.From equation (12), will notice, driver also has significant switching loss.If the response time of level shifter is such as about 2ns or following, the operation of the circuit shown in Fig. 2 can experience significant loss.

The circuit diagram of the driving operation of the anti-phase buck-boost type converter of Fig. 1 is showed referring now to Fig. 4, Fig. 4.In the configuration, capacitive character buck-boost type driving method is embodied.The driver of Fig. 4 does not need level shift circuit needed for Fig. 2 and adjuster.In this case, the driver of Fig. 4 carrys out driving power MOS transistor by using the capacitor circuit of coupling.

Drive singal DRV is received and is applied to inverter 60, and thus complementary drive singal DRV and DRV (inverse) is for available.Buffer amplifier circuit 62 and 64 receives drive singal DRV and DRV (inverse) and generates complementary buffering signals 66 and 68 respectively.Circuit 62 and 44 is powered by voltage source node VIN.High side half-bridge drive circuit (also being powered by the power supply node VIN) Received signal strength 66 formed by transistor M1 and M2 and in node A output first control signal.The low-side half-bridge drive circuit Received signal strength 68 formed by transistor M3 and M4 and export the second control signal in Node B.The capacitor circuit of coupling is formed in high side and downside by boost capacitor paired As described in detail below.

First forward high lateral circuit to, first control signal at node A place is applied to inverter circuit 70, thus generates the first complementary control signal.Noninverting the first control signal (at node A place) is applied to the bootstrap capacitor CBOOT1 be coupling between node A and node VB1.Anti-phase the first control signal (from inverter 70) is applied to the bootstrap capacitor CBOOT3 between output and node VB3 being coupling in inverter 70.Junction diode D11 is coupling between node VB1 (at negative electrode place) and input voltage node VIN (at anode place).Switch S 1 is coupling between node VB1 and node C.Switch may be embodied as MOS transistor (see Fig. 8).Node C is connected to the gate terminal of high side power transistor MHS, and wherein, current i 1 is applied in by capacitor CBOOT1 and operates with driving transistors.MOS transistor M5 has the source drain path be coupling between node C and node LX2.The gate terminal of transistor M5 is connected to node VB3.Zener diode D12 is coupling between node VB3 (at negative electrode place) and node LX2 (at anode place).Resistor R11 is coupling between node C and node LX2.

About low-side circuitry, second control signal at Node B place is applied to inverter circuit 72, thus generates the second complementary control signal.Noninverting the second control signal (at Node B place) is applied to the bootstrap capacitor CBOOT2 be coupling between Node B and node VB2.Node VB2 is connected to the gate terminal of lowside power MOS transistor MLS, and wherein current i 2 is applied in by capacitor CBOOT2 and operates with driving transistors.Anti-phase the second control signal (from inverter 72) is applied to the bootstrap capacitor CBOOT4 between output and node VB4 being coupling in inverter 72.MOS transistor M6 has the source drain path be coupling between node VB2 and output node Vo2.The gate terminal of transistor M6 is connected to node VB4.Zener diode D13 is coupling between node VB4 (negative electrode) and node Vo2 (anode).Resistor R12 is coupling between node VB2 and node Vo2.

Suppose that the converter circuit of Fig. 4 operates in equilibrium mode.Fig. 5 shows the work wave of the light load operation of the circuit of Fig. 4.Logical one is become from logical zero at stage 1, t=0, DRV signal.Capacitor CBOOT1 has the initial voltage of about VIN-0.7.Low side power transistor MLS turns off.High-side driver transistor M1 switches to VIN from 0.Node VB1 voltage is increased to VIN+VIN-0.7.Then some electric charges (through capacitor CBOOT1) are discharged to the gate terminal of high side power transistor MHS, and transistor MHS also conducting.The voltage at posterior nodal point LX2 place be pulled to VIN from the voltage of output node Vo2.

Logical zero is become from logical one at stage 2, t=DT, DRV signal.High side power device transistor M1 switches to reference voltage ground connection from VIN.The voltage couples at posterior nodal point VB1 place to VIN-VD.Switch S 1 disconnects, and is not connected with capacitor CBOOT1 to make the grid of transistor MHS.Electric current, through diode D11, in the opposite direction through capacitor CBOOT1, flow to ground connection through transistor M2.Transistor M5 conducting, and high side power transistor MHS turns off.Afterwards, the voltage couples at node VB2 place is paramount, and low side power transistor MLS conducting.Inductive current starts to reduce.If load is light, then this loop is also operated in PWM mode.When the electric current in inductor reduces to zero, low side power transistor MLS does not turn off, until receive following clock along (oscillation pulse signal) at time t=T.Thus electric current in inductor current is depicted as rightabout.

The underloaded loss calculation mode of the circuit of Fig. 4 is as follows:

Inductor losses:

$P_{\mathrm{loss},\mathrm{ind}}=\frac{1}{T}[{\∫}_0^{\mathrm{DT}}{(Y_0+\frac{V_{\mathrm{IN}}}{L}t)}^2\mathrm{dt}+{\∫}_0^{T-\mathrm{DT}}{(Y_0+\frac{V_{02}}{L}t)}^2\mathrm{dt}]\×R_{\mathrm{ind}}---\left(13\right)$

Wherein: $D=\frac{V_{02}}{\mathrm{VIN}+V_{02}}\mathrm{and}{I}_0=\frac{1}{T}{\∫}_0^{T-\mathrm{DT}}(Y_0+\frac{V_{02}}{L}t)\mathrm{dt}---\left(14\right)$

$\begin{array}{c}{P}_{\mathrm{loss},\mathrm{ind}}=(\frac{V_{02(V_{\mathrm{IN}}+V_{02})}}{{\mathrm{VIN}}^2}{I_{02}}^2+\frac{1}{12}{\left(\frac{T}{L}\right)}^2\frac{{\mathrm{VIN}}^2{V_{02}}^3}{{(\mathrm{VIN}+V_{02})}^3})\×R_{\mathrm{ind}}(\frac{\mathrm{VIN}+V_{02}}{\mathrm{VIN}}{I_{02}}^2+\\ \frac{1}{12}{\left(\frac{T}{L}\right)}^2\frac{{\mathrm{VIN}}^3{V_{02}}^2}{{(\mathrm{VIN}+V_{02})}^3})\×R_{\mathrm{ind}}\\ =(B_{\mathrm{hs}}+B_{\mathrm{ls}}){I_{02}}^2\×R_{\mathrm{ind}}+(C_{\mathrm{hs}}+C_{\mathrm{ls}})\×R_{\mathrm{ind}}\end{array}---\left(15\right)$

Drain source resistance conduction loss (Rdson):

$\begin{array}{c}{P}_{\mathrm{loss},\mathrm{rdson}}=(\frac{V_{02}(V_{\mathrm{IN}}+V_{02})}{{\mathrm{VIN}}^2}{I_{02}}^2+\frac{1}{12}{\left(\frac{T}{L}\right)}^2\frac{{\mathrm{VIN}}^2{V_{02}}^3}{{(\mathrm{VIN}+V_{02})}^3})\×R_{\mathrm{on},\mathrm{MHS}}+(\frac{\mathrm{VIN}+V_{02}}{\mathrm{VIN}}{I_{02}}^2+\\ \frac{1}{12}{\left(\frac{T}{L}\right)}^2\frac{{\mathrm{VIN}}^3{V_{02}}^2}{{(\mathrm{VIN}+V_{02})}^3})\×R_{\mathrm{on},\mathrm{LHS}}\\ =(B_{\mathrm{hs}}{I_{02}}^2+C_{\mathrm{hs}})\×R_{\mathrm{on},\mathrm{MHS}}+(B_{\mathrm{ls}}{I_{02}}^2+C_{\mathrm{ls}})\×R_{\mathrm{on},\mathrm{LHS}}\end{array}---\left(16\right)$

Driver losses:

P _{loss，driver}＝P _{loss，driver，switch}(17)

Following table compares the operation of the driving method of Fig. 2 and the driving method of Fig. 4:

In nonrestrictive example, consider VIN=3.7V, | Vo2|=4V, inductor resistance is 0.25ohm, high side drive transistors Rdson=0.2ohm and downside Rdson=0.2ohm.Afterwards, for inductor and DMOS conduction loss:

Fig. 2 driver: P _{loss, ind & rdson}=0.6647 × (I ₀₂) ^3/2... .. (18)

Fig. 4 driver: P _{loss, ind & rdson}=1.949I ₀₂ ²+ 0.0028 (19)

Fig. 6 shows according to the inductor of non-restrictive example and the Rdson power loss curve relative to load.The driver that it illustrates Fig. 4 stands more inductor and Rdson loss than the driver of Fig. 2.But, according to upper table, Fig. 4 driver should be noted not because adjuster or level shifter circuit operate the loss produced.These losses that driver for Fig. 2 stands can be very significant.

Fig. 7 shows the curve of the efficiency of the driver shown in comparison diagram 2 and Fig. 4.This curve table is shown in load and stands less loss higher than the driver of Fig. 4 time threshold value (in this example, being about 30mA) than the driver of Fig. 2, and stands higher loss in load lower than the driver than Fig. 2 during threshold value.

The circuit diagram of the driving operation of the anti-phase buck-boost type converter of Fig. 1 is showed referring now to Fig. 8, Fig. 8.In this configuration, the buck-boost type driving method of mixing is illustrated.The driver of Fig. 8 employs level shift circuit and adjuster (compared to Fig. 2) for driving low side power transistor MLS, and the capacitor circuit (compared to Fig. 4) employing coupling is for driving high side power transistor MHS.

Receive drive singal DRV and be applied to inverter 60, thus complementary drive singal DRV and DRV (inverse) is for available.

First high side drive circuit is forwarded to: buffer amplifier circuit 62 (being powered by power supply node VIN) receives drive singal DRV (inverse) and generates buffering signals 66.The high side half-bridge drive circuit Received signal strength 66 formed by transistor M1 and M2 (also being powered by power supply node VIN) and in node GPP output first control signal.The capacitor circuit of coupling is formed on high side by paired boost capacitor.First control signal at node GPP place is applied to inverter circuit 70, thus generates the first complementary control signal.Noninverting the first control signal (node GPP place) is applied to the bootstrap capacitor CB1 be coupling between node GPP and node VB1.Anti-phase the first control signal (from inverter 70) is applied to the bootstrap capacitor CB3 between output and node VB3 being coupling in inverter 70.The MOSFET M7 that diode connects is coupling between node VB1 (at negative electrode place) and input voltage node VIN (at anode place).Transistor M5 (switch S 1, Fig. 4) is coupling between node VB1 and node GP, and wherein the grid of transistor M5 is coupled to input voltage VIN, thus transistor M5 is in response to the voltage at VIN and node VB1 place and conducting.Node GP is connected to the gate terminal of high side power transistor MHS.High side drive singal is generated at node GP by the capacitor be coupled.MOS transistor M8 has the source drain path be coupling between node GP and node LX2.The gate terminal of transistor M8 is connected to node VB3.Zener diode D12 is coupling between node VB3 (negative electrode) and node LX2 (anode).Resistor R1 is also coupling in (in parallel with diode D12) between node VB3 and node LX2.Resistor R2 is coupling between node GP and node LX2.

Forward low side drive circuit to afterwards: drive singal DRV (inverse) is received and is applied to the input of the level shifter 162 of being powered by regulation voltage NCLAMP.Inverter circuit 164 (also being powered by voltage NCLAMP) incoming level displacement drive singal DRV (inverse) and generate buffering signals 166.The half-bridge drive circuit formed by transistor M3 and M4 (having the source drain path of the series coupled be coupling between NCLAMP and output node Vo2) is configured to receive buffering signals 166 and generates low side driving signal at node GN.Node GN is connected to the gate terminal of side power transistor MLS.Generate regulation voltage NCLAMP by circuit 168, this circuit 168 comprises current source 170, this current source 170 in node VCP1 place and Zener diode D3 series coupled, between input voltage node VIN and output voltage node Vo2.MOS transistor M6 is coupled to input node VIN and is configured to formation voltage NCLAMP.The grid of transistor M6 is coupled to node VCP1.Resistor R3 is coupling between the source electrode (wherein formation voltage NCLAMP) of transistor M6 and output node Vo2.

Non-continuous mode detects (DMD) module 80 for detecting the electric current when lowside power MOS is conducting and high side power MOS is shutoff across transistor MLS.When the electric current sensed is reduced to zero, DMD module 80 generates the signal (SDMD) being applied to control logic (see Fig. 1) and turning off to make lowside power MOS MLS.After turning off low side transistors MLS because DMD detects, the ringing on node LX2 is eliminated in vibration cancellation module 82 (being connected in parallel with outputting inductance L2) within the time period all turned off at high-side transistor MHS and low side transistors MLS.Output capacitor Co2 is coupling between output node Vo2 and reference power source ground connection.

Suppose that the converter operation of Fig. 8 is in equilibrium mode.Fig. 9 shows the work wave of the light load operation of the circuit of Fig. 8.Logical one is become from logical zero at stage 1, t=0, DRV signal.Low side power transistor MLS is turned off by transistor M4.In high-side driver, transistor M1 connects and electric current is applied to the grid of transistor MHS.The boost in voltage at node VB1 place is to VIN+VIN-VTHM7, and this voltage is higher than voltage VIN+VTHM5.So now, the voltage at node GP place equals the voltage at node VB1 place.In the configuration, high side power MOS MHS can connect (electric current in response to carrying out sufficient power from capacitor CB1) and electric current in inductor can increase.Thus the voltage at node LX2 place be pulled to VIN.

Logical zero is become from logical one at stage 2, t=DT, DRV signal.Here, transistor M2 connects.Afterwards, the voltage at node GPP place is dragged down.The voltage at node VB1 place is lower than voltage VIN-VTH7, so the transistor M7 that connects via diode of electric current and transistor M2 flows on the rightabout by capacitor CB1.Afterwards, capacitor CB1 changes to voltage VIN-VTH7, makes transistor M5 turn off like this, therefore makes the grid of transistor MHS disconnect from node VB1.Now, transistor M8 conducting.High-side transistor MOS MHS is by the switch off current spilt by transistor M8.Afterwards, the grid of lowside power MOS transistor MLS charges paramount by flowing through the electric current of transistor M6 and M3.Inductor current starts to reduce.

At stage 3, t=(D+D2) T, high side and lowside power MOS transistor MHS and MLS all turn off.Node LX2 is short-circuited to GND by the inductor L2 of electric discharge.

The account form of the underload loss of the circuit of Fig. 8 is as follows:

Inductor losses:

$\begin{array}{c}{P}_{\mathrm{loss},\mathrm{ind}}=\frac{1}{3\mathrm{VIN}}\sqrt{\frac{T}{L}}{\left({2I}_{02}{V}_{O2}\right)}^{3/2}\×R_{\mathrm{ind}}+\frac{1}{{3V}_{O2}}\sqrt{\frac{T}{L}}{\left({2I}_{02}{V}_{O2}\right)}^{3/2}\×R_{\mathrm{ind}}=(A_{\mathrm{hs}}+A_{\mathrm{ls}})\×\\ {\left(I_{02}\right)}^{3/2}\×R_{\mathrm{ind}}\end{array}---\left(20\right)$

Drain source resistance conduction loss (Rdson):

P _loss，rdson＝A _hs×(I ₀₂) ^3/2×R _on，MHS+A _ls×(I ₀₂) ^3/2×R _on，LHS(21)

Driver losses:

P _{loss，driver}＝P _{loss，lowside，driver，regulator}+P _{loss，lowside，driver，levelshtft}+P _{loss，driver，switch}(22)

Consider equation (22), should be understood that compared with the execution mode of Fig. 4, only the loss of downside adjuster and the loss of downside level shift are added into and drive in loss.So the high-side driver in low side driver loss ratio Fig. 2 execution mode is much smaller.

The efficiency of the driver shown in comparison diagram 8 and Fig. 4 is shown referring now to Figure 10, Figure 10.Compare according to the test result between the driver of Fig. 8 and the driver of Fig. 4, notice, the driver of Fig. 8 in threshold value (in this example, the load of about 20mA) below embody the improved efficiency of the driver relative to Fig. 4, and during load more than threshold value (such as, see, the load of 50-70mA), embody the efficiency curve of equivalence.

The driver of Fig. 8 embodies the further advantage of the driver relative to Fig. 4, and wherein circuit can use less area to be fabricated to integrated circuit, and this is not at least because low side driver needs to use the capacitor expending space.

It will be understood by those skilled in the art that and can change materials and methods when maintaining in the scope of the present disclosure.Should also be understood that and present disclose provides except for illustration of a lot of applicable creative concept except the specific context of embodiment.Thus, claims are intended to this technique of material, means, method or step, machinery, manufacture, combination to be included in its scope protected.

Claims (13)

1. a circuit, is characterized in that, comprising:

High side power transistor, has the source drain path be coupling between first node and Section Point;

Low side power transistor, has the source drain path be coupling between described Section Point and the 3rd node;

High side drive circuit, have and be configured to receive the input of drive singal and be configured to the output of the control terminal driving described high side power transistor, described high side drive circuit comprises capacitive drive device; And

Low side drive circuit, have and be configured to receive the input of complementary drive singal and be configured to the output of the control terminal driving described low side power transistor, described low side drive circuit comprises level shift driver.

2. circuit according to claim 1, it is characterized in that, described first node is coupled to receive positive voltage, and described 3rd node is configured to export negative supply voltage, described circuit is included in the ground connection load circuit be coupled between described 3rd node and described Section Point further.

3. circuit according to claim 1, is characterized in that,

Described capacitive drive device comprises:

First half-bridge driver, has the input in response to described drive singal; And

First bootstrap capacitor, between the output being coupling in described first half-bridge driver and the described control terminal of described high side power transistor; And

Described level shift driver comprises:

Level shift circuit, has the input of the drive singal in response to described complementation;

And

Second half-bridge driver, have in response to the output of described level shift circuit input and be coupled to the output of described control terminal of described low side power transistor.

4. circuit according to claim 3, it is characterized in that, described level shift driver comprises adjuster circuit further, and described adjuster circuit is configured to generate clamp voltage, thus to described level shift circuit and described second half-bridge driver supply power.

5. circuit according to claim 3, is characterized in that, described capacitive drive device comprises further:

Negative circuit, is configured to the output of anti-phase described first half-bridge driver;

Second bootstrap capacitor, is coupling between the output of described negative circuit and the 4th node; And

Transistor, has the source drain path be coupling between the described control terminal of described high side power transistor and described Section Point, and described transistor has the control terminal being coupled to described 4th node.

6. circuit according to claim 5, is characterized in that, described capacitive drive device comprises further:

Switching transistor, has the source-drain path be coupling between described first bootstrap capacitor and the control terminal of described high side power transistor, and the control terminal of wherein said switching transistor is coupled to described first node.

7. circuit according to claim 6, it is characterized in that, described capacitive drive device comprises diode further, and described diode-coupled is between described first node and the 5th node, and described 5th node locating is between described first bootstrap capacitor and described switching transistor.

8. circuit according to claim 5, is characterized in that, described capacitive drive device comprises clamp circuit further, and described clamp circuit is coupling between the described control terminal of described transistor and described Section Point.

9. circuit according to claim 1, is characterized in that, comprises control circuit for pulse-width modulation further, and described control circuit for pulse-width modulation is configured to generate the drive singal of described drive singal and described complementation as pwm signal.

10. circuit according to claim 9, is characterized in that, comprises feedback circuit further, and described feedback circuit is coupling between described 3rd node and the input of described control circuit for pulse-width modulation.

11. circuit according to claim 9, it is characterized in that, comprise current sensing circuit further, described current sensing circuit is configured to the electric current of senses flow through described high side power transistor, and current sensing signal is exported to the input of described control circuit for pulse-width modulation.

12. circuit according to claim 9, it is characterized in that, comprise non-continuous mode testing circuit further, described non-continuous mode testing circuit is coupled to described low side power transistor, and is configured to the non-continuous mode detection signal of the input generated for being applied to described control circuit for pulse-width modulation.

13. circuit according to claim 1, is characterized in that, described circuit is implemented as integrated circuit.