JP2020182321A - Gate drive circuit - Google Patents

Abstract

To provide a gate drive circuit that is compact, and has low loss, a large output current, and a wide operating frequency range.SOLUTION: A gate drive circuit includes a first level shift circuit that widens the amplitude voltage of a switching signal, a pre-amplifier circuit, and a current amplifier circuit. The current amplifier circuit includes first and second conductive type first and second MOSFETs connected in series. A source terminal of the first MOSFET is connected to a first power supply terminal of positive power supply voltage, a source terminal of the second MOSFET is connected to a second power supply terminal of negative power supply voltage, drain terminals of the first and second MOSFETs are connected to gate terminals of a transistor, a gate terminal of the first MOSFET is connected to an output node of the pre-amplifier circuit via a capacitor, and is connected to the first power supply terminal via a resistor, a gate terminal of the second MOSFET is connected to an output node of the pre-amplifier circuit, and an output node of the gate drive circuit is connected to the first power supply terminal via a bypass circuit.SELECTED DRAWING: Figure 2

Description

The present invention relates to a gate drive circuit, and more particularly to a gate drive circuit of a transistor used in a power conversion device.

In a power conversion device such as an inverter, a gate drive circuit that drives a power device such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) at high speed outputs as described in Patent Document 1. Push-pull circuit of emitter follower using NPN transistor and PNP transistor in the stage, or push-pull using N-channel type (Nch) and P-channel type (Pch) MOSFET in the output stage as described in Patent Document 2. The output current is amplified by the circuit.

Japanese Unexamined Patent Publication No. 2015-126596 Japanese Unexamined Patent Publication No. 2013-179828

As described in Patent Document 1, in a push-pull circuit of an emitter follower using an NPN transistor and a PNP transistor in the output stage, a discrete transistor of a single element that is generally used has a frequency of several tens to several hundreds of kHz. The rated current peak of high-frequency operation products is as low as several amperes. Therefore, when driving a semiconductor module having a large rating, for example, as shown in FIG. 3 of Patent Document 1, a plurality of push-pull circuits in the output stage of the gate drive circuit are connected in parallel to each stage. It is necessary to keep the current peak within the rating of the transistor.

As the number of push-pull circuits in parallel increases, the base current also increases, so the output current of the pre-stage circuit must also be amplified, which causes problems such as the number of parts, circuit scale, and mounting area, which increases the cost. The gate drive circuit disclosed in Patent Document 1 is not suitable for driving a large-capacity transistor.

Further, in the gate drive circuit disclosed in Patent Document 2, the output current is amplified by a push-pull circuit using a Pch MOSFET in the upper stage and an Nch MOSFET in the lower stage of the output stage, and an arm short circuit in which the MOSFETs in the upper and lower stages are turned on at the same time occurs. The short-circuit current when it occurs is suppressed to less than the rated current of the MOSFET, and the current limiting resistance that also serves as the gate resistance is set between the drain terminal of the MOSFET in the upper and lower stages and the output node so that the MOSFET does not fail due to loss or heat generation due to the short-circuit current. They are connected in between.

Further, the gate power supply of the gate drive circuit is generated by using the first and second DC power supplies, and the emitter terminals of the driven IGBT are the negative terminal of the first DC power supply and the positive terminal of the second DC power supply. The driving voltage of the IGBT fluctuates positively and negatively with reference to the potentials of the connection points of the negative terminal of the first DC power supply and the positive terminal of the second DC power supply. Further, the control circuit drives the Pch MOSFET and the Nch MOSFET of the current amplification unit of the gate drive circuit with reference to the negative terminal of the second DC power supply.

For example, in high-frequency switching of 100 kHz, in addition to a large loss in the current limiting resistor, the current limiting resistor also serves as a gate resistor, so when driving a large-capacity transistor at high speed, the resistance value of the current limiting resistor Cannot be increased. Therefore, it is necessary to select MOSFETs having a large rated current that can withstand the arm short-circuit current for the Pch MOSFET and Nch MOSFET in the output stage of the gate drive circuit, which causes a problem that the mounting area is large and the cost is high.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a gate drive circuit having a small size, low loss, a large output current, and a wide operating frequency range.

The gate drive circuit according to the present invention is a gate drive circuit that drives the gate of a transistor based on a switching signal input from a control circuit, and includes a first level shift circuit that widens the amplitude voltage of the switching signal. A pre-amplifier circuit that amplifies the output current of the first level shift circuit and a current amplifier circuit that amplifies the output current of the pre-amplifier circuit are provided, and the current amplifier circuit is connected in series to the first conductive circuit. It has a first MOSFET of the type and a second MOSFET of the second conductive type, and the source terminal of the first MOSFET is connected to the first power terminal which gives a positive power supply voltage, and the second MOSFET The source terminal of is connected to a second power supply terminal that gives a negative power supply voltage, and the drain terminal of the first MOSFET and the drain terminal of the second MOSFET serve as an output node of the gate drive circuit of the transistor. It is connected to the gate terminal, the gate terminal of the first MOSFET is connected to the output node of the pre-amplifier circuit via a capacitor, and is connected to the first power supply terminal via a resistor, and the second The gate terminal of the MOSFET is connected to the output node of the pre-amplifier circuit, and the output node of the gate drive circuit is connected to the first power supply terminal via a bypass circuit.

According to the gate drive circuit according to the present invention, the transistor can be driven by the gate voltage changing in the range of the positive power supply voltage and the negative power supply voltage, and the malfunction of the transistor due to noise can be prevented. Further, by providing a bypass circuit between the output node of the gate drive circuit and the first power supply terminal, the input capacitance of the transistor can be charged, so that the transistor can be kept on even at a low switching frequency, and the operating frequency can be increased. The range becomes wider.

It is a circuit diagram which shows the structure of the inverter circuit composed of the power device driven by the gate drive circuit of Embodiment 1 which concerns on this invention. It is a circuit diagram which shows the structure of the gate drive circuit of Embodiment 1 which concerns on this invention. It is a timing chart explaining operation of each part of the gate drive circuit of Embodiment 1. FIG. It is a timing chart which shows the change of the gate voltage of the MOSFET of the output circuit of the current amplifier circuit. It is a timing chart of the output current of the current amplifier circuit and the bypass current of the bypass circuit. It is a circuit diagram which shows the structure of the gate drive circuit of Embodiment 2 which concerns on this invention. It is a timing chart explaining the operation of each part of the gate drive circuit of Embodiment 2. It is a circuit diagram which shows the structure of the gate drive circuit of Embodiment 3 which concerns on this invention. It is a circuit diagram which shows the structure of the gate power source of the gate drive circuit of Embodiment 3 which concerns on this invention. It is a figure which shows the time change of the voltage of each part of a gate power supply.

<Embodiment 1>
FIG. 1 is a circuit diagram of an inverter circuit 1000 that converts a DC voltage into a single-phase high-frequency AC voltage as a power conversion device composed of a power device driven by the gate drive circuit of the first embodiment according to the present invention. is there.

The inverter circuit 1000 includes a semiconductor module 7 composed of MOSFETs, a DC power supply 2 that supplies a DC voltage to the semiconductor module 7, a smoothing capacitor 3 that stabilizes the DC voltage, and four gate drive circuits that drive each MOSFET. A gate power supply 5 connected to each of the gate drive circuits 4 and a control circuit 6 for controlling the four gate drive circuits 4 are provided.

The four switching elements constituting the semiconductor module 7 are large-capacity Nch (second conductive type) MOSFETs having a large rated current and constitute a full-bridge inverter circuit. That is, the MOSFET 101 and the MOSFET 102 are connected in series between the power line P (upper arm) connected to the positive terminal of the DC power supply 2 and the power line N (lower arm) connected to the negative terminal to form one circuit block. A full-bridge inverter circuit is configured by connecting two circuit blocks in parallel. The connection nodes of MOSFETs 101 and 102 of each circuit block serve as output nodes of the semiconductor module 7, and high-frequency AC voltage is output.

The gate power supply 5 includes DC power supplies 51 and 52 insulated from surrounding circuits, and the connection nodes of the negative terminal of the DC power supply 51 and the positive terminal of the DC power supply 52 are grounded (GND), and the positive and negative terminals are positive and negative with reference to the connection node. It is a power supply that changes to. Although each of the DC power supplies 51 and 52 is a single DC power supply, it may be configured by a plurality of DC power supplies.

The control circuit 6 is insulated from the surrounding circuits, and the four gate drive circuits 4 are individually controlled by the isolated switching signals Vs.

The configuration of the gate drive circuit 4 of one of the four gate drive circuits 4 is shown in FIG. In FIG. 2, the MOSFET driven by the gate drive circuit 4 is shown as the MOSFET 100.

As shown in FIG. 2, the gate drive circuit 4 includes a level shift circuit 41 (first level shift circuit), a pre-amplifier circuit 42, and a current amplifier circuit 43, and is a GND (0V) supplied from the gate power supply 5. It operates with a positive power supply voltage + Vdd1 and a negative power supply voltage −Vdd2 with reference to. The control circuit 6 operates with a power supply of 3.3 V or 5.0 V based on the power supply voltage −Vdd2.

The level shift circuit 41 has a configuration in which a resistor Rp1 is connected between the drain terminal of the MOSFET 8 of Nch and GND, and the source terminal of the MOSFET 8 is connected to the power supply terminal T2 to which the power supply voltage −Vdd2 is supplied. .. A switching signal Vs isolated from the control circuit 6 is input to the gate terminal of the MOSFET 8 via a gate resistor 9.

The pre-amplifier circuit 42 is composed of an NPN transistor 10 and a PNP transistor 11 in which emitter terminals and base terminals are connected to each other, and an emitter terminal commonly connected to the NPN transistor 10 and PNP transistor 11 is an output of the pre-amplifier circuit 42. Become a node. The collector terminal of the NPN transistor 10 is connected to the GND, and the collector terminal of the PNP transistor 11 is connected to the power supply terminal T2 to form a push-pull circuit of the emitter follower.

The drain terminal of the MOSFET 8 of the level shift circuit 41 is connected to the base terminal of the NPN transistor 10 and the PNP transistor 11, and the output voltage Vpre of the pre-amplifier circuit 42 changes in the range of the power supply voltage −Vdd2 to GND.

The current amplifier circuit 43 has a Pch (first conductive type) MOSFET 12 (first MOSFET) and an Nch MOSFET 13 (second MOSFET) in which drain terminals are connected to each other. The source terminal of the MOSFET 12 is connected to the power supply terminal T1 (first power supply terminal) to which the power supply voltage + Vdd1 is supplied, and the source terminal of the MOSFET 13 is connected to the power supply terminal T2 (second power supply terminal).

Similar to the MOSFET 100, the gates of the MOSFETs 12 and 13 have an input capacitance Ciss which is the sum of the gate-drain capacitance Cgd and the gate-source capacitance Cgs, but the illustration is omitted.

The gate terminal of the MOSFET 13 is connected to the output node of the pre-amplifier circuit 42 via a gate resistor 18 (second gate resistor) in which a diode 14 (second diode) is connected in parallel. The anode terminal of the diode 14 is connected to the gate terminal of the MOSFET 13, and the cathode terminal is connected to the output node of the preamplifier circuit 42. Further, a resistor Rc and a capacitor Cc are connected in series between the output node of the pre-amplifier circuit 42 and the power supply terminal T1 in order from the power supply terminal T1.

The gate terminal of the MOSFET 12 is connected to a connection node between the resistor Rc and the capacitor Cc via a gate resistor 17 (first gate resistor) in which a diode 15 (first diode) is connected in parallel. The cathode terminal of the diode 15 is connected to the gate terminal of the MOSFET 12, and the anode terminal is connected to the connection node of the resistor Rc and the capacitor Cc.

Further, the diode 16 is connected in parallel to the resistor Rc, the cathode terminal of the diode 16 is connected to the power supply terminal T1, and the anode terminal of the diode 16 is connected to the connection node between the resistor Rc and the capacitor Cc.

The drain terminals of the MOSFET 12 and the MOSFET 13 are connected to the gate terminal of the MOSFET 100 via the gate resistor Rg as an output node of the gate drive circuit 4, and are also connected to the power supply terminal T1 via the bypass resistor Rbyp to form a bypass circuit. ing.

The source terminal of the MOSFET 100 is connected to the GND, and the gate voltage Vg applied to the MOSFET 100 changes in the range of −Vdd2 to + Vdd1 with reference to the GND.

The amplitude voltage of the switching signal Vs from the control circuit 6 is generally 3.3V to 5.0V when the control circuit 6 is composed of an FPGA (Field-Programmable Gate Array) or a microcomputer.

In order to reduce the loss in the ON state (ON), the large-capacity MOSFET 100 needs to be overdriven at a gate voltage Vg sufficiently higher than the gate threshold voltage Vth to reduce the ON resistance. In a general MOSFET, a gate voltage of 12 V to less than 20 V is applied.

Further, when the MOSFET 100 switches a large current, noise is superimposed on the gate voltage Vg, and the MOSFET 100 may malfunction and turn on (erroneous on operation) at the timing when it should be in the off state (OFF). As a countermeasure, by applying a negative bias to the gate voltage Vg with reference to the source terminal of the MOSFET 100, the gate threshold voltage Vth is apparently increased by the amount of the negative bias voltage Vbias. That is, since the MOSFET 100 does not turn on unless the gate voltage Vg exceeds Vth + Vbias, erroneous on operation due to noise can be suppressed.

In the first embodiment, the voltage of the gate power supply 5 is + Vdd1 = + 15V, −Vdd2 = −15V, and the gate voltage Vg changes in the range of −15V to + 15V.

In the level shift circuit 41, the switching signal Vs from the control circuit 6 is changed from an amplitude voltage of 3.3V or 5V based on -15V of -Vdd2 to 15V which changes from -Vdd2 (-15V) to GND (0V). Expanded to the amplitude voltage of.

When the output voltage of the level shift circuit 41 is GND (0V), the output current of the level shift circuit 41 is limited by the resistance Rp1 between the drain terminal of the MOSFET 8 of the level shift circuit 41 and the GND, so that the pre-amplifier circuit The current is amplified at 42.

The output voltage Vpre of the pre-amplifier circuit 42 also changes in the range of −Vdd2 (-15V) to GND (0V) with reference to −Vdd2 (-15V) like the output of the level shift circuit 41, and the amplitude is 15V. ..

The gate voltage Vgop-g of the MOSFET 12 of the current amplification circuit 43 after passing through the capacitor Cc from the output of the pre-amplifier circuit 42 is the power supply voltage + Vdd1, that is, + Vdd1 (+ 15V) to GND (0V) based on the potential of the source terminal of the MOSFET 12. ) Varies. Further, the gate voltage Vpre-g of the MOSFET 13 of the current amplification circuit 43 after passing through the gate resistor 18 from the output of the pre-amplifier circuit 42 is the power supply voltage −Vdd2, that is, −Vdd2 (−Vdd2 (-) based on the potential of the drain terminal of the MOSFET 13. It varies in the range of 15V) to GND (0V).

Therefore, in the gate drive circuit 4 according to the first embodiment, even when the gate voltage Vg, which is the output voltage of the gate drive circuit 4, fluctuates positively or negatively and the amplitude exceeds 20 V, the MOSFET 12 of the current amplifier circuit 43 is subjected to the gate withstand voltage. It can be driven by the following gate voltage Vgop-g, and the MOSFET 13 can be driven by a gate voltage Vpre-g equal to or less than the gate withstand voltage.

FIG. 3 is a timing chart illustrating the operation of each part of the gate drive circuit 4 of the first embodiment. In FIG. 3, the horizontal axis is time [s] and the vertical axis is voltage [V], the gate voltage Vgop-g of the MOSFET 12 of the current amplification circuit 43, the output voltage Vpre of the pre-amplification circuit 42, and the current amplification circuit 43. The time change of the differential voltage Vc across the capacitor Cc and the gate voltage Vg from the gate drive circuit 4 is shown. The gate threshold voltage of the MOSFET 12 is −Vthp.

As an initial state, in the period A of FIG. 3, the switching signal Vs from the control circuit 6 is "High", the gate voltage Vg which is the output voltage of the gate drive circuit 4 is + 15V, and the difference between both ends of the capacitor Cc. It is assumed that the dynamic voltage Vc is 15 V and is charged.

In this period A, the NPN transistor 10 of the pre-amplification circuit 42 is off, the PNP transistor 11 is on, and the output voltage Vpre of the pre-amplification circuit 42 is the power supply voltage −Vdd2 (-15V). .. Therefore, the MOSFET 12 of the current amplifier circuit 43 is turned on, and the MOSFET 13 is turned off.

The capacitor Cc of the current amplifier circuit 43 is in the path of the power supply terminal T1 that supplies the power supply voltage + Vdd1 (+ 15V), the resistor Rc, the capacitor Cc, the PNP transistor 11, and the power supply terminal T2 that supplies the power supply voltage −Vdd2 (-15V). It is charged with the constant τ = Rc × Cc. In this formula, the resistance value of the resistor Rc is represented by Rc, and the capacitance of the capacitor Cc is represented by Cc.

In period A, the differential voltage Vc across the capacitor Cc and the gate voltage Vgop-g of the MOSFET 12 are equal, and the gate voltage Vgop-g of the MOSFET 12 is GND (when the power supply voltage −Vdd2 (-15V) is used as the reference potential. The voltage rises from 0V) with a time constant τ.

Before the gate voltage Vgop-g of the MOSFET 12 exceeds the power supply voltage + Vdd1 (+ 15V) -Vthp at which the MOSFET 12 of the current amplification circuit 43 is turned off, the switching signal Vs from the control circuit 6 changes to "Low" and shifts to the period B. To do.

Next, in the period B of FIG. 3, the NPN transistor 10 of the pre-amplifier circuit 42 is turned on, the PNP transistor 11 is turned off, and the output voltage Vpre of the pre-amplifier circuit 42 is changed from the power supply voltage −Vdd2 (-15V) to GND (0V). ).

Since the output voltage Vpre of the pre-amplifier circuit 42 changes from the power supply voltage −Vdd2 (−15V) to GND (0V), the capacitor Cc is biased at + 15V. Since the power supply voltage + Vdd1 (+ 15V) is exceeded by the differential voltage ΔVc charged in the period A, the battery is discharged via the diode 16 and the differential voltage Vc becomes + 15V.

The gate voltage Vgop-g of the MOSFET 12 of the current amplifier circuit 43 becomes 0V with reference to the power supply voltage + Vdd1 (+ 15V) of the power supply terminal T1 to which the source terminal is connected, and the MOSFET 12 is turned off. Further, since the output voltage Vpre of the pre-amplifier circuit 42 changes from the power supply voltage −Vdd2 (-15V) to GND (0V), the power supply terminal T2 to which the source terminal is connected to the gate terminal of the MOSFET 13 of the current amplification circuit 43. 15V is applied based on the power supply voltage −Vdd2 (-15V) of the above, the MOSFET 13 is turned on, and the gate voltage Vg, which is the output voltage of the gate drive circuit 4, changes from + 15V to −15V.

Next, the switching signal Vs from the control circuit 6 changes to "High", the period A is set again, and the period A and the period B are alternately repeated, so that the gate voltage Vg, which is the output voltage of the gate drive circuit 4, becomes ±. It varies in the range of 15V.

FIG. 4 is a timing chart showing changes in the gate voltages of the MOSFETs 12 and 13 of the current amplifier circuit 43. In FIG. 4, the horizontal axis is time [s] and the vertical axis is voltage [V], the changes in the gate voltage Vgop-g of the MOSFET 12 and the gate voltage Vpre-g of the MOSFET 12, and the gate threshold voltage Vthp of the MOSFET 12 and the MOSFET 13 The relationship with the gate threshold voltage Vthn of is shown in detail.

As shown in FIG. 4, when the gate voltage Vpre-g and the gate voltage Vgop-g change with the rise time tr and the rise time tf, respectively, the time at which the gate voltage Vpre-g intersects with the gate threshold voltage Vthn at the time of rise is calculated. Assuming that the time at which the gate threshold voltage Vthn intersects with the gate threshold voltage Vthn at the fall of the gate voltage Vpre-g is set to tn-off, the MOSFET 13 is turned on during the period from tun-on to tn-off.

Further, assuming that the time at which the gate voltage Vgop-g intersects with the gate threshold voltage Vthp at the rising edge is tp-off and the time at which the gate voltage Vgop-g intersects with the gate threshold voltage Vthp is tp-on. During the period of ~ tp-off, the MOSFET 12 is off.

As shown in FIG. 4, the rise of the gate voltage Vgop−g is fast and the fall is slow. The reason for this is that the voltage is applied via the diode 15 at the rising edge of the gate voltage Vgop-g, and is discharged via the gate resistor 17 at the falling edge.

That is, in order to turn on / off the MOSFET 12 of the current amplifier circuit 43, it is necessary to charge / discharge the input capacitance Ciss of the MOSFET 12, and since the input capacitance Ciss is charged via the diode 15 at the time of rising, it can be charged rapidly and rises. Becomes faster. On the other hand, at the time of falling, the electric charge accumulated in the input capacitance Ciss is discharged via the gate resistor 17, so that the falling is delayed.

Further, as shown in FIG. 4, the rise of the gate voltage Vpre-g is slow and the fall is fast. The reason for this is that the voltage is applied through the gate resistor 18 at the rising edge of the gate voltage Vpre-g, and discharged via the diode 14 at the falling edge.

That is, in order to turn on / off the MOSFET 13 of the current amplifier circuit 43, it is necessary to charge / discharge the input capacitance Ciss of the MOSFET 13, and at the time of rising, the input capacitance Ciss is charged via the gate resistor 18, so the rising is delayed. On the other hand, at the time of falling, the electric charge accumulated in the input capacitance Ciss is discharged via the diode 14, so that the falling becomes faster.

In this way, since there is a difference between the rising and falling edges of the gate voltage Vgop-g and the rising and falling edges of the gate voltage Vpre-g, there is a period in which both the MOSFET 12 and the MOSFET 13 are off, which is the dead time. It becomes. In FIG. 4, the dead time tdead is between tp-off and tp-on, and the dead time tdead is between tn-off and tp-on. By ensuring the dead time, it is possible to prevent both the MOSFET 12 and the MOSFET 13 from being turned on at the same time and causing an arm short circuit. The length of the dead time tdead can be adjusted by changing the resistance values Rgp and Rgn of the gate resistors 17 and 18, respectively.

As described above, according to the gate drive circuit 4 of the first embodiment, the dead time of the MOSFET 12 and the MOSFET 13 of the output circuit of the current amplifier circuit 43 can be secured, so that the arm short circuit can be prevented and the short circuit current generated at the time of the arm short circuit can be suppressed. It is not necessary to provide a current limiting resistor for this purpose between the power line P (upper arm) and the power line N (lower arm). Therefore, the gate resistance of the large-capacity MOSFET 100 does not increase, and the MOSFET 100 can be driven at high speed.

Further, according to the gate drive circuit 4 of the first embodiment, since the input capacitance Ciss of the MOSFET 100 can be rapidly charged and discharged by using the MOSFET 12 and the MOSFET 13 of the current amplifier circuit 43, the MOSFET 100 can be switched at a high frequency of several hundred kHz. Moreover, it has a feature that the MOSFET 100 can be kept on even at a low switching frequency.

Hereinafter, this feature will be described with reference to FIG. FIG. 5 is a timing chart of the output current Ichr of the current amplifier circuit 43 of the gate drive circuit 4 and the current Ibyp flowing through the bypass resistor Rbyp of the bypass circuit.

In FIG. 5, the current value in the direction of flowing from the current amplification circuit 43 of the gate drive circuit 4 into the input capacitance Ciss of the MOSFET 100 is + Ion, and the current value in the direction of being drawn from the input capacitance Ciss into the current amplification circuit 43 of the gate drive circuit 4 is set. When −Ioff is set, + Ion and −Ioff flow only for a short time when the gate voltage Vg, which is the output voltage of the gate drive circuit 4, rises and falls, and the input capacitance Ciss is rapidly charged and discharged. Since it is sufficient that the bypass current Ibyp flows through the bypass resistor Rbyp as much as necessary for the MOSFET 100 to keep on, the resistance value of the bypass resistor Rbyp can be increased and the loss can be suppressed.

Here, in the timing chart of FIG. 3, the power supply voltage + Vdd1 (+ 15V) is supplied during the period A in which the MOSFET 12 of the current amplification circuit 43 is on, that is, the period in which the PNP transistor 11 of the pre-amplification circuit 42 is on. In the path of the power supply terminal T1, the resistor Rc, the capacitor Cc, the PNP transistor 11, and the power supply terminal T2 for supplying the power supply voltage −Vdd2 (-15V), both ends of the capacitor Cc are from GND (0V), and the time constant τ = Rc × It is charged with Cc.

Assuming that the gate threshold voltage of the MOSFET 12 of the current amplifier circuit 43 is -Vthp, the gate voltage Vgop-g of the MOSFET 12 is the source until the voltage across the capacitor Cc, that is, Vgop-g exceeds the power supply voltage + Vdd1 (+ 15V) -Vthp. When the power supply voltage of the terminal + Vdd1 (+ 15V) is used as a reference, it falls below the gate threshold voltage −Vthp, so that it can be maintained on. On the other hand, when the switching frequency of the MOSFET 100 falls below the time constant τ (Rc × Cc), that is, when the switching frequency becomes low, the voltage across the capacitor Cc exceeds + Vdd1 (+ 15V) −Vthp, and the MOSFET 12 turns off.

In the gate drive circuit 4 of the first embodiment, by providing the bypass resistor Rbyp as a bypass circuit, even after the input capacitance Ciss of the MOSFET 100 is rapidly charged by the MOSFET 12 of the current amplification circuit 43, it is bypassed via the bypass resistor Rbyp. Since the input capacitance Ciss can be continuously charged by the current Ibyp, the MOSFET 100 can be kept on.

Then, the time constant τ (Rc × Cc) is set to be larger than the switching frequency of the MOSFET 100, Rhyp × Ciss is set to be equal to or less than the switching frequency of the MOSFET 100 and the time constant τ (Rc × Cc), and Rc × Cc ≧ Rbyp. The bypass resistor Rbyp is set so as to satisfy the condition of × Ciss. As a result, the input capacitance Ciss can be charged with the bypass current Ibyp, and the MOSFET 100 can be kept on even at a low switching frequency below the time constant τ due to the resistor Rc and the capacitor Cc.

In the first embodiment, the drive target of the gate drive circuit 4 is a large-capacity MOSFET built in the semiconductor module 7, but the drive target is a discrete transistor instead of being built in the semiconductor module. But the same effect can be obtained. Needless to say, the same effect can be obtained by applying the gate drive circuit 4 of the first embodiment to the drive of the IGBT as well as the MOSFET.

<Embodiment 2>
FIG. 6 is a diagram showing the configuration of the gate drive circuit 40 of the second embodiment according to the present invention, and the same configuration as that of the gate drive circuit 4 described with reference to FIG. 2 is designated by the same reference numerals and overlaps. The description is omitted.

As shown in FIG. 6, the gate drive circuit 40 includes a level shift circuit 411 (first level shift circuit), a level shift circuit 412 (second level shift circuit), a pre-amplifier circuit 42, a current amplifier circuit 43, and a bypass. It is composed of a circuit 44, and operates with a positive and negative power supply voltage + Vdd1 and a power supply voltage −Vdd2 based on GND (0V) supplied from the gate power supply 5.

The level shift circuit 411 has a configuration in which a resistor Rp1 is connected between the drain terminal of the MOSFET 8 of the Nch and the GND, and the source terminal of the MOSFET 8 is connected to the power supply terminal T2 to which the power supply voltage −Vdd2 is supplied. .. A switching signal Vs isolated from the control circuit 6 is input to the gate terminal via a gate resistor 9.

The level shift circuit 412 has resistors Rp2, Rp3, and Nch MOSFET19 connected in series between the power supply terminal T1 to which the power supply voltage + Vdd1 is supplied and the power supply terminal T2 to which the power supply voltage −Vdd2 is supplied. The source terminal of the MOSFET 19 is connected to the power supply terminal T2, the drain terminal is connected to the resistor Rp3, and the connection node between the resistor Rp2 and the resistor Rp3 is the base terminal of the PNP transistor Tbyp of the bypass circuit 44 as the output node of the level shift circuit 412. It is connected to the. A switching signal Vs isolated from the control circuit 6 is input to the gate terminal of the MOSFET 19 via a gate resistor 91.

In the bypass circuit 44, the emitter terminal of the PNP transistor Tbyp that functions as a bypass transistor is connected to the power supply terminal T1, and the collector terminal is connected to the output of the gate drive circuit 40. A bypass signal whose polarity is inverted from the switching signal Vs output by the control circuit 6 is input from the level shift circuit 412 to the base terminal (control terminal) of the PNP transistor Tbyp.

FIG. 7 is a timing chart illustrating the operation of each part of the gate drive circuit 40 of the second embodiment. In FIG. 7, the horizontal axis is time [s], the vertical axis is voltage [V], and the switching signal Vs output from the control circuit 6, the output voltage Vpre of the preamplifier circuit 42, and the output voltage of the gate drive circuit 40. It shows the on / off time change of a certain gate voltage Vg and PNP transistor Tbyp.

As shown in FIG. 7, the polarity of the output voltage Vpre of the pre-amplifier circuit 42 after passing through the level shift circuit 411 is inverted with respect to the switching signal Vs. Further, the PNP transistor Tbyp of the bypass circuit 44 controlled by the bypass signal is turned on and off in synchronization with the gate voltage Vg.

As described above, in the gate drive circuit 40 of the second embodiment, the PNP transistor Tbyp of the bypass circuit 44 turns on and off in synchronization with the gate voltage Vg. Therefore, when the gate voltage Vg is off, the PNP transistor Tbyp is used. Since no current flows, it has the advantages of lower loss and higher efficiency than the gate drive circuit 4 of the first embodiment in which the bypass resistor Rbyp is used as the bypass circuit.

In addition, it goes without saying that the same effect as that of the gate drive circuit 4 of the first embodiment can be obtained with respect to the same configuration as the gate drive circuit 4 of the first embodiment.

Although the configuration in which the PNP transistor Tbyp is used as the bypass transistor is shown in the second embodiment described above, the bypass transistor is not limited to the bipolar transistor and may be configured by the MOSFET.

<Embodiment 3>
FIG. 8 is a diagram showing the configuration of the gate drive circuit 4A of the third embodiment according to the present invention, and the same configuration as that of the gate drive circuit 4 described with reference to FIG. 2 is designated by the same reference numerals and overlaps. The description is omitted.

In the inverter circuit 1000 shown in FIG. 1, the gate power supply 5 is connected to the gate drive circuit 4, but the gate drive circuit 4A shown in FIG. 8 has a built-in gate power supply 5A.

As shown in FIG. 8, the gate power supply 5A built in the gate drive circuit 4A supplies the power supply voltage + Vdd1 (+ 15V) and the power supply voltage −Vdd2 (-15V) to the gate drive circuit 4A, and supplies the power supply voltage − to the control circuit 6. Vdd2 (-15V) is supplied. Further, the power supply voltage −Vcc (−10V) is supplied to the control circuit 6.

FIG. 9 is a circuit diagram showing the configuration of the gate power supply 5A. As shown in FIG. 9, the gate power supply 5A is a DC power supply 20 (first power supply) and a DC power supply having an output voltage of 15 V between the pins P1 and P2 of the connector CN1 and between the pins P2 and P3, respectively. 21 (second power supply) is connected. Then, in order to stabilize the voltages of the DC power supplies 20 and 21, smoothing capacitors C1 and C2 are connected between the pins P1 and P2 and between the pins P2 and P3, respectively. The DC power supplies 20 and 21 are isolated from the surrounding circuits.

The voltage detection resistors 22 and 23 connected in series are connected in parallel to the smoothing capacitor C1, and the connection nodes of the voltage detection resistors 22 and 23 are connected to the control terminals of the switch 25. Further, between the connection nodes of the voltage detection resistors 22 and 23 and the pin P2 of the connector CN1, a capacitor 24 that functions as a time-determining capacitor that defines the time when the switch 25 is turned on is provided.

The switch 25 is turned on when the capacitor 24 is charged via the voltage detection resistor 22 and the voltage across the capacitor 24 exceeds the specified voltage specified by the voltage detection resistors 22 and 23, and the voltage across the smoothing capacitor C1 + Vin is supplied. It is supplied as a voltage + Vdd1 (+ 15V) to the power supply terminal T1 of the gate drive circuit 4A.

Further, the voltage across the smoothing capacitor C2 is supplied to the power supply terminal T2 of the gate drive circuit 4A as a power supply voltage −Vdd2 (-15V).

The input terminal of the 3-terminal regulator 26 is connected to the pin P3 of the connector CN1, and the 3-terminal regulator 26 generates the power supply voltage −Vcc (-10V) with reference to the power supply voltage −Vdd2 (-15V), and the control circuit 6 It is supplied to the power supply terminal T3 of. The common terminal of the 3-terminal regulator 26 is connected to the pin P2 of the connector CN1, and a smoothing capacitor 27 is connected between the pin P2 and the output terminal of the 3-terminal regulator 26. The voltage difference between the power supply voltage −Vdd2 (-15V) and the power supply voltage −Vcc (−10V) is + 5V, and the power supply is supplied and used as the power supply for the transistor of the control circuit 6.

FIG. 10 is a diagram showing the time change of the voltage of each part of the gate power supply 5A when the DC power supplies 20 and 21 are turned on. As shown in FIG. 10, the voltage of the power supply voltage + Vin and the power supply voltage −Vdd2 rises and falls at the same timing and with the same slope, respectively.

The power supply voltage −Vcc and the power supply voltage −Vdd2 output by the 3-terminal regulator 26 also decrease with the same slope, and the power supply voltage −Vcc becomes constant when it reaches −10V.

The capacitor 24 is charged via the voltage detection resistor 22, and when it reaches a specified voltage t1 second after the start of charging, the switch 25 is turned on to supply the power supply voltage + Vdd1 to the gate drive circuit 4A. In FIG. 10, the power supply voltage + Vdd1 is shown by a broken line.

As described above, in the gate power supply 5A, the power supply voltage + Vdd1 is not supplied to the gate drive circuit 4A until the switch 25 is turned on 1 second after the start of charging of the capacitor 24. Here, the time t1 second is set based on the time when the MOSFET 13 of the current amplifier circuit 43 of the gate drive circuit 4A is surely turned on.

In the gate drive circuit 4A of the third embodiment, the power supply voltage −Vdd2 (-15V) of the gate power supply 5A and the voltage of the power supply voltage −Vcc (-10V) are stable, and the MOSFET 13 of the current amplification circuit 43 is turned on. Later, after t1 second, the switch 25 is turned on and the power supply voltage + Vdd1 (+ 15V) is supplied. Therefore, when the gate power supply is started, the power supply voltage + Vdd1 becomes the gate voltage through the bypass resistor Rbyp during the period when Vpre-g becomes transiently "Low" due to the operation delay of the PNP transistor 11 of the preamplifier circuit 42. It is supplied as Vg and can prevent the MOSFET 100 from being erroneously turned on and short-circuiting the arm.

In addition, it goes without saying that the same effect as that of the gate drive circuit 4 of the first embodiment can be obtained with respect to the same configuration as the gate drive circuit 4 of the first embodiment.

In the present invention, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the invention.

4,4A, 40 gate drive circuit, 5,5A gate power supply, 6 control circuit, 7 semiconductor module, 41,411,412 level shift circuit, 42 pre-amplification circuit, 43 current amplification circuit.

Claims (6)

A gate drive circuit that drives the gate of a transistor based on a switching signal input from a control circuit.
A first level shift circuit that expands the amplitude voltage of the switching signal, and
A pre-amplifier circuit that amplifies the output current of the first level shift circuit and
A current amplifier circuit that amplifies the output current of the pre-amplifier circuit is provided.
The current amplifier circuit
It has a first conductive type first MOSFET and a second conductive type second MOSFET connected in series.
The source terminal of the first MOSFET is connected to the first power supply terminal that gives a positive power supply voltage.
The source terminal of the second MOSFET is connected to a second power supply terminal that gives a negative power supply voltage.
The drain terminal of the first MOSFET and the drain terminal of the second MOSFET are connected to the gate terminal of the transistor as an output node of the gate drive circuit.
The gate terminal of the first MOSFET is
It is connected to the output node of the pre-amplifier circuit via a capacitor, and is connected to the first power supply terminal via a resistor.
The gate terminal of the second MOSFET is
Connected to the output node of the pre-amplifier circuit,
The output node of the gate drive circuit
A gate drive circuit connected to the first power supply terminal via a bypass circuit. The gate terminal of the first MOSFET is
A first diode is connected to the capacitor and the resistor via a first gate resistor connected in parallel.
The gate terminal of the second MOSFET is
A second diode is connected to the output node of the pre-amplifier circuit via a second gate resistor connected in parallel.
The first diode is
The cathode is connected to the gate terminal of the first MOSFET,
The second diode is
The gate drive circuit according to claim 1, wherein the anode is connected to the gate terminal of the second MOSFET. The bypass circuit
The gate drive circuit according to claim 1 or 2, further comprising a bypass resistor connected between the output node of the gate drive circuit and the first power supply terminal. A second level shift circuit that inverts the polarity of the switching signal and widens the amplitude voltage is further provided.
The bypass circuit
It has a bypass transistor connected between the output node of the gate drive circuit and the first power supply terminal.
The control terminal of the bypass transistor is
The gate drive circuit according to claim 1 or 2, which is connected to the output node of the second level shift circuit. Further equipped with a gate power supply that supplies the positive power supply voltage and the negative power supply voltage,
The gate power supply
The gate drive circuit according to any one of claims 1 to 3, wherein the supply of the positive power supply voltage is started after the negative power supply voltage is stable and the second MOSFET is turned on. The gate power supply
The first power supply that supplies the positive power supply voltage and
The second power supply that supplies the negative power supply voltage and
A plurality of voltage detection resistors connected in parallel to the first power supply,
A time-defined capacitor connected in parallel with any of the plurality of voltage detection resistors,
It has a switch that is connected to the time-specified capacitor and turns on when the time-specified capacitor is charged and the voltage across it reaches the specified voltage.
The switch
Connected in series between the positive terminal of the first power supply and the first power supply terminal,
The start of supply of the positive power supply voltage is
The gate drive circuit according to claim 5, wherein the voltage across the time-defined capacitor is defined by the time it takes to reach the specified voltage.

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