CN105577150A - Pulse Width Regulator - Google Patents

Abstract

The invention provides a pulse wave width regulating device, apply to a N port random access memory, N is greater than or equal to 2, have complex groups of character lines in the random access memory of said N port, at least one group of character lines include N port character lines in the said complex group of character lines, the said pulse wave width regulating device includes: a state detection device, for correspondingly sending out a first control signal when the voltage value of the first port character online and the voltage value of the second port character online are both located in a first level range; and a clock signal generator electrically connected to the state detector and the group of word lines for generating a first clock signal to the group of word lines, wherein a time length of the first clock signal in the first level range is changed in response to the first control signal. The invention can avoid the excessive consumption of the power supply and also can reduce the risk of the inversion or the loss of the stored data of the component caused by the overlong starting time of the character line.

Description

Pulse Width Regulator

technical field

The invention relates to a pulse width adjusting device, in particular to a pulse width adjusting device applicable to a multi-port random access memory.

Background technique

Please refer to Figure 1, which is a circuit schematic diagram of a common dual-port (dual-port/2-port) static random access memory (StaticRAM, referred to as SRAM) unit, between it and a single-port static random access memory The difference is that in addition to the latch unit 10 composed of four transistors and the first group of switch circuits 11 in the dual-port SRAM, a second group of switch circuits 12 is additionally provided, so that The read-write circuit (not shown in this figure) around the memory can simultaneously use the first port word line WLA and the second port word line WLB to respectively lock the latch unit 10 and other latch units on the same column ( not shown in this figure) to read or write data.

In order to provide the margin (margin) required to simultaneously read or write different latch units on the same column, the traditional read-write circuit must provide sufficient wordline pulse width (wordline pulsewidth), that is, in Selected characters maintain a high voltage on the line long enough to ensure that data reads and data writes can still be completed correctly when the worst case occurs. However, in this way, the following defects will occur. First, it will cause excessive power consumption; second, the time for turning on the word line for too long will increase the risk that external disturbances will affect the correctness of the stored data.

Contents of the invention

The technical problem to be solved by the present invention is to provide a pulse width adjusting device which saves electric energy and improves the accuracy and safety of stored data.

In order to solve the above-mentioned technical problems, the present invention provides a pulse width adjustment device, which is applied to an N-port random access memory, where N is greater than or equal to 2, and the N-port random access memory has complex word lines, and the At least one group of word lines in the complex group of word lines includes N port word lines, and the pulse width adjustment device includes:

A state detecting device, used for correspondingly sending out a first control signal in response to the voltage value of the character line of the first port and the voltage value of the character line of the second port being in a first level range; and

A clock signal generator, electrically connected to the state detection device and the group of word lines, for generating a first clock signal sent to the group of word lines, the first clock signal is located in the group of word lines The time length of the first level range is changed according to the first control signal.

Wherein, the N-port random access memory is an N-port static random access memory, wherein each group of word lines includes N-port word lines.

Wherein, the state detection device includes a logic circuit device electrically connected to the word line of the first port and the word line of the second port for responding to the word line of the first port and the word line of the second port. When the voltage values of the word lines are all in the first level range, the first control signal is sent to the clock signal generator, and between the first port word line and the second port word line When the voltage values are not all within the first level range, a second control signal is sent to the clock signal generator.

Wherein, the logic circuit device is an AND gate, the input end of which is electrically connected to the word line of the first port and the word line of the second port, and the output end of which outputs the control signal to the clock signal generator.

Wherein, the state detection device includes:

An adjustable electrical load, the adjustable electrical load is electrically connected to the word line of the first port and the word line of the second port, and is used for corresponding to the voltage value of the word line of the first port and the word line of the first port When the voltage values of the character lines of the second port are all in the first level range, adjusting from a first load value to a second load value; and

A control signal generator, electrically connected to the adjustable electrical load, for correspondingly generating the control signal in response to the second load value.

Wherein, the adjustable electrical load includes:

a first load wire electrically connected to the control signal generator;

a second load lead; and

a controlled switching device, electrically connected to the first port word line, the second port word line, the first load wire and the second load wire, for responding to the first port word line When the voltage value of the character line of the second port is within the first level range, the first load wire is electrically connected to the second load wire, so that the adjustable electrical load is controlled by the The first load value is adjusted to the second load value; on the contrary, when the voltage values of the word line of the first port and the word line of the second port are not both in the first level range, the An open circuit is maintained between the first load wire and the second load wire, thereby maintaining the adjustable electrical load at the first load value.

Wherein, the load value of the first load wire or the second load wire is substantially equal to the equivalent load value of a bit line in the N-port random access memory.

Wherein, the controlled switch device includes:

a first metal-oxide-semiconductor transistor, the gate of which is electrically connected to the first port word line, and the source of which is electrically connected to the first load wire; and

A second metal oxide semitransistor, its gate is electrically connected to the word line of the second port, its source is electrically connected to the second load wire, and its drain is electrically connected to the first metal oxide The drain of the half transistor.

Wherein, the control signal generator includes:

A controlled discharge path, electrically connected to the adjustable electrical load, used to provide the adjustable electrical load to perform a discharge action in a specific time, so that the voltage on the adjustable electrical load decrease in value; and

A voltage trigger unit, electrically connected to the adjustable electrical load, is used for sending out the control signal when the voltage on the adjustable electrical load drops to a threshold value.

Wherein, the controlled discharge path includes a third metal-oxide-semiconductor transistor, the gate of which is electrically connected to a second clock signal, the drain of which is electrically connected to the first load wire, and the source of which is electrically Connect to a ground point.

Wherein, the voltage trigger unit is a NOT gate, the input end of which is connected to the first load wire in series, and the output end is used to output the control signal.

Wherein, the state in which the first clock signal generated by the clock signal generator and sent to the group of word lines is in the first level range is switched to a first level range in response to the triggering of the control signal Secondary range.

Wherein, the control signal sent by the state detection device is transmitted to a bit line data sensing device, and the bit line data sensing device is electrically connected between the state detection device and the N-port random A set of bit lines in the memory is accessed, and the bit line data sensing device is used to be enabled in response to the triggering of the control signal.

The present invention also provides a pulse width adjustment device, which is applied in a static random access memory, the static random access memory has a plurality of groups of word lines, and at least one group of word lines in the plurality of groups of word lines includes at least There is a first port word line and a second port word line, and the pulse width adjustment device includes:

A state detection device, used for correspondingly performing the corresponding operation according to a first load value in response to the voltage value of the character line of the first port and the voltage value of the character line of the second port being in a first level range Discharging is adjusted to discharge according to a second load value; and

A clock signal generator, used to generate a first clock signal sent to the group of word lines, the time length of the first clock signal in the first level range is at least according to the first load value or the discharge time of one of the second load value.

Wherein, when the voltage of a first load wire of the state detection device discharges to a threshold value, a control signal is sent to the clock signal generator to determine that the first clock signal is in the The time length of the first level range.

Implementing the embodiment of the present invention will bring the following beneficial effects: through the state detection device, the voltage value of the character line of the port is all in the first level range to send the first control signal, and the clock signal generator generates the voltage value sent to the character line. The first clock signal, and the length of time during which the first clock signal is in the first level range changes with the first control signal, so that excessive power consumption can be avoided, and the problem caused by too long turn-on time of the word line can also be reduced. The risk of data reversal or loss due to external environmental interference caused by component storage data.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic circuit diagram of an existing dual-port SRAM.

FIG. 2A is a circuit block diagram of a preferred embodiment of a pulse width adjusting device according to the present invention.

FIG. 2B is a circuit block diagram of a preferred embodiment of the state detection device in the present invention.

FIG. 2C is a schematic circuit block diagram of an embodiment of the controlled switch device in the present invention.

FIG. 2D is a circuit block diagram of an embodiment of the control signal generator in the present invention.

Fig. 3 is a schematic diagram of a waveform of an embodiment of the pulse width adjusting device of the present invention when it is working.

FIG. 4 is a schematic diagram of another embodiment of an adjustable electrical load in the present invention.

FIG. 5 is a circuit block diagram of another preferred embodiment of a pulse width adjusting device according to the present invention.

A brief description of the reference numbers:

Latch unit 10; first group of switch circuits 11; second group of switch circuits 12; first port word line WLA; second port word line WLB; bit lines BLA, BLB; static random access memory unit Un[N], …, U0[N], …, Un[0]…, U0[0]; first port word lines WLA[N], …, WLA[0]; second port word lines WLB[N], …, WLB [0]; state detection device 20; clock signal generator 21; adjustable electrical load 201; control signal generator 202; first load wire 2011; second load wire 2012; controlled switching device 2013; Metal-oxide-semiconductor transistor 20131; second metal-oxide-semiconductor transistor 20132; controlled discharge path 2021; voltage trigger unit 2022; bit line data sensing device 29; system clock CLK; first load wire RBLA; second load wire RBLA' The controlled switching device 41; the third load wire RBLB; the fourth load wire RBLB'; the controlled switching device 42; the first metal oxide semitransistor MA; the second metal oxide semitransistor MB; Device 500 ; clock signal generator 51 .

detailed description

Some typical embodiments embodying the features and advantages of the present invention will be described in detail in the description in the following paragraphs. It should be understood that the invention is capable of various changes in different aspects without departing from the scope of the invention, and that the description and illustrations therein are illustrative in nature and not limiting. this invention.

Please refer to FIG. 2A , which is a schematic circuit block diagram of a preferred embodiment of a pulse width adjustment device developed by the present invention. This embodiment uses static random access memory as an example for illustration, but this embodiment In fact, it can be widely applied to N-port SRAM or other similar N-port memory units, but not limited thereto, where N greater than or equal to 2 can be applicable. As shown in the figure, this embodiment is described with a dual-port static random access memory. The dual-port static random access memory has a plurality of static random access memory units U _n [N], ..., U ₀ [N], ..., U _n [0] ..., U ₀ [0] and complex group characters Line (wordline), each group of word lines contains the first port word line and the second port word line, such as WLA[N], WLB[N] shown in the figure, or WLA[0], WLB[0 ].

The pulse width adjustment device developed by the present invention mainly includes a state detection device 20 and a clock signal generator 21. The state detection device 20 is electrically connected to the first port word lines WLA[N], ..., WLA[0] and the second port word lines WLB[N], ..., WLB[0], which can mainly respond to the voltage values of the first port word line and the second port word line in the same word line group are all in the first level range and correspondingly send a first control signal; otherwise, when the voltage values of the first port word line and the second port word line of the same word line group are not all in the first level range, A second control signal is correspondingly sent out. As for the clock signal generator 21 electrically connected to the state detection device 20, it is used to generate the clock signal sent to the groups of word lines, and the clock signal is in the time of the first level voltage value range The length can be changed according to the control signals. For example, when the pulse width of the word line clock signal depends on whether the voltage values of the word line of the first port and the word line of the second port of the same word line group are all in the first standard bit range varies.

Please refer to FIG. 2B , which is a schematic circuit block diagram of a preferred embodiment of the above-mentioned state detection device 20. The state detection device 20 mainly includes an adjustable electrical load 201 and a control signal generator 202. The adjustable electrical load 201 Electrically connected to the word lines WLA[N], ..., WLA[0] of the first port and the word lines WLB[N], ..., WLB[0] of the second port, which can mainly respond to the same word line group When the voltage values of the first port word line and the second port word line in the same word line group are both in the first level range, the first load value is adjusted to the second load value; otherwise, when the first port word line of the same word line group When the voltage values on the character line of the second port are not all within the first level range, the adjustable electrical load 201 is maintained at the first load value. Taking the figure as an example, the adjustable electrical load 201 includes a first load wire 2011, a second load wire 2012 and a controlled switching device 2013, and the controlled switching device 2013 is electrically connected to the first port word line WLA [N],..., WLA[0], the second port word lines WLB[N],..., WLB[0], the first load wire 2011 and the second load wire 2012, the controlled switching device 2013 is When the voltage values of the first port word line and the second port word line in the same word line group are both in the first level range, the first load wire 2011 is electrically connected to the second load wire 2012 , so that the adjustable electrical load 201 is adjusted from the first load value with a smaller value to the second load value with a larger value, otherwise, the first port word line and the second port word line in the same word line group When the voltage values of the port word lines are not all in the first level range, keep the open circuit between the first load wire 2011 and the second load wire 2012, so as to keep the adjustable electrical load 201 at a smaller value The first load value. The load value of the above-mentioned first load wire 2011 and the second load wire 2012 is close to the equivalent load value of a bit line (bitline) in the random access memory, wherein the load value can be a capacitance value, a resistance value or both The combination. Preferably, the first load wire 2011 and the second load wire 2012 can be arranged in parallel with the bit line in the random access memory, and their length or width is similar to or proportional to the length or width of the bit line, thereby Simulate equivalent load values.

The above-mentioned embodiment of the controlled switching device 2013 can be shown in FIG. 2C , which is composed of a first metal oxide semitransistor 20131 and a second metal oxide semitransistor 20132 connected in series. The first metal oxide semitransistor The gate of 20131 is electrically connected to the first port word line WLA, its source is electrically connected to the first load wire 2011, and the gate of the second metal oxide semiconductor transistor 20132 is electrically connected to the second port character The source of the line WLB is electrically connected to the second load wire 2012 , and the drain is electrically connected to the drain of the first metal oxide semiconductor transistor 20131 .

As for the control signal generator 202 electrically connected to the adjustable electrical load 201, it can generate a first control signal corresponding to the appearance of the first load value or generate a second control signal corresponding to the appearance of the second load value. Two control signals are given to the clock signal generator 21, so that the time length of the clock signal generated by the clock signal generator 21 in the first level voltage value range is due to the change of the load value of the adjustable electrical load 201 And change. As shown in FIG. 2D as an example, the control signal generator 202 may include a controlled discharge path 2021 and a voltage trigger unit 2022, and the controlled discharge path 2021 is electrically connected to the first load of the adjustable electrical load 201 The wire 2011 and the controlled discharge path 2021 provide the adjustable electrical load 201 to perform a discharge action during a specific time, so that the voltage value on the adjustable electrical load gradually decreases with time until it falls to a threshold value , the voltage trigger unit 2022 sends out the first or second control signal. Taking this figure as an example, the controlled discharge path 2021 is mainly completed by a metal-oxide-semiconductor transistor, the gate of which is electrically connected to a second clock signal that is synchronized with or associated with the system clock CLK, and the drain of which is It is electrically connected to the first load wire 2011 , and its source is electrically connected to a ground point. The component size and circuit characteristics of the metal-oxide-semiconductor transistor can simulate a certain transistor that is grounded among the four transistors in the latch unit 10 in FIG. 1 . As for the voltage trigger unit 2022, it can be implemented by a NOT gate as shown in the figure, the input end of which is connected to the first load wire 2011 in series, and the output end is used to output the control signal.

Therefore, when the controlled discharge path 2021 is triggered by the second clock signal that is synchronized with or related to the system clock CLK and is turned on, the adjustable electrical load 201 will start to change from the first level range (this embodiment is a high voltage level) and start discharging until the voltage is low enough to trigger the NOT gate to output the high level control signal to the subsequent circuit, because when the word line of the first port in the same word line group and the second port When the voltage values of the word lines are all in the first level range, the first load wire 2011 will be electrically connected to the second load wire 2012, and then the adjustable electrical load 201 will be changed from the first load wire 2012 with a smaller value. The load value is adjusted to the second load value with a larger value. On the contrary, when the voltage values of the word line of the first port and the word line of the second port in the same word line group are not all in the first level range, the The first load wire 2011 and the second load wire 2012 are kept disconnected, so that the adjustable electrical load 201 is maintained at the first load value with a smaller value. Therefore, the second control signal will be sent later due to the longer discharge time in the state of larger load value, and the first control signal will be sent earlier in the state of smaller load value due to shorter discharge time.

The above-mentioned control signal is sent to the clock signal generator 21 for reference, so as to adjust the time (or pulse width) of the first clock signal sent to the group of word lines in the first level range, for example, Switching from the first level range to the second level range in response to the triggering of the first or second control signal, for example, switching the original high potential to a low potential, so that in a state with a large load value, it will be sent later The second control signal of the second control signal will cause the high level time of the first clock signal on the character line to be longer, and in the state of the smaller load value, the first control signal issued faster will make the first clock signal on the character line The high-level time of the first clock signal is relatively short, so that the pulse width can be effectively adjusted to achieve the purpose of saving power.

In addition, the above-mentioned control signal can also be transmitted to the bit line data sensing device 29 shown in FIG. The control signal generator 202 in the state detection device 20 and a set of bit lines (not shown in this figure) in the random access memory, the bit line data sensing device 29 is used to be activated due to the triggering of the control signal Enable (enable), so as to reduce the time when the bit line in the random access memory is at the first level voltage value, so as to reduce power consumption and achieve the purpose of power saving.

For clear description, please refer to the schematic diagram of waveforms shown in Figure 3, which is after applying the pulse width adjusting device of the present invention, under three different states, the first port word lines WLA[N], ..., WLA[0 ] and the embodiment waveform diagrams on the second port word lines WLB[N], ..., WLB[0], wherein in the period of state A, the word lines belonging to different groups are simultaneously controlled by the second level voltage The value is pulled to the first level voltage value, for example, the signals on WLA[N] and WLB[0] are pulled from the low level to the high level at the same time, ready to correspond to two static random access memory cells The bit line (not shown in the figure) performs data reading or writing, but this state does not match the voltage values of the word line of the first port and the word line of the second port in the same word line group are both at the first level at the same time Therefore, the adjustable electrical load 201 is still maintained at the first load value.

In the period of state B, when the voltage values of the first port word line and the second port word line in the same word line group are different, the second level is pulled to the first level, such as WLA[N] and WLB The voltage value of the signal on [N] is pulled from the low level to the high level without overlapping, ready to perform data on the two-bit line corresponding to a static random access memory unit (not shown in the figure) The action of reading or writing, and this state does not meet the condition that the voltage values of the first port word line and the second port word line in the same word line group are in the first level range at the same time, so the adjustable electrical load 201 is still maintained at the first load value.

In the period of state C, the voltage values of the word line of the first port and the word line of the second port in the same group of word lines are all pulled from the second level to the first level, such as WLA[N] and WLB[ There is an overlapping time between the voltage values of the signal on N] that are both at the high level at the same time, which is used to prepare for data reading or data reading of the two lines corresponding to a certain static random access memory unit (not shown in the figure). The action of writing, and this state conforms to the condition that the voltage values of the word line of the first port and the word line of the second port in the same word line group are in the first level range at the same time, so on WLA[N] and WLB[N] When the voltage values of the signals are both at the high level for an overlapping time, the adjustable electrical load 201 is switched to the second load value. The clock signal generator 21 responds to the phenomenon that the discharge speed slows down caused by the second load value (the waveform slopes of the first load wire RBLA and the third load wire RBLB in the state C become smaller), and then control according to the slower generation. signal and lengthen the time length of the voltage value of the clock signal sent to the group of word lines in the first level range (high level in this example) to cope with a corresponding static random memory at this time The two bits of the memory unit (not shown in the figure) are charged and discharged at the same time, and the speed is slow due to a large load. The charging and discharging waveforms can be seen in the figure as shown in the first load wire RBLA and the third load wire RBLB.

In this way, in state C, since there will be an overlapping time during which two bit lines need to be charged and discharged at the same time, it is in a state with a relatively large load. At this time, the clock signal generator 21 can adjust the electrical load 201 according to The clock signal generated corresponding to the presented load value and sent to the group of word lines, the time length for which the voltage value is in the first level range (high level in this embodiment) can be set as shown in the figure The longer time is used to cope with the slow charging and discharging speed of the bit line. However, in states A and B, since there are no two bit lines that need to be charged and discharged at the same time, they are in a state with a small load. At this time, the clock signal generator 21 can adjust the load presented by the electrical load 201 Value corresponding to the clock signal generated and sent to the group of word lines, the length of time it is in the first level range (high level in this embodiment) can be set to a shorter time, which will avoid Excessive power consumption can also reduce the risk of data reversal or loss due to external environmental interference caused by the long turn-on time of the word line. Therefore, the present invention can improve the technical deficiencies of the conventional multi-port SRAM and its read-write circuit.

Please refer to FIG. 4 , which is a schematic diagram of another preferred embodiment of the above-mentioned adjustable electrical load 201, which mainly includes two sets of load wires and controlled switching devices, including a first load wire RBLA and a second load wire RBLA. ', the controlled switching device 41 and the third; the fourth load wire RBLB, RBLB' and another group of controlled switching device 42, wherein the first load wire RBLA is electrically connected to the clock signal generator 21, and controlled The switch device 41 is electrically connected to the first port word lines WLA[N], . . . , WLA[0] and the second port word lines WLB[N], . and the second load wire RBLA', which is in response to the voltage values of the first port word line and the second port word line in a certain group of word lines being in the first level range (in this embodiment, the high level ), the first load wire RBLA is electrically connected to the second load wire RBLA', so that the adjustable electrical load 201 is adjusted from the first load value to the second load value, otherwise, each group When the voltage values of the word line of the first port and the word line of the second port among the word lines are not all in the first level range, the first load wire RBLA and the second load wire RBLA' will keep disconnected, and then Keep the adjustable electrical load 201 at the first load value. The circuit layout of the first load wire RBLA and the second load wire RBLA' can be similar to that of the bit lines BLA and BLB of the static random access memory unit (not shown in the figure) as far as possible, so that the first The load value of the load wire RBLA and the second load wire RBLA' can be close to the equivalent load value of any bit line in the dual-port random access memory.

The controlled switching device 41 may include a first metal oxide semitransistor MA and a second metal oxide semitransistor MB, the gate of the first metal oxide semitransistor MA is electrically connected to the first port word lines WLA[N], . . . WLA[0], its source is electrically connected to the first load wire RBLA, and the gate of the second metal-oxide-semiconductor transistor MB is electrically connected to the second port word line WLB[N], . . . WLB[0], its source is electrically connected to the second load wire RBLA', and its drain is electrically connected to the drain of the first metal oxide semiconductor transistor MA. In this way, the action of the above-mentioned controlled switching device 41 and the schematic diagram of the waveform on the RBLA shown in FIG. 3 can be completed, thereby improving the lack of conventional means, and the control of the adjustable electrical load 201 electrically connected in FIG. 2D The signal generator 202 is electrically connected to the RBLA for generating a control signal corresponding to the word line WLA of the first port according to the voltage change on the RBLA. In addition, another group of controlled switch devices 42 and the third and fourth load wires RBLB and RBLB' in the adjustable electrical load 201 are mainly set corresponding to the requirements of the word line of the second port, so that , another group of control signal generators 202 can generate a control signal corresponding to the second port word line WLB according to the voltage change on RBLB. Of course, if there are character lines with a third port or more ports, the control signal generators can be set corresponding to the number of ports.

Please refer to FIG. 5 again, which is a circuit block diagram of another preferred embodiment of a pulse width adjustment device developed by the present invention. The difference from the previous embodiment is that the state detection device 50 does not use The electrical load 201 and the controlled switching device can be adjusted, but the logic circuit device 500 is used to complete the judgment. The logic circuit device 500 mainly responds to the first port word lines WLA[N],... When the voltage value and the voltage value on the word lines WLB[N], . The generator 51 is used to generate a clock signal sent to the group of word lines. The time length of the clock signal in the first level range is changed according to the control signal. The waveform change is shown in FIG. 3 for example. So no more details. The logic circuit device 500 is used for sending the first control signal to the clock signal generator when the voltage values of the word line of the first port and the word line of the second port are both in the first level range at the same time, and then When the voltage values of the first port word line and the second port word line are not both in the first level range at the same time, a second control signal is sent to the clock signal generator. The logic circuit device 500 can be implemented with an AND gate or similar logic gate. In addition, this case can also be widely applied to memory cells with three ports or even more ports, only the devices related to the number of ports, for example, in the embodiment of three ports, the logic circuit device 500 will be used to detect When the two ports or the three ports are all in the first level range at the same time, different control signals are sent, so that the time length for the clock signal sent to the group of word lines to be in the first level range is changed, The principle is that the more ports are in the first level range at the same time, the longer the clock signal is in the first level range, and the details will not be repeated here.

The above disclosures are only preferred embodiments of the present invention, and certainly cannot limit the scope of rights of the present invention. Therefore, equivalent changes made according to the claims of the present invention still fall within the scope of the present invention.

Claims (15)

1. A pulse width adjustment device, applied in an N-port random access memory, where N is greater than or equal to 2, and the N-port random access memory has complex word lines, at least one of the complex word lines N port word lines are included in the group word line, it is characterized in that, described pulse width adjusting device comprises: A state detecting device, used for correspondingly sending out a first control signal in response to the voltage value of the character line of the first port and the voltage value of the character line of the second port being in a first level range; and A clock signal generator, electrically connected to the state detection device and the group of word lines, for generating a first clock signal sent to the group of word lines, the first clock signal is located in the group of word lines The time length of the first level range is changed according to the first control signal. 2. The pulse width adjustment device according to claim 1, wherein the N-port random access memory is an N-port static random access memory, wherein each group of word lines includes N ports respectively character line. 3. The pulse width adjustment device according to claim 1, wherein the state detection device comprises a logic circuit device electrically connected to the word line of the first port and the word line of the second port , for sending the first control signal to the clock signal generator when the voltage values of the first port word line and the second port word line are both in the first level range, and Sending a second control signal to the clock signal generator when the voltage values of the first port word line and the second port word line are not both in the first level range. 4. The pulse width adjustment device according to claim 3, wherein the logic circuit device is an AND gate, and its input terminals are electrically connected to the word line of the first port and the word line of the second port respectively. The word line, the output end of which outputs the control signal to the clock signal generator. 5. The pulse width regulating device according to claim 1, wherein the state detecting device comprises: An adjustable electrical load, the adjustable electrical load is electrically connected to the word line of the first port and the word line of the second port, and is used for corresponding to the voltage value of the word line of the first port and the word line of the first port When the voltage values of the character lines of the second port are all in the first level range, adjusting from a first load value to a second load value; and A control signal generator, electrically connected to the adjustable electrical load, for correspondingly generating the control signal in response to the second load value. 6. pulse width regulating device as claimed in claim 5, is characterized in that, described adjustable electrical load comprises: a first load wire electrically connected to the control signal generator; a second load lead; and a controlled switching device, electrically connected to the first port word line, the second port word line, the first load wire and the second load wire, for responding to the first port word line When the voltage value of the character line of the second port is within the first level range, the first load wire is electrically connected to the second load wire, so that the adjustable electrical load is controlled by the The first load value is adjusted to the second load value; on the contrary, when the voltage values of the word line of the first port and the word line of the second port are not both in the first level range, the An open circuit is maintained between the first load wire and the second load wire, thereby maintaining the adjustable electrical load at the first load value. 7. The pulse width adjustment device according to claim 6, wherein the load value of the first load wire or the second load wire is substantially equal to one of the N-port random access memory Equivalent load value of the bit line. 8. The pulse width regulating device according to claim 6, wherein said controlled switching device comprises: a first metal-oxide-semiconductor transistor, the gate of which is electrically connected to the first port word line, and the source of which is electrically connected to the first load wire; and A second metal oxide semitransistor, its gate is electrically connected to the word line of the second port, its source is electrically connected to the second load wire, and its drain is electrically connected to the first metal oxide The drain of the half transistor. 9. The pulse width regulating device according to claim 5, wherein the control signal generator comprises: A controlled discharge path, electrically connected to the adjustable electrical load, used to provide the adjustable electrical load to perform a discharge action in a specific time, so that the voltage on the adjustable electrical load decrease in value; and A voltage trigger unit, electrically connected to the adjustable electrical load, is used for sending out the control signal when the voltage on the adjustable electrical load drops to a threshold value. 10. The pulse width modulation device according to claim 9, wherein the controlled discharge path comprises a third metal oxide semiconductor transistor, the gate of which is electrically connected to a second clock signal, and the drain of which The electrode is electrically connected to the first load wire, and the source thereof is electrically connected to a ground point. 11. The pulse width adjustment device according to claim 9, wherein the voltage trigger unit is a NOT gate, the input end of which is connected to the first load wire in series, and the output end is used for output the control signal. 12. The pulse width adjustment device according to claim 5, wherein the first clock signal generated by the clock signal generator and sent to the group of word lines is at the first level The state of the range is switched to a second level range in response to the triggering of the control signal. 13. The pulse width adjustment device according to claim 1, wherein the control signal sent by the state detection device is transmitted to a bit line data sensing device, and the bit line data sensing device The device is electrically connected to the state detection device and a set of bit lines in the N-port random access memory, and the bit line data sensing device is used to be enabled in response to the triggering of the control signal. 14. A pulse width adjustment device, applied in a static random access memory, the static random access memory has a plurality of groups of word lines, at least one group of word lines in the plurality of groups of word lines includes at least one first A port word line and a second port word line, characterized in that the pulse width adjustment device includes: A state detection device, used for correspondingly performing the corresponding operation according to a first load value in response to the voltage value of the character line of the first port and the voltage value of the character line of the second port being in a first level range Discharging is adjusted to discharge according to a second load value; and A clock signal generator, used to generate a first clock signal sent to the group of word lines, the time length of the first clock signal in the first level range is at least according to the first load value or the discharge time of one of the second load value. 15. The pulse width adjustment device according to claim 14, wherein when the voltage of a first load wire of the state detection device discharges to a threshold value, a control signal is sent to the clock The signal generator is used to determine the time length during which the first clock signal is in the first level range.